JPS5823472A - Semiconductor device - Google Patents

Abstract

PURPOSE:To protect input even under the conditions of surge, discharge time thereof is long, and the opening of a power supply terminal by forming PNPN elements at the input side of a semiconductor circuit, input thereto must be protected. CONSTITUTION:An N<+> type buried layer 12 is formed to a P type substrate 11, and an N type epitaxial layer 13 is shaped onto the layer 12 through vapor growth. An N type island 13' is formed through selective P<+> type isolation and diffusion and the formation of an isolation diffusion layer 14. The base of a normal NPN transistor is diffused to the island 13' while at least two P type diffusion regions 151, 152 mutually separated are molded. An N<+> type diffusion region 16 is shaped by diffusing an N<+> type impurity into the emitter region 152 of a lateral PNP transistor. Contact holes are formed to an insulating film 17 on the regions 151, 16, and electrodes 181, 182 are taken out. Accordingly, the region 151 is connected to the signal input terminal of the semiconductor circuit, input thereto must be protected, and the region 16 is connected to ground.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit and a semiconductor device that takes input protection measures.

Figure 1 shows a conventional differential amplifier circuit with input protection measures.
is a current limiting resistor provided between the input pin (terminal) 1 and the transistor TEJ, Dl is a surge protection diode provided between the input pin 1 and ground, and R*#R1 is the transistor TE1. Te2: This is a transistor and a resistor connected between the collector and the power supply VCC.

Conventionally, in a differential amplifier circuit as shown in FIG. 1 and other semiconductor circuits, a diode-1'DJ and a resistor IL are used to prevent damage to the F-tun transistor due to a surge from the input f-n1.
1 is inserted.

This current limiting resistance I! 1 is Nw in an integrated circuit device
It is made by diffusing into the epitaxial layer at the same time as the pace diffusion, and is a bpsi resistor], and since the normal power supply VCCO potential is applied to the islands of the above Nll engineering female taxial layer, the power supply circuit is drawn. It will be as shown in Figure jI2. That is, the negative surge applied to input 1 flows to ground through diode DI. In this case, the potential of input bin 1 is lower than ground by forward voltage v1 of diode D1. Also, for positive surge, it passes through resistor R1 and this R
The potential of input bin 1 at this time is equal to the power supply voltage VCC plus the forward voltage Vf of the diode D2 formed by the resistor 81 and the island. Become. In this way, the conventional surge protection circuit is configured to clip surges by the potential difference between the power supply VCC and the ground.

However, it is thought that the reason why a transistor is destroyed in an actual WAt voltage is not due to the peak voltage but because power is concentrated in a part of the junction for a relatively long period of time. That is, Δwar is concentrated in a part of the PN & joint, and a high temperature region is formed locally. Silene melting (M
@lting) occurs and the recrystallized @fPN junction is destroyed, or abnormal diffusion of impurities occurs in the high temperature region and the junction is destroyed. For this reason, the conventional circuit that only clears the peak voltage does not function as a protection circuit against surges with relatively long discharge times, and the power supply is connected to the integrated circuit. (if the potential of the power supply VCC is not applied to the island of the N-type epitaxial layer), for a positive surge, the VC
Since the C voltage is determined by the breakdown voltage of the device, a relatively high voltage may be applied.

The present invention has been made in view of the above-mentioned circumstances. By providing a PNPN element on the input side of a semiconductor circuit to which input protection is to be performed, it is possible to protect the input from surges with long discharge times and even when the power supply terminal is open. The purpose of this invention is to provide a semiconductor device that enables this.

An embodiment of the present invention will be described below with reference to the drawings. First, as shown in FIG. 3, an N''!Ill-containing layer 12 is formed on a P-type substrate 11, and an N''!Ill-containing layer 12 is formed thereon by vapor phase growth. By performing the separation diffusion of y and forming the separation diffusion layer 14,
An island 11 of ril is formed. Is there a normal NPN on this island JJ'? Simultaneously with the pace diffusion of the sensor, at least two pm diffusion regions Is1, Isg separated from each other
will be established. At this time, the spaced area 1! It, IB.

The separation interval must be large enough to obtain a sufficient current amplification factor hv as a tunister (2-chiral PNP). This lateral PNP) Tunjista's work 2
．． An N + type diffusion region 16 is provided by diffusing an N type impurity into the target region 153 . Then area 15. ．． A contact hole is provided in the insulating film 11 on the electrode 18 . ．． 1g is taken out, so that region 151 is connected to the signal input end of the semiconductor circuit for input protection, and region 16 is connected to ground.

The semiconductor circuit side using the input protection element SCR1 having the configuration shown in FIG. 3 is shown in FIG. 4. Note that the differential amplifier circuit in this figure is an example in which it corresponds to the one in FIG. 1. Corresponding parts are denoted by the same reference numerals and their explanation will be omitted. However, in the circuit of FIG. 4, when looking from the input terminal 1 to the ground side, the PNPN element 8CR1 of FIG. 3 is interposed therebetween. The characteristics of the PNPN element have a negative resistance region as shown in FIG. When a positive voltage is applied to the input side and a negative voltage is applied to the ground side, the PNPN element turns on when the break-over Δ voltage is exceeded, and the forward impedance becomes extremely small. The impedance at this time is approximately equal to the normal PNN Kanakura forward impedance. Further, until the turn-on voltage is reached, the impedance between the input side and the ground is equal to the reverse impedance of the PN junction, so below the breakover voltage, the input bin 1 and the ground are completely separated in terms of the circuit.

In the circuit shown in FIG. 4, when a large positive surge is applied to the input bin 1, the PNPN element SCR1 turns on, causing the surge current to flow to ground. When the surge disappears, HaMeikyoko 8CRf turns off and returns to normal usage. Only when a positive surge voltage is applied like this, the PNPN
The element SCR1 has a low impedance, and the PNPN
In a normal NPN transistor, which plays the role of suppressing heat generation in the element and protecting the input element, even if a surge is applied to the PACE, E, or Y junction, which is the most susceptible to surges, the PACE, E, or R junction will be destroyed. Minimum of -
The resulting power is much greater than the product of the breakover voltage and breakover current of the PNPN device. For this reason, it sufficiently operates as a protection element even against instantaneously applied high potential, resulting in a good surge protection circuit. ttaPNPN
Since the element SCR1 is turned on by a positive surge, the power supply VC is connected to the Nfi epitaxial layer forming the island resistor R1.
Even if C is not added, no problem will occur.

Note that the present invention is not limited to the above-mentioned embodiments, and can be applied in various ways. For example, in FIG. 3, the present invention can be applied to a structure in which the conductivity of each semiconductor layer is reversed. In addition, in the embodiment, the input side of the semiconductor circuit provided with the input protection element is connected to the pace electrode of the input transistor or the pace electrode of the input transistor through the current limiting resistor, but the collector of the input transistor or the input side is connected to the pace electrode of the input transistor through the current limiting resistor. It can be applied in the same way even if

As explained above, according to the present invention, since the K PNPN element is provided on the input side of the semiconductor circuit, even if there is a surge with a long discharge time or the power supply of the integrated circuit is in an open state,
A semiconductor device that enables input protection of a semiconductor circuit can be provided.

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams of conventional differential amplifier circuits with input protection, Figure 3 is a configuration diagram showing an embodiment of the present invention, and Figure 4 is a differential amplifier circuit using the same configuration. Figure 5 shows I of the same configuration.
-V characteristic diagram. 1... Input ♂ (terminal), 11... pm board, 12
...N'' mm layer, 13...Nll epitaxial layer, 11...Island, 14...P+ type separation layer, 151
. 151-...P type layer, 1#...-N+ vote layer, 11...
Insulating film, 111%, 11g-・electrode, 5CRJ・-PN
PN element.

Claims (1)

[Claims] a first conductive semiconductor substrate; a second conductive epitaxial layer formed on the substrate; a second conductive buried layer formed between the layer and the substrate; a separation layer of a first conductive plate formed by separating a part of the epitaxial layer to form an island; and a first conductive plate formed on the height at a distance from each other. a second region and a third region of the second conductive Wi formed on the second region, and the region [1] is connected to the signal input side of the semiconductor circuit that performs input protection. A semiconductor device, wherein the third region is connected to a ground side.