JPS5823100U - Long-term voltage holding sample and hold circuit - Google Patents

Long-term voltage holding sample and hold circuit

Info

Publication number
JPS5823100U
JPS5823100U JP11449581U JP11449581U JPS5823100U JP S5823100 U JPS5823100 U JP S5823100U JP 11449581 U JP11449581 U JP 11449581U JP 11449581 U JP11449581 U JP 11449581U JP S5823100 U JPS5823100 U JP S5823100U
Authority
JP
Japan
Prior art keywords
long
hold circuit
voltage holding
holding sample
term voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11449581U
Other languages
Japanese (ja)
Inventor
広野 勝
野口 亘
Original Assignee
日立電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立電子株式会社 filed Critical 日立電子株式会社
Priority to JP11449581U priority Critical patent/JPS5823100U/en
Publication of JPS5823100U publication Critical patent/JPS5823100U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来のサンプルホールドの構成図、第2図は
、本考案の−・実施例のサンプルホールドの構成図であ
る。 1・・・人力値9シ・電圧、2・・・スイッチ、3・・
・基準電IEまたはアース、4・・・・・・コンデンサ
、5・・・増幅器、6・・・制御信号、7・・・スイッ
チ。
FIG. 1 is a block diagram of a conventional sample hold, and FIG. 2 is a block diagram of a sample hold according to an embodiment of the present invention. 1...Manpower value 9/voltage, 2...switch, 3...
-Reference voltage IE or ground, 4...Capacitor, 5...Amplifier, 6...Control signal, 7...Switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] スイッチとコンデンサを有する長時間電圧保持サンプル
車、−ルド回路において、前記=Jコンデンサ子がアー
スまたは基準電圧から切りはなされる手段を具備したこ
とを特徴とするサンプルホールド回路。
1. A sample and hold circuit for long-time voltage holding sample and hold circuits having a switch and a capacitor, characterized in that the =J capacitor element is provided with means for being disconnected from ground or a reference voltage.
JP11449581U 1981-08-03 1981-08-03 Long-term voltage holding sample and hold circuit Pending JPS5823100U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11449581U JPS5823100U (en) 1981-08-03 1981-08-03 Long-term voltage holding sample and hold circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11449581U JPS5823100U (en) 1981-08-03 1981-08-03 Long-term voltage holding sample and hold circuit

Publications (1)

Publication Number Publication Date
JPS5823100U true JPS5823100U (en) 1983-02-14

Family

ID=29908770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11449581U Pending JPS5823100U (en) 1981-08-03 1981-08-03 Long-term voltage holding sample and hold circuit

Country Status (1)

Country Link
JP (1) JPS5823100U (en)

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