JPS5822838B2 - Sequential circuit with non-volatile memory function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to sequential circuits such as various counters and shift registers, and particularly to a sequential circuit having a nonvolatile memory function.

In the field targeted by the present invention, "Non-volatile decimal 4-digit MNOS counter" announced by the present inventors (1975 Institute of Electronics and Communication Engineers National Conference, A4),
8).

The configuration of one bit of this counter is shown in FIG.

In the same figure, MT. MT2 is a P-channel MNOS memory transistor, and when a positive erase voltage pulse of (+25V, 1m5ec) is applied to its gate with respect to the substrate, the threshold of the MNOS memory transistor moves in the positive direction to a high-level threshold state (+2V ).

Conversely, when a negative write voltage pulse of (-25V, 1 m5ec) is applied to the gate of the MNOS memory transistor with respect to the source potential, the threshold value moves in the negative direction and becomes a low-level threshold state (-6V).

In FIG. 1, TRI to TI2 are enhancement type P-channel MO8) transistors, and T, 3°TI4 is a depletion type P-channel MOS transistor as a load.

When the power supply VDD is in the ON state, the MOS
Transistor T1. .

T1□ becomes conductive, and the circuit in Figure 1 is a normal MO8.
Shape counter operation.

While the power is on, an erase voltage pulse is applied to the gate of the MNOS memory transistor at an appropriate time to set it in the erase state.

When a power cutoff is detected, a write voltage pulse is applied to the gate line MG, and the MNOS memory transistor M
Writing occurs to the T12MT2 whose source potential is at a high level, and the source potential of the other memory transistor is at a low level (for example, VDD - -20V), so only about -5V is applied between the gate and channel. Therefore, writing is prohibited.

As a result, the information contained in this bit is transferred to the MNOS
It is stored non-volatilely in the memory transistor even when the power is off.

During the transition period when the power supply returns to the ON state, the power supply VDD
Information from the MNOS memory transistor is read by applying a gradient potential of the same potential to the gate line MG.

MNOS memory transistor MT. The source potential of MT2, that is, the node potential of Qi and Qi, is the voltage obtained by subtracting the threshold voltage of each MNOS memory transistor from the potential applied to the gate, and among these, the one with a more negative value is the voltage applied to the cross connected to these. Combined MOS
) Make one of the transistors T, , T2 conductive first.

and MOS) transistor T11. When T]2 is made conductive, the potentials of Qi and Qi are set corresponding to the information held by the MNOS memory transistors MT, MT2.

In FIG. 1, a circuit constituted by MOS transistors T3 to TIO is an auxiliary circuit for performing a counting operation, and TI5 is a reset transistor.

If Ql-1 is now at a low level, the capacitance C1, C
2 is a conductive MOS transistor T7. They are charged to the node potential of Qi and Qi through T8, respectively.

At this time, Q 1- ] is at a high level, so the MOS
) transistor T5. T6 is in a non-conductive state.

After that, Q '1-1 becomes high level, and at the same time glance -1
becomes low level, MOS) transistor T7. T
8 is in a non-conductive state, and the capacitances C1 and C2 are connected to the node Q.
Although it is disconnected from i and Qi, it is already charged and maintains the same potential.

On the other hand, MO8 transistor T5. Since T6 becomes conductive, MOS) transistor T3. T5 or MOS transistor T4. Either one of the DC current paths T6 is formed, and the bits of this binary counter are in a state that is inverted from the previous state.

In this way, the circuit shown in Figure 1 is a complete combination of a flip-flop circuit that exchanges nonvolatile information and a circuit that has a counting function, making it possible to hold the count value in a nonvolatile manner even when the power is turned off. It constitutes a counter circuit.

By cascading the circuits shown in FIG. 1, an n-ary (ri>1) up counter can be constructed.

However, it is extremely difficult to combine the circuit shown in FIG. 1 with a logic circuit to construct a counter (generally a sequential circuit) having a down-counting function or an up-down counting function.

This is due to bit-to-bit interference effects that occur when non-volatile information is restored.

When the circuit of FIG. 1 is combined with a logic circuit for use as a sequential circuit, when the information in the MNOS memory transistor is restored, the information in the MNOS memory transistor is gradually read out, but the logic circuit connected to it is read out gradually. Because the output characteristics have a certain fixed threshold value, the signal changes suddenly in a non-monotonic manner, and this logic circuit output (changes suddenly in a non-monotonic manner)
is added as an input signal to another bit, and acts as a count input to that bit.

Therefore, in general, in order to construct a nonvolatile sequential circuit, a new technique that does not have such interference effects between bits is desired.

It should be noted here that in the n-ary up counter configured by cascading the circuits shown in FIG. Similar MNO in the previous stage
Since the information Qi-1゜Q'1-1 as an input is always a slope signal that changes monotonically from the ground potential (Vss) level, it changes as the information is read from the S memory transistor. No interference effects occur.

However, this condition cannot be satisfied in general sequential circuits.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sequential circuit having a non-volatile memory function without interference effects between bits.

The present invention provides, in a sequential circuit having a non-volatile memory function, multiple memory cells are provided independently without being mixed in the sequential circuit, corresponding to the sequential circuit and each bit of the sequential circuit,
It is characterized in that bidirectional information transfer is performed independently between each bit of the corresponding sequential circuit and the multiplexed memory cell.

In this invention, each bit of the sequential circuit and the multiple memory cell are provided independently, and bidirectional information transfer between each bit of the sequential circuit and the multiple memory cell is performed independently, so that interference between bits is prevented. does not occur.

Further, the multiple memory cell according to the present invention is capable of holding at least two types of information.

The sequential circuit in the present invention means a sequential circuit that can be set in parallel, and is typified by, for example, an up counter, a down counter, an up/down counter, a shift register, a ring counter, and a frequency dividing circuit, and also has various other arithmetic functions. It also includes sequential circuits.

First, an embodiment of the present invention will be described with reference to FIG.

In the figure, sequential circuit 100 includes bits B1. B2. -B
It is composed of m stages (m≧1).

Each pin 1-Bl to Bm is comprised of a presettable flip-flop.

Flip-flops B1-Bm have corresponding multiple storage cells S1-Sm, respectively.

Each multiple memory cell consists of a bistable circuit incorporating one pair (l≧1) of non-volatile memory elements, and one bit of circuit (volatile) information is stored in the bistable node potential of the bistable circuit.
It is possible to store multiple (1+1 bit) binary information consisting of physical information of a 1-bit non-volatile memory element, and also provides means and physical properties for writing circuit information to the non-volatile memory element as physical information. and means for reading physical information into the bistable circuit as circuit information.

Further, the bits B1 to Bm constituting the sequential circuit 100 and the corresponding multiple storage cells S1 to Sm are mutually independent information transfer means, that is, Bi→5i (i=1, .
. . , m) for information transfer, and Si-+Bi (i=1, . . . , m) parallel set means for information transfer.

With the above circuit configuration, it was possible to completely eliminate the interference effect between bits during the transition when nonvolatile information is returned to the sequential circuit.

That is, in FIG. 2, each multiplexed storage cell remains completely independent of the sequential circuit and other multiplexed storage cells when its non-volatile information is restored as circuit information within the multiplexed storage cell.

Since the information thus restored can be further set in parallel to the sequential circuit, the interference effect between bits can be completely eliminated.

According to this embodiment, the sequential circuit itself only needs to have a parallel set input, and the configuration of a conventional (volatile) sequential circuit can be used as is.

In addition, parallel setting of nonvolatile information restored to multiple memory cells to the sequential circuit is possible at any time.
Moreover, since it can be carried out in a completely short time circuit-wise, the operation of the sequential circuit is not impaired.

FIG. 3 is a circuit diagram of the embodiment shown in FIG. 2.

The sequential circuit 100 consists of a flip-flop Bi, which is the first component, and a multiple memory cell Si provided corresponding thereto.

In the figure, 1 to 4 and 7 to 12 are P-channel enhancement type MO8 transistors, and their threshold values are set to -1.5V.

5 and 6 are P-channel deflection type load MO8 transistors whose threshold value is +5.

Mll to Ml and Ml2 to Ml2 (l≧1) are 1
A pair of MNOS memory transistors.

3 and 4 are switching transistors, and when these are made conductive, a bistable circuit is formed in which 1 and 2 are cross-coupled driver transistors and 5 and 6 are load transistors.

Output points Qi and Qi of this bistable circuit are connected to preset input terminals i and Ti of a flip-flop Bi, which is a component of the sequential circuit 100, respectively.

The gates of transistors 9 and 100 are commonly connected to the parallel set input signal line Ps, while the gates of transistors 9 and 8 are connected to the output terminal Q of the flip-flop Bi, respectively.
i, connected to Qi.

Further, the gates of transistors 11 and 120 are both connected to signal line (2).

The signal line pb sets the information of the output points Qi and Qi of the multiple writing cell Si in parallel to the sequential circuit, and plays a role opposite to that of the signal line Ps.

Next, the connection state inside the memory cell Si will be explained.

The gate of transistor 1 is connected to the drain of transistor 2, while the gate of transistor 2 is connected to the drain of transistor 1.
Connect to the drain of

The sources of transistors 1 and 2 are both connected to ground potential Vss.

The drains of transistors 1 and 2 are respectively output points Qi,
Connect to Qi.

Further, the gate and source of the transistor 5.6 are connected in common to the drains of the transistors 3 and 4, respectively.

The sources of transistors 3 and 4 are connected to output points Qi and Qi, and their respective gates are both connected to signal line K.

MNOS) Transistors MH to M11 are transistors 3
Similarly, the MNOS transistors M12 to M1□ are connected in parallel to the transistor 4.

MNOS) transistors M and Mj2 (j-1,...
, 1 (2) are commonly connected to the signal line MGj.

Transistors 9 and 7 are connected in series between the output point Qi and the ground potential, and transistors 10 and 8 are connected in series between the output point Qi and the ground potential.

The drains of the transistors 11 and 12 are connected to the gate of the transistor 1 and the gate of the transistor 2, respectively, and the sources of the transistors 11 and 120 are connected to the ground potential Vss.

To explain the operation of the circuit shown in FIG. 3, the operation within the multiple memory cell is performed when the transistors 9 and 10 are rendered non-conductive by the signal Ps.

The operation at this time is similar to that described in FIG.

First, the power supply VDD--20V and Vss=OV.

Furthermore, a model of the hysteresis characteristics of the MNO8) transistor is shown in FIG.

That is, when a +25V, 1 msec pulse is applied to the gate of the MNOS transistor with respect to the substrate, the threshold value moves in the positive direction to -2V.

Conversely, the gate voltage is -23V, 1 m with respect to the source potential.
When a pulse of sec is applied, the threshold value moves in the negative direction to -6V.

When the effective gate applied voltage VG, that is, the absolute value of the above voltage pulse applied to the gate, is 15 V or less, it is within the shoulder range of the hysteresis characteristic, and no change in the threshold value occurs.

FIG. 5 is a timing chart of an example of a signal group for operating the circuit of FIG.

In the figure, H represents a high level (for example, OV), and L represents a low level (for example, -5V).

The operation of the circuit shown in FIG. 3 can be roughly divided into two modes.

One is a sequential circuit operation in which the flip-flop Bi is exactly like in a conventional sequential circuit, and the other is a multiple memory cell operation.

The multiple memory cell operation constitutes the main part of the present invention, and includes the operation of setting the physical information stored in the multiple memory cell Si to the flip-flop in the multiple memory cell Si, and the circuit included in the flip-flop Bi. It has the operation of setting the target information to the multiplexed storage cell Si.

Although FIG. 3 shows the configuration of one bit of the sequential circuit, in the operation described below, all the bits forming the sequential circuit shown in FIG. 2 operate in parallel.

Time t.

When the signal line NR changes from H level to L level, transistors 11 and 12 in multiple storage cell Si become conductive, and the output point potential of Qi and Qi goes to Vss level (O
V).

At this time, the signal line changes from the L level to the H level, and the signal line Ps is kept at the H level, so the transistors 3, 4, 9, and 10 are in a non-conductive state.

Next, at time t1, the signal line NR is set to H level,
A read signal 50 is supplied to one of the signal lines MG to MGl, MGj.

As shown in FIG. 5, the readout signal 50 can be a -1, OV ramp signal or a -6V constant voltage pulse.

By the readout signal 50, the physical information of the MNOS transistor pair Mj, , Mj2 is transferred to the output point Qi, as in FIG.
, Qi.

That is, the threshold value v of MNO8) transistor M・2M・
Mj1. Regarding VMj2, Jl j2 (VMj+5VMj2) - (VMH+ VML)
If (VMH; high level e.g. -2V, VML; low level e.g. -6V), transistor 2 conducts first (Q
i.

Qi)-(L,H).

Inverse K (VM jI 7 vM j2 )−(vML,
VMH), then (Qi, Qi)-(H.

L).

In this manner, the read signal 50 causes information written to any one of the MNO8 transistor pairs to be returned to the bistable circuit in the multiple storage cell.

At time t2, when the read signal 50 ends, the signal line K is brought to the L level, so that the transistors 3 and 4
conducts, and the bistable circuit in the multiplexed storage cell reaches the output point Qi
, holds the information returned to Qi.

Thereafter, by setting the signal line pb to L level between times t3 and t4, the information on the output points Qi and Qi is set in the flip-flop Bi of the sequential circuit via the preset input terminals Ii and Ii.

Other flip-flops in the sequential circuit are similarly set in parallel.

The sequential circuit operates as a normal volatile sequential circuit from time t5 using the data information set in parallel in this manner as an initial value.

By stopping the sequential circuit operation at an arbitrary time t6 and performing the multiple storage cell operation again, the data information stored in the sequential circuit at that time can be stored in a nonvolatile manner.

First, when the signal line Ps is set to the L level between times t7 and t8, the transistors 9 and 10 become conductive.

Therefore, the information at the output terminal Qi of the flip-flop Bi is transmitted through the transistors 8 and 10 to the output point Q of the bistable circuit.
i, and the information at the output terminal Qi of the flip-flop Bi is transmitted to the output point Qi of the bistable circuit via the transistor 7.9.
will be set respectively.

When the signal line Ps is returned to H level at time t8, the multiplexed storage cell Si becomes independent from the sequential circuit and other multiplexed storage cells.

After time t8, the sequential circuit can start the sequential circuit operation again.

When the erase pulse 51 is supplied to the signal line MGj at time t9, the threshold values of both the MNOS transistor pair Mj1 and Mj2 move in the positive direction to -2V.

When the MNOS memory transistor has the characteristics shown in FIG. 4, the erase pulse 51 is 25 V and 1 m s.
ec voltage pulses can be used.

After that, at time tl+, a write pulse 5 is applied to the signal line MGj.
2, the circuit information of the multiple memory cell, that is, the information of the output points Qi and Qi, is written to the MNOS transistor pair Mj, .

Although the operation of the circuit example shown in FIG. 3 has been described above using the timing chart of FIG. 5, this is only an example of the operation, and it goes without saying that various different operations can be performed.

For example, the erase pulse 51 can be supplied to the signal line MGj at time t5, or after performing a sequential circuit operation using the information read from the MNOS transistor pair Mj++Mj2 at time t1, the information of the sequential circuit can be supplied to the other MNOS).
Ransistor vs. Mk2. In order to store data in Mk2, the erase pulse 51 is applied to the signal line MGk at time t, and the write pulse 52 is applied to the signal line MGk at time t11.
may be supplied to

FIG. 6 shows another embodiment of the invention.

In this figure, parts that can have the same configuration as those in FIG. 2 are designated by the same reference numerals, and the explanation thereof will be omitted.

The control circuit 200 includes a signal MG that controls the exchange of non-volatile physical information and volatile circuit information in the multiple memory cells S, ~Sm, and the sequential circuit 100.
A signal S for setting initial information in the multiple storage cells 81 to S
A signal Ps for setting the information of bits B1 to Bm of the sequential circuit 100 in parallel to m, and a signal pb for setting the information of multiple memory cells in the sequential circuit 100 in parallel.
occurs.

The coincidence detection circuit 300 receives each bit output O of the sequential circuit 100.
Matching of information between Bi and 5i (i=1, . . . , m) is detected between 3 to Om and each output point Q1 to Qm of the multiplexed storage cell.

When each bit information matches, the match detection circuit 300 supplies a match output C to the control circuit 200.

The coincidence output C causes the control circuit 200 to output the signal MG.
.

Generate any one of S, Ps, and Pb.

For example, if the control circuit 200 generates the signal S based on the coincidence output C, the sequential circuit 1000 bits B1 to Bm
are all cleared to 0.

With such a configuration, it can be used as a program counter that uses the information contents of multiple memory cells as program information.

Assuming that the sequential circuit is an up-counter and m = 4, the multiple storage cells S to S4 have decimal information in which Sl is 2° digits, S2 is 21 digits, S3 is 22 digits, and S4 is 23 digits. It is variable within the range of 0 to 15.

The contents of multiple memory cells 81 to S4 are expressed in decimal notation r, (0
<r, <15), it means that an r-unary counter has been constructed.

Furthermore, when a coincidence output is detected, the physical information of the multiple memory cell is transferred to circuit information in the multiple memory cell (signal MG), and then the circuit information of this multiple memory cell is set in parallel to the sequential circuit (signal MG). It is also possible to configure the control circuit 200 as shown in pb).

This configuration allows sequential circuit operation in which the initial value and final value are determined by physical information in multiple storage cells.

For example, a multiple storage cell (1>2) stores at least two pieces of physical information in the same cell.

One of these may be preset in the sequential circuit 100 as initial data, and the other may be used as comparison information for detecting coincidence.

FIG. 7 shows yet another embodiment of the invention.

With this circuit configuration, it is possible to obtain a sequential circuit that does not lose its contents even when the power is cut off.

FIG. 8 is an operation timing chart of this embodiment.

In FIG. 7, 400 indicates signals MG and Ps. A control circuit 500 that generates pb is a circuit that detects power fluctuations.

In FIG. 8, when the power supply VDD starts to increase at time t'o, the power supply fluctuation detection circuit 500
A control signal is supplied to 00.

As a result, the control circuit 400 generates a voltage having approximately the same slope and the same amplitude as the power supply VDD, that is, a signal MG.

Referring to FIG. 3, this signal MG is
When supplied to the gates of the NOS) transistor pair Mj, 5 Mj2, the physical information possessed by the MNOS) transistor pair Mj1゜Mj2 is returned to the bistable circuit in the multiple storage cell as circuit information.

Time t. At this point, the signal K becomes L level, and the transistor 3
When ゜4 is in a conductive state, a bistable circuit in a multiple storage cell °
As mentioned above, is initialized by physical information, and the operation becomes stable.

Thereafter, at time t'2, the circuit information of the multiple storage cells is set in parallel in the sequential circuit 100 by the signal pb.

Thereafter, from time 174 to time 115, the sequential circuit 100 performs a sequential circuit operation using the parallel set information as an initial value.

At time 115, the fluctuation in the power supply VDD is detected by the power supply detection circuit 50.
When detected as 0, control circuit 400 generates signal Ps to set the contents of sequential circuit 100 in parallel in multiple memory cells 81-Sm.

Thereafter, the control circuit 400 sends an erase signal (+25V,
1 msec), and then further write signal (-
25V, 1 msec).

As a result, the contents of the sequential circuit 100 are stored in a nonvolatile manner, and when the power is turned on again, the sequential circuit 100 can be restored in the same manner as described above.

As described above in detail, according to the present invention, it is possible to completely eliminate the interference effect between bits during the transition of returning nonvolatile information to a sequential circuit.

For example, in the case of the embodiment shown in FIG. 7, if the power supply voltage conventionally required to read nonvolatile information is small, that is, operation at a voltage lower than the minimum operating power supply voltage of the constituent circuits is not a problem. It turned out to be a good thing.

This is because, according to the present invention, non-volatile information can be returned to the sequential circuit at a time when the sequential circuit operates sufficiently stably.

Furthermore, parallel setting of nonvolatile information restored as circuit information of multiple storage cells to sequential circuits is possible at any time, and since it is possible purely from a circuit perspective, it can be performed at high speed.

Furthermore, the embodiment shown in FIG. 6 has great versatility and can perform various functions that are difficult to perform with conventional non-volatile counters.

For example, a sequential circuit that can be preset, a counter that can be programmed to operate in any base, a sequential circuit that operates between a programmable initial value and a final value, a sequential circuit that contains various programmable preset data, etc. is possible.

Moreover, especially as the number of bits of non-volatile information in multiple memory cells increases, the functionality of sequential circuits increases in proportion to this. Only two MNOS memory transistors are added, and the chip area increases only slightly.

The present invention is not limited to the above embodiments, but can be widely applied without departing from the spirit of the present invention.

In the above embodiment, a pair of MNOS transistors were used as the nonvolatile elements in the multiple memory cell, but in general, MIO
It is also possible to use a variable threshold field effect transistor with an 8 structure or an MIS structure, a variable threshold field effect transistor with a floating gate structure, or the like.

Furthermore, it does not necessarily have to be a pair of variable threshold transistors (, - elements may also be used).

In this case, one of the pair of variable threshold transistors may be a fixed threshold transistor, as long as the threshold of the fixed threshold transistor is located between the high level threshold and the low level threshold of the variable threshold transistor.

The first transfer means and control means or the second transfer means and control means do not necessarily have to be provided independently.

The sequential circuit in the present invention may be any sequential circuit that can be set in parallel.

As mentioned above, it includes up counters, down counters, up/down counters, shift registers, ring counters, frequency dividing circuits, and sequential circuits including various other arithmetic functions.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of one bit of a conventional non-volatile counter, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing an example of the circuit configuration of an embodiment of the present invention. Figure 4 is MNO
FIG. 5 is a timing waveform diagram of one embodiment of the present invention, FIG. 6 and FIG. 7 are diagrams showing other embodiments of the present invention, and FIG. 8 is a timing waveform diagram of an embodiment of the present invention.
FIG. 3 is a timing waveform diagram of the embodiment shown in the figure. 100... Sequential circuit, 200.400...
... Control circuit, 300 ... Coincidence detection circuit, 500 ... Power supply detection circuit.

Claims (1)

[Claims] 1 A sequential circuit, a bistable circuit provided corresponding to each bit of this sequential circuit, a nonvolatile memory section built into this bistable circuit, and a potential of a bistable node of the bistable circuit. a first transfer means for transferring circuit information to each bit of the corresponding sequential circuit; a first control means for prohibiting information transfer by the first transfer means; and information on each bit of the sequential circuit. a second transfer means for transferring the information to the corresponding bistable circuit; a second control means for prohibiting the transfer of information by the second transfer means; a third transfer means for writing circuit information into physical information of the nonvolatile storage element; and a third transfer means for writing physical information of the nonvolatile storage element into circuit information represented by the potential of a bistable node of the bistable circuit. and a fourth transfer means for writing, and when the physical information is transferred as circuit information by the fourth transfer means, the first and second control means control the first and second transfer means. A sequential circuit having a nonvolatile memory function, characterized in that information transfer by a second transfer means is prohibited.