JPS5822468A - Processor bus connection system - Google Patents

Processor bus connection system

Info

Publication number
JPS5822468A
JPS5822468A JP56119208A JP11920881A JPS5822468A JP S5822468 A JPS5822468 A JP S5822468A JP 56119208 A JP56119208 A JP 56119208A JP 11920881 A JP11920881 A JP 11920881A JP S5822468 A JPS5822468 A JP S5822468A
Authority
JP
Japan
Prior art keywords
input
output control
processor
control device
standby state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56119208A
Other languages
Japanese (ja)
Other versions
JPS5852263B2 (en
Inventor
Shozo Hachitsuka
横山達男
Hidefumi Takahashi
高橋英史
Tatsuo Yokoyama
高山明
Akira Takayama
松井誠治
Seiji Matsui
八塚昭三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP56119208A priority Critical patent/JPS5852263B2/en
Publication of JPS5822468A publication Critical patent/JPS5822468A/en
Publication of JPS5852263B2 publication Critical patent/JPS5852263B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To permit a processor in a standby state to control an input and output controller, by inputting operation/standby state information on a system and an input and output controller connection/disconnection request signal from the processor to a processor bus switching device. CONSTITUTION:For example, while a processor CC0 is in a standby state, the CC0 sends an input and output controller (IOC) connection request signal to a processor bus switching device SW through a processor bus PRB0. Then, a detecting circuit DET0 discriminates whether an FF1 is turned on or not through a lead D. As a result, when the FF1 is turned off, an FF is set. A selector circuit SEL connects the PRB0 to the IOC only when the FF0 is on and the FF1 is off. When the FF1 is turned on, a processor CC1 in operation sends an IOC disconnection request signal to a detecting circuit DET through a processor bus PRB1 to reset the FF1. When the FF1 is turned off, the CC0 and IOC are connected mutually through PRB0.

Description

【発明の詳細な説明】 本発明は待機予備方式の系構成をもつ二重化した処理装
置に１系共通の入出力制御装置を系対応のプロセッサパ
スに接続するためのプロセッサパス接続方式に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processor path connection method for connecting an input/output control device common to one system to a processor path corresponding to a system in a duplex processing device having a standby/standby system configuration. .

従来、待機予備方式の系構成すなわち、θ系と１系の二
重化した処理装置にシステムの使用目的上、系共通の入
出力制御装置を接続する場合、例えば第１図に示すよう
に、゛二重化構成をとる処理装置ＣＣＤ　、ＣＣＪから
のびる系対応のプロセッサパスＰＲＢ　Ｏ、ＰＲＢ　Ｊ
にプロセッサパス切替装置ＳＷが接続され、さらに該プ
ロセッサ・々ス切替装置ＳＷを介して入出力制御装置Ｉ
ＯＣ、および該入出力制御装置１０Ｃの配下として入出
力装置ＩＯを接続する構成をとっていた。Conventionally, when connecting a common input/output control device to the dual processing units of the θ system and 1 system in a system configuration of the standby/backup system, for example, as shown in Fig. Processor path PRB O, PRB J extending from the processing device CCD, CCJ
A processor path switching device SW is connected to the processor path switching device SW, and an input/output control device I is connected via the processor path switching device SW.
The configuration was such that an input/output device IO was connected under the OC and the input/output control device 10C.

ここで、プロセッサパス切替装置ＳＷは、処理装置ＣＣ
Ｏ、ＣＣ７からの動作状態情報ＡＣＴ　Ｏ。Here, the processor path switching device SW is the processor path switching device SW.
O, operation status information from CC7 ACT O.

ＡＣＴ　１により動作状態の処理装置ＣＣＯ，ＣＣＩ対
応のプロセッサパスＰＲＢ　Ｏ、ＰＲＢ　１に入出力制
御装置ｒｏｃを接続する。いま処理装置ＣＣＯが動作状
態であれば、動作状態情報ＡＣＴ　Ｏはオフで、動作状
感情＠ＡｃＴＪはオフと々る３、従って、プロセッサバ
ス切替装置ＳＷは、動作状態にある処理装置ＣＣｏ対応
のプロセッサパスＰＲＢ　Ｏに入出力制御装置ｒｏｃを
選択接続するので、該入出力制御装置ｒｏｃ及び該入出
力制御装置ＩＯＣ配下の入出力装置■０は動作状態にあ
る処理装置ＣＣＯによってのみ制御を受けることになる
。By ACT 1, the input/output control device roc is connected to the processor paths PRBO and PRB 1 corresponding to the processing devices CCO and CCI in the operating state. If the processing device CCO is currently in the operating state, the operating state information ACT O is off, and the operating state emotion @AcTJ is off. Therefore, the processor bus switching device SW selects the corresponding processing device CCo that is in the operating state. Since the input/output control device roc is selectively connected to the processor path PRB O, the input/output control device roc and the input/output device 0 under the input/output control device IOC must be controlled only by the processing device CCO in the operating state. become.

しかしながら、以上述べた接続方式では例えばｌ−記入
出力制御装置ｒｏｃ又は入出力装置■０が障害となり障
害の回復確認試験等を行う場合、動作状態にある処理装
置ＣＣＯ対応のプロセッサ・ぐスＰＲＢ　Ｏにしか入出
力制御装置ｒｏｃは接続できないため、待機状態にある
処理装置ＣＣＩ対応のｊロセ、サバスＰＴｈＢ　７と入
出力制御装置ＩＯＣを接続して処理装置ＣＣ７から障害
の回復確認試験を行うことは不可能であった。However, with the connection method described above, when the input/output control device roc or the input/output device ■0 fails and a failure recovery confirmation test is performed, the processor/gus PRBO corresponding to the processing unit CCO in the operating state Since the input/output control device roc can only be connected to the processing device CC7, it is not possible to connect the input/output control device IOC to the processing device CCI-compatible JROSE, SAVAS PThB 7, which is in standby mode, and perform a failure recovery confirmation test from the processing device CC7. It was impossible.

本発明はこれらの問題点を解決するため、処理装置から
プロセッサパス切替装置に対して、系の動作／待機状態
情報及びプロセッサパスを介して入出力制（財）装置接
続要求信号又は人出力制御装置切断要求信号を人力させ
ることにより待機状態にある処理装置から入出力制御装
置を制御可能にしだもので、以下、詳細に説明する、。In order to solve these problems, the present invention provides system operation/standby state information and input/output control device connection request signals or human output control signals from the processing device to the processor path switching device via the processor path. The input/output control device can be controlled from a processing device in a standby state by manually issuing a device disconnection request signal, and will be described in detail below.

第２図は本発明の一実施例を示すプロ、り図であって、
ＣＣＯは待機予備方式の系構成をもつ二重化された処理
装置の一力の処理装置であり、ＣＣＩはもう一方の処理
装置である４、Ａは処理装置ＣＣＯの動作／待機状態情
報ＡＣＴθの情報信号線、Ｂは処理装置ＣＣＩの動作／
待機状態情報ＡＣＴ　７の情報信号線、ＰＲＢθは処理
装置ＣＣＯと接続されるプロセッサパス、ＰＲＢｌは処
理装置ＣＣ７と接続さｉするプロセッサパス、ＳＷはプ
ロセッサバス切替装置である。このプロセッサパス切替
装置ＳＷは、処理装置ＣＣＯからの人出力制御装置の接
続及び切断要求信号を検出する検出回路ＤＥＴ　Ｏ、処
理装置ＣＣ７からの入出力制御装置の接続及び切断要求
信号を検出する検出回路ＤＥＴ　７　、前記検出回路Ｄ
ＥＴ　Ｏの出力によって士。FIG. 2 is a professional diagram showing an embodiment of the present invention,
The CCO is one of the processing units in a duplex processing unit that has a system configuration of standby and backup system, and the CCI is the other processing unit 4. A is the information signal of the operation/standby state information ACTθ of the processing unit CCO. line, B is the operation of the processing unit CCI/
The information signal line of the standby state information ACT 7, PRBθ, is a processor path connected to the processing device CCO, PRB1 is a processor path connected to the processing device CC7, and SW is a processor bus switching device. This processor path switching device SW includes a detection circuit DET O that detects connection and disconnection request signals of the human output control device from the processing device CCO, and a detection circuit DET O that detects connection and disconnection request signals of the input/output control device from the processing device CC7. circuit DET 7, the detection circuit D
according to the output of ETO.

ト又はリセットされ、プロセ、す・々スＰＲＢ　Ｏと後
述する入出力制御装置を接続するだめのフリップ７０ッ
ゾＦＦ０１前記検出回路ＤＥＴ　１の出力によってセッ
ト又はリセットされ、ゾロセッサ・マスＰＲ１３７と後
述する入出力制御装置を接続するだめのフリッデフロッ
ｆＦＦＩ、前記フリ、ｆフロ。Flip 70 is set or reset by the output of the detection circuit DET 1, and is set or reset by the output of the detection circuit DET 1, and is connected to the input/output control device described below with the processor PRBO. The flip-flop fFFI, which connects the input/output control device, is the above-mentioned flip-flop.

：ｆ　Ｆ　Ｆ　Ｏの出力と情報信号線Ａとの論理積によ
りフリ、デフロ、ゾＦＦＪをリセットする論理積回路Ａ
ＮＤＯ，前記フリッゾフロ、　ｆＦ　Ｆ　Ｊの出力と情
報信号線Ｂとの論理積によりフリ、ゾフロツゾＦＦＯを
リセットする論理積回路ＡＮＤ　１　、および前記フリ
、プフロッｆＦＦｏ及ｏ：フリ、ｆフロツゾＦＦ７の出
力によりプロセッサパスＰＲＢ　Ｏ又はｌロセ、ザパス
ＰＲＢ　１を後述する人出力制御装置へ選択接続するセ
レクタ回路ＳＥＬより構成されている　又、ＩＯＣは入
出力制御装置であり、■０は入出力装置である。:f FFO AND information signal line A and logic product circuit A that resets FFJ, defro, and FFJ.
NDO, an AND circuit AND 1 that resets the FFO FFO by the AND of the output of the FRI, fF F J, and the information signal line B; It is composed of a selector circuit SEL that selectively connects the processor path PRB O or 1, and the path PRB 1 to a human output control device to be described later.IOC is an input/output control device, and 0 is an input/output device.

次に、以上の構成において、処理装置ＣＣＯが動作状態
にあるとき、該処理装置ＣＣＯと入出力制御装置１０Ｃ
をプロセッサパスＰＲＢ　Ｏを介して接続を行う場合に
ついて説明する。処理装置ＣＣ。Next, in the above configuration, when the processing device CCO is in the operating state, the processing device CCO and the input/output control device 10C
A case will be described in which connection is made via the processor path PRBO. Processing device CC.

は、プロセッサ・ぐス切替装置ＳＷに対して人出力制御
装置接続要求信号をゾロセ、す・マスＰＲＢメツを介し
て送出する１、ゾロセ、す・マス切替装置ＳＷ内の検出
回路ＤＥＴθは、前記処理装置ＣＣＯ力・らの情報信号
線Ａに現れた動作／待機状態情報力玉動作状態を示して
いる時に−１−証人出力制御装置接続要求信号をプロセ
ッサパスＰＲＢ　Ｏを経由１−で受信すると、リードＣ
を介してフリ、１７０．ノ”　Ｆ　Ｆ　。1 sends a human output control device connection request signal to the processor switching device SW via the output control device PRB. When the operating/standby state information appearing on the information signal line A of the processing unit CCO indicates the operating state, -1- witness output control device connection request signal is received via the processor path PRBO O. , lead C
Free via, 170.ノ”FF.

をヒツトする６、−力、情報信号線Ａ上の動作状態信号
と、ノリ、ゾフロ、ノＦＦＯの出力との論ｆｑｊ積回路
ＡＮＩ）　ｏの出力は、ノリッデフロノゾＦＦＩをリセ
ットする１次いで、セレクタ回＠　ＳＥＬは、ノリノｆ
ノ０７１Ｆ　Ｆ　Ｏか〕ンＣフリツノ０フ１１７ノＯＦ
Ｆノがオフという条（’ｌによりブｒコ（ニノ°す・ゞ
スＰＲＢ　Ｏを入出力制御装置ｒｏｃへ選択接続する・
この様に、処理装置ＣＣＯが動作状態であるときに・入
出力制御装置接続要求信号をプロセノヅー′６スＰＲＢ
　Ｏに送出すると、人出力制御装置１０Ｃはｐｉｊ＋、
４２件に前記処理装置ＣＣＯとゾ１コセ、ダ・マス［１
１３（１を介して接続される。The output of the AND circuit (ANI) o of the operating state signal on the information signal line A and the output of the FFO resets the FFI, then the selector circuit @ SEL is Norino f
ノ071F
When F is off, select and connect the BRCO to the input/output control device roc.
In this way, when the processing unit CCO is in the operating state, the input/output control unit connection request signal is sent to the processor PRB.
When sent to O, the human output control device 10C outputs pij+,
In 42 cases, the processing equipment CCO and Zo1kose, Da Mas [1
13 (connected via 1).

又、処理装置ＣＣＩが動作状態にあるとき、該処理装置
ＣＣＩと入出力制御装置ＩＯＣをプロセッサパスＰＲＢ
　Ｊを介して接続を行う場合も上記と同様の手順で行え
ることは明白である。Further, when the processing device CCI is in the operating state, the processing device CCI and the input/output control device IOC are connected to the processor path PRB.
It is clear that the same procedure as above can be used when connecting via J.

次に１処理装置ＣＣｏが待機状態にあるとき、該処理装
置ＣＣＯと入出力制御装置ＩＯＣをゾロセ、サパスＰＲ
Ｂ　Ｏを介して接続を行う場合について−説明する。先
ず、処理装置ＣＣＯはゾロセッサバス切替装置ＳＷＫ対
して入出力制御装置接続要求信号をゾロセッサパスＰＲ
Ｂ　Ｏを介して送出する。Next, when one processing device CCo is in the standby state, the processing device CCO and the input/output control device IOC are
The case where connection is made via BO will be explained. First, the processing device CCO sends an input/output control device connection request signal to the processor bus switching device SWK via the processor path PR.
Send via BO.

ｆロセ、サパス切替装置ＳＷ内の検出回路ＤＥＴ　Ｏは
、前記処理装置ＣＣＯからの情報信号線Ａに現われた動
作／待機状態情報が待機状態を示している時に上記処理
装置ＣＣＯからの入出力制御装置接続要求信号をゾロセ
ッサパスＰＲＢθを経由して受信すると、７す、ゾフロ
ッゾＦＦＩがオンになっているか否かをリードＤを介し
て識別する。その結果フリ、！フロッゾＦＦＩがオフの
場合にはり−ＰＣを介してフリ、プフロッ！ＦＦＯをセ
ットする。セレクタ回路ＳＥＬはフリッｆ７０．ｆＦＦ
（ｌがオンＣフリップフロ、ゾＦＦＩがオフという条件
によりプロセッサパスＰＲＢ　Ｏを入出力制御装置ＩＯ
Ｃへ選択接続する。The detection circuit DET O in the SAPASS switching device SW performs input/output control from the processing device CCO when the operation/standby state information appearing on the information signal line A from the processing device CCO indicates a standby state. When the device connection request signal is received via the Zorocessor path PRBθ, step 7 identifies via the lead D whether the Zorozzo FFI is on or not. As a result, pretend! If Flozzo FFI is off, Furi, Flozzo! can be accessed via the PC. Set FFO. The selector circuit SEL is flip f70. fFF
(Due to the conditions that l is on and FFI is off, the processor path PRBO is connected to the input/output control device IO.
Selectively connect to C.

又、上記識別の結果、）ＩＪ　、　ｆフロッゾＦＦＩが
オンの場合は、動作状態にある処理装置ＣＣＩが入出力
制御装置ｒｏｃを使用していることを意味し、検出回路
ＤＥＴ　Ｏはフリ、ゾフロッｆＦＦＯをセットしない。Also, as a result of the above identification, if )IJ, fFlozzoFFI is on, it means that the processing unit CCI in the operating state is using the input/output control device roc, and the detection circuit DETO is Do not set fFFO.

すなわち、待機状態にある処理装置ＣＣＯと入出力制御
装置ＩＯＣはプロセッサパスＰＲＢ　Ｏを介して接続さ
れない。この様な場合に、待機状態にある処理装置ＣＣ
Ｏと入出力制御装置ＩＯＣをゾロセッサパスＰＲＢ　Ｏ
を介して接続しようとするには、動作状態にある処理装
置ＣＣＩから入出力制御装置切断要求信号をプロセッサ
パスＰＲＢ　Ｊを介して検出回路ＤＥＴ　１に送出し、
フリ。That is, the processing device CCO and the input/output control device IOC in the standby state are not connected via the processor path PRBO. In such a case, the processing device CC in standby state
O and input/output control device IOC to Zorosesa path PRB O
In order to attempt to connect via the processor path PRBJ, an input/output controller disconnection request signal is sent from the operational processor CCI to the detection circuit DET1 via the processor path PRBJ;
pretend.

ゾフロッｆＦＦ１をリセ、トシて処理装置ＣＣＩと入出
力制御装置ＩＯＣを切り離すようにする。すなわち、検
出回路ＤＥＴ　７は前記入出力制御装置切断要求信号を
受信するとリードＥを介してフリ。Reset and toss the Zoflo fFF1 to separate the processing unit CCI and the input/output control unit IOC. That is, when the detection circuit DET7 receives the input/output control device disconnection request signal, it disconnects via the lead E.

ゾフロッグＦＦＩをリセットする。フリラグフロッグＦ
ＦＩがオフになると前述の手順によりフリ、ゾフロッゾ
ＦＦＯがセットされ、セレクタ回路ＳＥＬによシ処理装
置ＣＣＯと入出力制御装置ＩＯＣはプロセッサパスＰＲ
Ｂ　Ｏを介して接続される。Reset Zofrog FFI. Frilag Frog F
When the FI is turned off, the FFO is set according to the procedure described above, and the selector circuit SEL causes the processing unit CCO and the input/output control unit IOC to switch to the processor path PR.
Connected via BO.

又、処理装置ＣＣＩが待機状態にあるとき、該処理装置
ＣＣＩと入出力制御装置Ｉ’ＯＣをプロセ。Also, when the processing device CCI is in a standby state, the processing device CCI and the input/output control device I'OC are processed.

サパスＰＲＢ　１を介して接続を行う場合も上記と同様
の手順で行えることは明白である。It is clear that the same procedure as above can be used to establish a connection via SAPAS PRB 1.

以上説明したように１本発明によれば待機予備方式の系
構成をもつ二重化された処理装置の各々から、系の動作
／待機状態情報を受信する手段と、各基のプロセッサパ
スな介して入出力制御装置接続要求信号及び入出力制御
装置切断要求信号を受信する手段と、各基のゾロセッサ
パスと入出力制御装置とを選択接続する手段を有するこ
とにより、待機状態にある系の処理装置も入出力制御装
置とプロセッサ・ぐス接続可能となる。また、動作状態
にある系の処理装置と入出力制御装置がノロセッサパス
接続されている場合は、待機状態にある系の処理装置と
入出力制御装置との！ロセッサパス接続は行わず動作状
態にある系に影響を与えない等の利点がある。As explained above, according to the present invention, there is provided a means for receiving system operation/standby state information from each of the duplex processing devices having a standby-standby type system configuration, and a means for receiving system operation/standby state information from each of the duplex processing devices having a standby system configuration. By having a means for receiving an output control device connection request signal and an input/output control device disconnection request signal, and a means for selectively connecting the processor path of each group and the input/output control device, processing devices in a standby state can also be connected. Output control device and processor gas can be connected. In addition, if the system's processing device and input/output control device in the active state are connected by a no-rocessor path, the system's processing device and the input/output control device in the standby state! It has the advantage that it does not require processor path connection and does not affect the system in operation.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のプロセッサパス接続方式の一実施例を示
すブロック図であり、第２図は本発明の一実施例を示す
ブロック図である。 ＣＣＯ、ＣＣＩは処理装置、Ａ、Ｂは情報信号線、ＰＲ
Ｂ　Ｏ、ＰＲＢ　１はゾロセッサパス、ＳＷはプロセッ
サパス切替装置、ＤＥＴ　Ｏ、ＤＥＴ　７は検出回路、
ＦＦＯ，ＦＦＭはフリ、！フロップ、ＳＥＬはセレクタ
回路、ＩＯＣは入出力制御装置、ＩＯは入出力装置。 特許出願人　沖電気工業株式会社 日本電信電話公社 日本電気株式会社 株式会社日立裂作所 第１頁の続き ■出　願　人　株式会社日立製作所 東京都千代田区丸の内−丁目５ 番１号 ■出　願　人　富士通株式会社 川崎市中原区上小田中１０１５番地 −３５７−FIG. 1 is a block diagram showing an embodiment of a conventional processor path connection method, and FIG. 2 is a block diagram showing an embodiment of the present invention. CCO and CCI are processing units, A and B are information signal lines, PR
BO, PRB 1 is a processor path, SW is a processor path switching device, DET O, DET 7 is a detection circuit,
FFO, FFM is free! Flop, SEL is a selector circuit, IOC is an input/output control device, and IO is an input/output device. Patent Applicant Oki Electric Industry Co., Ltd. Nippon Telegraph and Telephone Public Corporation NEC Corporation Hitachi Risakusho Co., Ltd. Continued from page 1 ■Applicant Hitachi Ltd. 5-1 Marunouchi-chome, Chiyoda-ku, Tokyo ■Applicant Fujitsu Ltd. 1015-357 Kamiodanaka, Nakahara-ku, Kawasaki City

Claims (1)

【特許請求の範囲】 待機予備方式の系構成をもつ、例えばθ系、１系のよう
に二重化された処理装置に、該二重化された系に共通に
使用される装置であって、配下に入出力装置を接続して
いる入出力制御装置を夫々の系に対応のプロセッサパス
を介して接続するシステムにおいて、 夫々の系の動作、待機状態情報を受信する′手段と、夫
々の系よりプロセッサパスを介して入出力制御装置の接
続及び切断の要求信号を受信する手段、と、更には、入
出力制御装置とプロセッサパスとを選択接続する手段と
を配し、これらの手段により、上記二重化された処理装
置からの入出力制御装置の接続要求に対しては、その処
理装置が動作状態か、あるいは待機状態であるかに応じ
て入出力制御装置を要求のあった処理装置対応のプロセ
ッサパスに選択接続することを特徴としたゾロセッサパ
ス接続方式。[Scope of Claims] For duplex processing devices such as the θ system and 1 system, which have a system configuration of standby and backup system, a device that is commonly used in the duplex system and is subordinate to the In a system in which an input/output control device that connects an output device is connected to each system via a corresponding processor path, there is a means for receiving operation and standby state information of each system, and a means for receiving information on the operation and standby status of each system, and means for receiving request signals for connection and disconnection of the input/output control device via the processor path, and further means for selectively connecting the input/output control device and the processor path. In response to a connection request for an input/output control device from a processing device, the input/output control device is connected to the processor path corresponding to the requested processing device depending on whether the processing device is in an active state or a standby state. Zorosesa path connection method characterized by selective connection.
JP56119208A 1981-07-31 1981-07-31 Processor bus connection method Expired JPS5852263B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56119208A JPS5852263B2 (en) 1981-07-31 1981-07-31 Processor bus connection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56119208A JPS5852263B2 (en) 1981-07-31 1981-07-31 Processor bus connection method

Publications (2)

Publication Number Publication Date
JPS5822468A true JPS5822468A (en) 1983-02-09
JPS5852263B2 JPS5852263B2 (en) 1983-11-21

Family

ID=14755605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56119208A Expired JPS5852263B2 (en) 1981-07-31 1981-07-31 Processor bus connection method

Country Status (1)

Country Link
JP (1) JPS5852263B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103058A (en) * 1981-12-15 1983-06-18 Nec Corp Switching controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103058A (en) * 1981-12-15 1983-06-18 Nec Corp Switching controller
JPS6246896B2 (en) * 1981-12-15 1987-10-05 Nippon Electric Co

Also Published As

Publication number Publication date
JPS5852263B2 (en) 1983-11-21

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