JPS58223944A - Digital type phase locked circuit - Google Patents

Abstract

PURPOSE:To constitute a titled circuit of a gate IC and a counter IC easy to obtain, by comparing the phase between an input signal and an output frequency signal of a digital control transmitting signal and transmitting a detected output in response to the phase lead and phase lag. CONSTITUTION:When a signal at an input terminal 1 is not synchronized with an output of a digital control oscillating circuit 11, a signal at an OUT terminal of a lock detecting circuit 14 is ''1'' and a primary loop feeding back an output of the oscillating circuit to a phase detecting circuit is formed. When the initial phase locking is finished with this primary loop, the signal of the OUT terminal of the lock detecting circuit 14 goes to ''0'' and the signal is changed over to the secondary loop leading the integration output to the oscillating circuit. This secondary loop erases a stationary phase error generated in the primary loop.

Description

DETAILED DESCRIPTION OF THE INVENTION [Description of Technical Field] The present invention relates to a phase synchronized circuit constructed from a digital circuit.

[Description of prior art]

For command decoders mounted on artificial satellites, especially deep space probes, the distance between the earth and the probe is very large, so the signal-to-noise ratio of the input signal becomes extremely poor. Therefore, it is necessary to considerably narrow the bandwidth of the phase locked circuit used to demodulate the command signal. On the other hand, when the bandwidth is narrowed, the stability of the phase-locked circuit must also be improved, and conventional analog phase-locked circuits have poor stability and are difficult to satisfy the performance as a command decoder. For the above reasons, a highly stable digital phase synchronization circuit is used in the command decoder mounted on a deep space probe.

Here, FIG. 1 shows the configuration of a conventional digital phase synchronization circuit. In Fig. 1, l is a signal input terminal, 2 is a signal output terminal of the phase-locked circuit, 3 is a clock input terminal that is necessary for the operation of the phase-locked circuit and inputs the lock, 5 is a phase detection circuit with a gain of Kd, and 6 is a phase detection circuit with a gain of Kd. 7 is an adder circuit, 8 is a latch circuit, 9 is a coefficient circuit for coefficient B, IO is an adder circuit, 11 is an interest 1% K. Digital system f! 11 oscillation circuits are shown respectively. The output of the oscillation circuit 11 is obtained at the output terminal 2, and this signal is feedback-coupled to the input of the phase detection circuit 5, and its phase is compared with the signal at the input terminal 1. The comparison results are digitally integrated and other processed in each circuit, and are applied to the control input of the oscillation circuit 11 to control the oscillation frequency.

However, such digital phase-locked circuits have complex configurations and require many types and numbers of parts, making them unnecessary for products that are produced in small numbers, such as equipment mounted on artificial satellites and deep space probes. The drawback is that many different types of parts are produced in small quantities, which increases costs.

[Explanation of purpose]

The present invention improves this point, and aims to provide a digital phase synchronization circuit that can be constructed from commonly used parts and can be mounted on an artificial satellite or a deep space exploration vehicle.

[Summary of the invention]

The present invention includes a digitally controlled oscillator circuit and a phase detection circuit that compares the phase of an input signal and an output frequency signal of the digitally controlled oscillator circuit and sends out a detection output in response to a phase lead or a phase lag. Output of digitally controlled oscillator circuit 'f! :, J: Feed back to the phase detection circuit and detect the phase detection circuit. In a digital phase synchronized circuit configured to control the oscillation frequency of the digitally controlled oscillation circuit with its output, the phase lead and phase delay are and a rate multiplication circuit that controls the oscillation frequency of the digitally controlled oscillator circuit in response to the output of the integration circuit. do.

Further, it is preferable to include a lock detection circuit that detects whether or not the input signal and the output of the digitally controlled oscillation circuit match in phase, and resets the integration circuit when they do not match.

[Explanation of Examples]

An embodiment of the present invention will be described based on the drawings.

FIG. 2 is a block diagram of main parts of an embodiment of the present invention.

Comparing with the conventional example shown in FIG. It is characterized in that it is composed of a secondary loop led to a gold digitally controlled oscillation circuit 11 and a lock detection circuit 14.

Other points are similar to the conventional example shown in FIG. 1, and the same reference numerals indicate the same parts.

FIG. 3 is a detailed view of FIG. 2.

In Fig. 3, l is a signal input terminal, 21 is a signal output terminal of a phase synchronized circuit, 3 is a clock input terminal, 18 is a command receiver, 19 is a bandpass filter for passing the command signal, and 20 is a zero-cross control terminal. 21 and 22 are D-type edge trigger flip-flops, 23
is an exclusive OR circuit, 24 is an up/down counter, 25a to 251 are exclusive OR circuits, 1
3 is a rate multiplication circuit, 14-digit lock detection circuit, 28 and 29 are AND circuits, 30 is an inverter circuit, 31 is N
A stage counter 32 indicates that the output value of the N stage counter 31 is -
33 is a 0 detection circuit that detects that the output value of the N-stage counter 31 is 0; 34 and 35 are AND circuits; 36 is an OR circuit;
37 is an inverter circuit, and 38 is a frequency divider. Also, P8 of the command decoder f, [H2] input to the signal input terminal 1 is a modulated wave, and the signal tq
The input terminal 2 outputs a signal synchronized with the command signal input from the signal input terminal l. Clock input terminal 3
is supplied with a constant frequency clock from the outside. The frequency of the clock differs depending on the number of stages of the N-stage counter 31, but in this case, since it is an N-stage counter, the frequency of the clock input to the clock input terminal 3 is 2NX fs[: Hz
].

-tNarichi, bandpass filter 19. Comparator 2
0, flip-flops 21 and 22, and an exclusive OR circuit 23 constitute a phase detection circuit 5. The bandpass filter 19 has a band number for passing the command signal.

The comparator 201d is configured to compare the output of the bandpass filter 19 with the ground level, and output "1" if the output voltage of the bandpass filter 190 is higher than the ground level, and output "oJ" if it is lower. flip 70 tube 2
1 and 022Bcr, 4 (clock terminal) At the rise of the signal from the digital oscillation circuit 11 to which VC is applied, the output of the comparator 2o is held until the next rise of the signal ρ of the digital oscillation circuit 11. The signals from the digitally controlled oscillator circuit 11 seen at the OL and terminals of the flip-flops 21 and 22 have different phases from each other by 9o0.

Exclusive OR circuit 23 is flip 70 knob 21
and the exclusive OR of the outputs of 22. The output of the exclusive pair circuit 23 is configured to be the output signal of the phase detection circuit 5.

The up/down counter 24 and the exclusive OR circuits 25a to 251 constitute the accumulation circuit 12. The exclusive OR circuits 25a to 251 of the integration circuit 12 are connected correspondingly to the output terminals of the up/down counter 24 except for the MSB output, and the other input terminals are led to the MSB output of the uptown counter 24, respectively. . When “1” is input to the RJIET terminal of the up/down counter 24, the MRB is input from the LSB of the up/down counter 24.
"o" is output to all output terminals. Up/down counter 240Rg sF; T terminal is r OJ f U
Itiji when the P/DOWN terminal is "1" = The value of the uptown counter 24 becomes 1 when the signal from the digital control l11 oscillation circuit 11 applied to the OL terminal rises.
To increase. □UP' of up/down counter 24
? When the /DOWN terminal is "0", the value of the up/down counter 24 is decremented by 1 at the rise of the signal from the digitally controlled oscillation circuit 11 applied to the terminal.

MS B-1 from LSB of uptown counter 24
Each output at the switch is exclusive ORed with the MSB output by the exclusive OR circuits 25a to 251, and the outputs of the exclusive OR circuits 25a to 25j indicate the absolute value of the value of the up/down counter 24. The output MSB of town counter 24 is configured to indicate the sign of the value of up/down counter 24.

The rate multiplier circuit 13 is configured so that when pulses are input to the OLL terminal, the number of pulses proportional to the value input to the terminals from MSB to LSB of the rate multiplier circuit 13 is outputted from the OUT terminal.

The lock detection circuit 14 outputs a 77 signal from the OUT terminal when the phase synchronization circuit operates and the outputs of the comparator 20 and the frequency divider 38 match in phase.

The digitally controlled oscillator circuit 11 includes an N-stage counter 31 that counts the clock from the clock input terminal 3, and an AND circuit 28 and 2 that determine the initial value of the N-stage counter 31.
9. Inverter circuit 30; 34, 35) and outputs an initial value setting signal to the N-stage counter 31. MOB output of the 11-stage counter 31 and 9.
It is composed of an inverter circuit m and a frequency divider 38 that generate signals with different 0' phases. The output of this frequency divider is output from the signal output terminal 2 as an output signal of the phase synchronization circuit.

The digitally controlled oscillator circuit 11 receives the output signal of the phase detection circuit 5 and the MS of the up/down counter 24 of the WtS circuit 12.
The oscillation frequency is changed by a signal from the OUT terminal of the B output and the rate multiplier circuit 13. That is, when the OUT terminal of the lock detection circuit 14 is "1", the output MSB terminal of the up/down counter 24 and the OUT terminal of the rate multiplication circuit 13 are always "o", and the AND circuit 28
"o" is always output to the outputs of and 29, and "1" is always output to the output of the inverter circuit 30.

At this time, if the SET terminal of the N-stage counter 31 becomes "1", the value of the N-stage counter 31 is set to r-2N-IJ,
The count is increased by the clock from the clock input terminal 3. When the 8-stage counter 31 counts up and its value reaches "-2", the output of the -2 detection circuit 32 becomes "1". If the output signal of the phase detection circuit 5 is "1" at this time, the 8FjT terminal of the 8-stage counter 31 becomes "1" again through the AND circuit 34 and the OR circuit 36, and the value of the 8-stage counter 31 becomes r-1. - set to IJ. Since the number of clocks from the clock input terminal 3 counted by the 8-stage counter 31 between "-2J and "-21-11 is 2-1, it is the cycle of the signal output from the signal output terminal 2. .

Again, the eight-stage counter 31 counts up based on the clock from the clock input terminal 3. At this time, the output signal of the phase detection circuit 5 is set to "0" 2. Then, when the value of the 8-stage counter 31 becomes "0", the 0 detection circuit 3
3, the SKT terminal of the 8-stage counter 31 becomes "1" through the AND circuit 35 and the OR circuit 36, and the value of the N-stage counter is set to r-2N-IJ. The number of clocks from the clock input terminal 3 counted by the 8-stage counter 31 between "0" and r-2N-IJ is 2+1, so the frequency of the signal output from the signal output terminal 2 is be. In this way, when the OUT terminal of the lock detection circuit 14 is "1", the frequency characteristic of the signal output from the signal output terminal 2 due to the output signal of the phase detection circuit 5 is N2N-1×f8 [H2] and ≠×fsCH2 ] Either 2+1.

On the other hand, when the OUT terminal of the lock detection circuit 14 is "o", roJ or "1" is output to the MSB terminal of the output of the up/down counter 24 and the OUT terminal of the rate multiplication circuit 13. When the MSB terminal of the output of the up/down counter 24 is "0" and the OUT terminal of the rate multiplier circuit 13 is "0", the outputs of the AND circuits 28 and 29 are "0", and the output of the inverter circuit 30 is "1". . Therefore, when the SET terminal of the 8-stage counter 31 becomes "1", the value of the 8-stage counter 31 is set to "=2N-IJ. Therefore,
When the output signal of the phase detection circuit 5 is "0" and "1", a signal of -Xfo[Hz':1 N-1 is outputted from the signal output terminal 2.

The MSB terminal of the output of the up/down counter 24 is “0”.
'', when the OUT terminal of the rate multiplier circuit 13 is "1", the output of the AND circuit 29 and the inverter circuit 30 is "0", and the output of the AND circuit 28 is [1-1], so the 8-stage counter 3
When the ET terminal on the 1st becomes "1", the value of the 8-stage counter 31 is set to r-z'J. Therefore, the phase detection direction I
I! When the output signal of 85 is roJ, the signal when fS[H2] is "1" is output from the signal output terminal t2.

The MSB terminal of the output of the uptown counter 24 is “1”
When the OUT terminal of the rate multiplier circuit 13 is "1", the output of the AND circuit 28 and the inverter circuit 30 is [OJ], and the output of the AND circuit is "1", so the SET terminal of the 8-stage counter 31 is "1". ”, the value of the 8-stage counter 31 is r
-2N-2J.

Therefore, when the output signal of the phase detection circuit 5 is "o" When “1” f8 [Hz] A signal is output from the signal output terminal 2.

The lock detection circuit 14 detects whether the output of the digitally controlled oscillation circuit 11 and the input signal match, and when the phases do not match, resets the up/down counter 24 to prevent the up/down counter 24 from overflowing. It is configured.

With this circuit configuration, when the command receiver 18 is not receiving radio waves, a command signal is input to the signal input terminal l, and nothing appears at the output of the bandpass filter 19. Therefore, the output of comparator 2゜(
'' or ``1'', and the digitally controlled oscillation circuit 11 also outputs all the signals with the frequency of ,,', , x f8 (uz). At this time, from the QUT terminal of the lock detection circuit 14 The output lock signal is "1" indicating that the phase synchronization circuit is not synchronized.

Next, when the command receiver 18 receives the radio wave, the command signal is input to the input terminal 15, so the command signal is input to the input terminal 15.
The output of the filter 19 also shows the command signal strength. Therefore, the output of the controller 20 also changes between "0" and "1" depending on the voltage of the command signal.

On the other hand, signals with a 90° phase difference from the digitally controlled oscillator circuit 11 are sent to the output terminals of the two flip-flops 21 and 22.
added to the L terminal. These two] IJ Tsubufu
Outputs d! of locks 21 and 22! If both are "1", the output of the exclusive OR circuit 23 becomes "0" and is added to the digital control oscillation circuit 41 as the output of the phase detection circuit 5.

At this time, the frequency of the signal output from the digitally controlled oscillator circuit 11 is -f-x fF3[H2] 2+'1+1, and the phase with respect to the command signal input to the signal input terminal 1 changes in the direction of delay. .

By repeating this operation, the output of the flip-flop 22 becomes "
When the signal changes to "0", the output of the exclusive OR circuit 23 becomes "1" and is applied to the digitally controlled oscillation circuit 11 as the output of the phase detection circuit 5.

As a result, the frequency of the signal output from the digitally controlled oscillation circuit 11 changes to ≠xf8()1z'), and the phase with respect to the command signal input to the signal input terminal 1 advances.

However, next time the output of the flip-flop 22 will be "0" again.
'', and the signal output from the digitally controlled oscillation circuit 11 becomes 'X fe [H2] 2N+1. While the phase synchronization circuit repeats such operations, the phases of the command signal input to the signal input terminal 1 and the signal output to the signal output terminal 2 match.

As a result, the OUT terminal of the lock detection circuit 14 becomes "0".
The up/down counter 24 becomes operable.

Here, the frequency of the command signal input to signal input terminal 1 is f. When the value is slightly lower than [H2] by 7, "0" appears more than "1" in the output signal of the phase detection circuit 11 because the phase synchronization circuit maintains a synchronized state. The value of the up/down counter 24 changes at a rate corresponding to the probability of appearance of "0" and "1" in the output signal of the phase detection circuit 11, and the output of the up/down counter 24 at the M/B terminal is "1" or "K". Therefore, a number of pulses proportional to the absolute value of the up/down counter 24 are outputted from the OUT terminal of the rate multiplication circuit 13.

As a result, the digitally controlled oscillation circuit 11 is controlled in a direction where the phase is further delayed. This control is balanced when "1" and "01" appear at the same rate in the output signal of the phase detection circuit 5.

Further, if the frequency of the command signal input to the signal input terminal IK is slightly higher than fsCH2], the reverse control to the above is performed in the same way.

As described above, this phase synchronized circuit operates as an open-order loop in which the OUT terminal of the lock detection circuit 14 is "1". −
When the initial phase synchronization is completed by the next loop, the OUT terminal of the lock detection circuit 14 becomes "0" and the loop is switched to the second loop. The main purpose of the secondary loop is to eliminate the steady phase error that occurs in the -order loop when the frequency of the command signal input to signal input terminal 1 is slightly different from f8 [Hz]. .

[Explanation of effects]

As explained above, according to the present invention, it is possible to configure a phase-locked circuit using a commonly used game IC and a counter IC, parts are easily available, and product costs can be reduced. In addition, the phase-locked circuit of the present invention hardly uses digital signals handled in parallel and controls the circuit based on the probability of pulse generation corresponding to phase lead or lag, which reduces the number of connections between circuit elements. , the overall configuration can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts of a conventional example. FIG. 2 is a block diagram of main parts of an embodiment of the present invention. FIG. 5 is a detailed view of FIG. 2. l...Signal input terminal, 2...Signal output terminal, 3...
・Clock input terminal, 5... Phase detection circuit, 11...
・Digital control oscillation circuit, 12... Integration circuit, 13
...Rate multiplication circuit, 14...Lock detection circuit, 24
...Uptown counter, 31...N stage counter, 32...-2 detection circuit, 33...0 detection circuit. Patent applicant: NEC Corporation Representative Patent attorney: Naotaka Ide

Claims (2)

[Claims] (1) Completely equipped with a digitally controlled oscillation circuit and a phase detection circuit that compares the phases of the input signal and the output frequency signal of the digitally controlled K1 oscillator circuit and sends out detection outputs in response to phase leads and lags; In the digital-total type phase synchronized circuit configured to feedback-couple the output of the digitally controlled oscillation circuit to the phase detection circuit and control the oscillation frequency of the digitally controlled oscillation circuit with the detected output of the phase detection circuit, the phase It is fully equipped with an integrating circuit that integrates the probability of occurrence of a detection output that occurs in response to lead and phase lag, and a rate multiplier circuit that controls the oscillation frequency of the digitally controlled oscillator circuit in accordance with the output of this integrating circuit. A digital phase synchronized circuit characterized by: (2) A digital phase synchronized circuit according to claim 0, which includes a lock detection circuit that detects whether or not the human input signal and the output of the digitally controlled oscillation circuit match the phases and resets the integrating circuit when there is a mismatch. Two