JPS58220287A - Memory access controller - Google Patents

Abstract

PURPOSE:To improve the memory access performance, by providing a hash circuit which supplies prescribed plural bits of a request address and deciding a bank address through the hash circuit to give a request to a memory having divided banks. CONSTITUTION:The 10th, 11th, 17th-20th bits are referred to as A, B, C, D, E and F respectively among 24 bits of an address of a memory access request given from a central processor 1. Then an exclusive OR circuit 41 produces bank address 2 bits 19 and 20 of a memory device 3 in the form of AVCVE and BVDVF. These bits are defined as an address 40 within a bank and sent to the memory 3 containing independent banks B0-B3 which are connected to the contents of bits 0-18 of the address 40. As a result, the concentration of memory addresses to a specific bank is avoided. This decreases the waiting time for an idle bank.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to memory access control in an information processing device, and particularly relates to address manipulation of main memory.

(2) 4 Description of Prior Art Recent central processing units of this type have 51. A high-speed cache memory is provided that partially stores and retains data in the main memory, and data transfer between the main memory and the cache memory is performed in units of blocks containing core data when the target data does not exist in the cache. It is carried out as

Blocks are generally selected to be 32 bytes, 64 bytes, or more, but since it is physically difficult to transfer them all at once, they are divided into approximately 8 bytes and transferred sequentially the necessary number of times, starting with the desired data. .

FIG. 3 shows a pull slip of 32 bytes, the number of memory banks=4, and the number of read bytes divided by 8 bytes, which is the relationship between block data and memory banks, which has been generally performed in the past. In the figure, 100 represents a block and 200 represents a main memory.

Due to the nature of the program, the address of the target data (=data that does not exist in the cache memory) is often the first address of the block, that is, the address of the target data (data that does not exist in the cache memory) is often the first address of the block, that is, the address of the target data is often read from bank 0 of the memory. As central processing units become more multiplexed and faster, the first data read is concentrated in bank 0, resulting in an increase in waiting time due to contention and a decrease in p1 performance.

(3) Detailed Description of the Invention The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional technology.Therefore, an object of the present invention is to solve the problem of the above-mentioned disadvantages of the conventional technology. , the badge circuit allows the memory addresses to be distributed uniformly across other banks without being concentrated in bank 0, reducing the waiting time for bank 9 due to contention, and making it possible to quickly return the first requested data to the request source. The purpose of the present invention is to provide a new device with improved performance.

(4) Detailed Description of the Invention In order to achieve the above object, the present invention provides an information processing device that is divided into banks and has a menu that can be accessed independently between the banks. By inputting a predetermined nine or more bits into the hash circuit to determine the bank address, it is possible to temporarily avoid concentration of accesses to a specific bank at the same time and even out the accesses. , which aims to shorten waiting times at banks.

(5) Detailed Description of the Invention Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram showing one embodiment showing the positional relationship of the present invention within a system. In the figure, one embodiment of the present invention includes a central processing unit 1, a memory access control device 2, a hash circuit 5 which is a main part of the present invention, a memory device 3, and four banks that can be accessed independently in the memory device. 4 (
BOlBl, B2, B3).

Figure 2 shows an example in which the maximum memory capacity is 16'pi) (-224 bytes) and the block transfer request from the central processing unit 1 is divided into 4 times of 8 bytes each (32 bytes/block) and transferred. , which shows the hash circuit 5 of FIG. 1 in more detail.

Address 2 of memory access request from central processing unit 1
The 4 bits i are shown in FIG. 2 40. Address 10.1
1.17.18.19 and additional bits A1B and C respectively
, D1B and F, E and F indicate 8-byte boundary addresses within the Boo3-lock.

The two bits of the bank address of the memory device 3 are created as J) AVC'lE and B'SD'%F by the exclusive OR circuit 41, and are combined with the contents of bits θ to 18 of the address 40 as an address in the bank. A request is issued to the memory power supply 3 in the format shown by 42.

In the conventional device, addresses 20Ω (20Ω) E and F were often bank addresses, so data request addresses from each central processing unit were concentrated in the memory of bank BO, resulting in performance degradation due to contention.

Table 1 shows the relationship between the access request address and the bank address in the present invention (an example showing the effects of the present invention). Here, A-=F corresponds to A-F at address 40 in FIG. According to this, it is clear that the values of E and F and the value of the bank address are random.

4- The +1 circuit 43 in FIG. 2 can sequentially read the 9th 8-byte digit from the previous address for rounding of pull transfer, and the pits 19 and 19 of address 40 are replaced. Also, the f111 portion (bits 21 to 23) of address 40 (bits 21 to 23 = 61 is an address indicating a data position within 8 bytes) is unnecessary for main memory access.

(Detailed Description of the Invention) As explained above, the present invention uses a hash circuit to determine the bank address, thereby avoiding the temporary concentration of accesses on a specific puncture, and the memory access. It has the effect of improving performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the general position of the present invention in the system, and FIG. 2 is a detailed diagram showing one embodiment of the present invention.
FIG. 8 is a schematic diagram showing the relationship between intra-block addresses and puncture addresses in a conventional device. 1...Central processing unit, 2...Memory access control device, 3...Main memory device, 4...
...Punk, 5...Hatush circuit, 41.
...Exclusive OR circuit, 48...+1 addition circuit modulo 3, BO to B3...Punk, 1
00...Block, 200...Main memory patent applicant NEC Corporation Representative Patent attorney "Yutabe Kumagai 7- Kugi

Claims (1)

[Claims] In an information processing device having a memory divided into banks and independently accessible between banks, a hash circuit is provided, and a plurality of predetermined bits of an address of a memory access request are input to the hash circuit to obtain a bank address of the memory. A memory access control device that determines the percentage of mold.