JPS58219842A - Transmitting device of information - Google Patents

Abstract

PURPOSE:To store data information stored in the 1st storage means of a transmitting device in the 2nd storing means of a receiving device without loading a processor. CONSTITUTION:When the processor 21 specifies an address and writes the address, data information from the processor 21 is stored in a memory 7. The memory outputs the data information of which address is specified to a data bus 22 through a reading-out signal from the 1st control circuit 6 through a line 16 and an address signal through an address bus 15. A shift register 8 loads the address and data information in parallel by a load signal supplied from a line 17 and outputs them in series in the direction of the arrow 23. A shift register 26 loads the address and data information through a line 4 successively in the direction of an arrow 30. The address information and data information loaded by the shift register 26 are outputted in parallel to an address bus 31, and data bus 32 while being shifted always in respondence with a pulse signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information transmission device, and more particularly, the present invention relates to an information transmission device, and more specifically, a transmission device having a first storage means in which data information is read and written by a processing device; a receiving device having a second storage means for reading and writing, and interposed between the transmitting device and the receiving device,
The present invention relates to an information transmission device having a single data line for storing data information stored in a first storage means in a second storage handcuff.

In the prior art, in order to store the data information stored in the first storage means of the transmitting device in the second storage means of the receiving device, a processing device in the transmitting device reads the data information from the first storage means. , passes the read data information to the first temporary storage means, and the processing device activates the first temporary storage means to derive the data information to the data line. Further, in the receiving device, the data information from the data line is stored in the second temporary storage means and the processing device is notified that the data information has been sent, and the processing device, after receiving the data information from the second temporary storage means, The data information is stored in the second storage means. Therefore, the burden on the processing device was heavy. In other prior art, a direct memory access controller (DMAC) is used instead of the processing unit;
had to be activated each time data information is transferred, which places a heavy burden on the processing device when data information is transferred at high speed.

An object of the present invention is to solve the above-mentioned technical problem and to store data information stored in the first storage means of the transmitting device in the second storage means of the receiving device without imposing a burden on the processing device. The objective is to provide an information transmission device that can

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block circuit diagram of one embodiment of the present invention.

The information transmission device 1 includes a transmitting device 2 and a receiving device @3. The transmitting device 2 and the receiving device 3 are connected by a single data line 4 for transmitting data information from the transmitting device 2 to the receiving device 3.

The transmitting device 2 is a pulse generating port FI! I5, a first control circuit 6, a memory 7 as a first storage means, and a shift register 8 as a first temporary storage means.

The pulse generating circuit 5 outputs a pulse signal having a predetermined first constant period TI to a line 9, as shown in FIG. 2(1).

The first control circuit 6 includes counters 10 and 11 and an inverting circuit 1.
2, and NAND gates 13 and 14. A pulse signal from the pulse generating circuit 5 is applied to the counter 10VC via a line 9. The counter 10 counts the falling edge of the pulse signal in binary numbers from "0" to "7" at a predetermined second fixed period T2 as shown in FIG. 2 (2). Numerical values are output in parallel from output terminals Qa+Qbw Qc in 3 bits and with a weight of Qc>Qb>Qa. The output from the output terminal Qc of the counter 10 is input to the inverting circuit 12. The output from the inversion circuit 1+l1%12 is input to the counter 11.

The counter 11 counts the rising and falling edges of the signal given from the inverting circuit 12 in binary numbers from "0" to [15J, and outputs the counted value from the output terminal Qa+Qbw Qc+Qd in 4 bits.Qc>Qb>Qa It is output to the address bus 15 in parallel with the weight of . The signal output from the counter 12 to the address bus 15 is incremented by ``+IJ'' from ``o'' to ``15'' at a period T2 as shown in Figure 2 (3) K. This is the Natres signal.

The outputs from the output terminals Qb and Qc of the counter IO are NA
ND game) 131C are respectively input. The signal outputted from the NAND gate 13 on line 16rC is shown in FIG.
4), during the period W1 [, NAND game] 13 when the count values of the counter 10 are "6" and "7", the output of the NAND gate 13 is a low level tonal. This low level signal number, period T2
A line 161C is derived for each signal and used as a read signal.

The outputs from the output terminals Qa, Qb, and Qc of the counter 10 are inputted to the NAND game 14, respectively.

The signal output from NAND gate 14 on line 17 [is shown in FIG.
[7J] Period W2 [NAND game] 14 (7) Output cut becomes tff-level. This low level signal is
A line 171C is derived every period T2 and used as a load signal.

The memory 7 is a so-called dual port memory, and has two separate parallel input/output ports 18 and 19. The boat 18 connects to the processing device 2 via the system bus 20.
Connected to 1. Data information from the processing device 21 is stored in the memo IJ7 by addressing and writing by the processing device 21. Further, when the processing bag flt21 specifies an address and issues a read command, the data information stored in the memory 7 is transferred to the processing bag [21VC].

Boat 19 is connected to address bus 15 and line 16. The memory 7 outputs addressed data information to the data bus 22 as shown at +61 VC in FIG. . The memory 7 can individually transfer data information to and from the processing device 21 independently of the first control circuit 6 via the baud) 18 and 19, and can also transfer data information to and from the processing device 21 independently of the first control circuit 6. Data information can be transferred to the data bus 22 in individual correspondence with the control circuit 6.

Lines 4, 9.17, address bus 15 and data bus 22 are connected to shift register 8. The shift register 8 loads the address information of the address signal via the address bus 15 and the data information via the data bus 22 in parallel at the rise of the pulse signal when the load signal applied from the line 17 is at a low level. The shift register 8 also transfers the address information and data information loaded at the rising edge of the pulse signal in the direction shown by the arrow 23 to the data line 4 in this order as shown in FIG. 2 (7).
Outputs 1C in series. Line 9 is also connected to receiving device 3 .

The receiving device 3 includes a shift register 26 as a second temporary storage means, a second control circuit 27, and a memo 28 as a second storage means. Data line 4 is connected to the input of shift register 26. Line 9 is
It is connected to the input of the control circuit 27, and also connected to the input of the inverting circuit 2.
9 to the input of the shift register 26.

The shift register 26 serially loads the address information and data information via the data line 4 in the direction shown by the arrow 30 while sequentially shifting them in this order at every rise of the pulse signal via the inversion circuit 29. The inverting circuit 29 is
Since the shift register 8 of the transmitter 2 shifts the address information and data information with a delay of half a period Tl/2 of the pulse signal, it is provided to delay the pulse signal by a half period. The address information and data information loaded into the shift register 26 are output in parallel to the address bus 31 and data bus 32 while being constantly shifted in response to pulse signals.

The second control circuit 27 includes a counter 33 and a NAND gate 34. A line 9 is connected to the input of the counter 33. The counter 33 converts the falling edge of the pulse signal into a predetermined second value in binary notation as shown in FIG. 2 (8).
It counts from 0 to 7 at a constant period T2, and outputs the counted value in parallel from the output terminals QaeQb and Qc in 3 bits with a weight of Qc>Qb>Qa. The output from the output terminals Qa+Qb+Qc of the counter 33 is NA
The signals are respectively input to the ND gate 34. The signal output from the NAND gate 34 to the line 35 is shown in FIG. 2 (9).
, and the period W of the count value “7” of the counter 33
At 2, the output of the NAND gate 14 becomes low level. This low level signal is led out to line 35 every period T2 and is used as a write signal.

The memory 28 is a so-called dual port memory,
It has two separate sets of parallel input/output ports 36 and 37. The boat 36 has an address bus 31 and a data bus 32.
and stone connected to line 35. The memory 28 stores valid data information addressed by the write signal from the second control circuit 27 and the address information from the shift register 26 via the address bus 31 in the diagonal lines in FIG. Remember as shown.

The boat 37 connects to a processing device 39 via a system bus 38.
Connected to VC. Data information from the processing device 39 is stored in the memory 28 when the processing device 39 specifies an address and issues a write command. Further, when the processing device 39 specifies an address and issues a read command, the data information stored in the memory 28 is transferred to the processing device 39JC.
be transferred.

The memory 28 can store data information from the data bus 32 in correspondence with the second control circuit 27 independently of the processing device 39 through the ports 36 and 37, and can store data information from the data bus 32 independently of the processing device 39. can independently transfer data information to and from the processing device 39.

FIG. 3 is a block diagram of another embodiment of the present invention, and parts corresponding to those of the embodiment shown in FIG. 1 are given the same reference numerals. What should be noted in this embodiment is the information transmission device 51
Only an optical fiber 54 as a single data line is provided between the transmitting device 52 and the receiving device 53, and the data information stored in the memory 71C is reversely opened twice in succession. That's true.

In the transmitting device 521C, the shift register 8 receives the address information from the first control circuit 8862 via the address bus 15, and the inversion signal via the address bus 15 and an inverting circuit 55 for inverting the address information bit by bit. address information, data information from the memory 7 via the data bus 22, and inverted data information via the data bus 22 and an inversion circuit 56 for inverting the data information bit by bit. The shift register 8GC is also provided with 4-bit audio information via a microphone 57, an analog/digital converter 58, and a data bus 59, and 4-bit switch information via a switch circuit 60 to be operated and a data bus 61. Therefore, the shift register 8 is given 24 bits of information.

The pulse signal from the pulse generation circuit 5 is transmitted to a first control circuit 6 configured in the same manner as the first control circuit 6 in the embodiment shown in the first figure.
It is applied to the synchronization circuit 63 via the control circuit 62. The control circuit 62 controls the pulse signal from t to [23j].
It is counted at the period T3 of a2, and the counted value [22J, [
A low level signal is output to line 16 only when the signal is 23J. Further, the first control circuit 62 outputs a low level signal on the line 17VC only when the count value is "2-3". moreover! 11 part wS62 is "+1" every second period T3
The incremented address signal is sent to the address bus 15V.
C output. Therefore, the shift register 8 loads each piece of information when the count value is "23j," and sequentially supplies the loaded information to the modulator 64 starting after half a cycle of the pulse signal.

The synchronization circuit 63 responds to the pulse signal and provides a synchronization signal to the modulator 64VC every second period T3 to clarify the counting start timing and the like.

A pulse signal from the pulse generating circuit 5 via the line 9 is also applied to the modulation a64. The modulator 64 modulates the pulse signal, the synchronization signal, and each information component by a method such as Manchester or pi-phase, and outputs the modulated signal via the electrical/optical converter 65 to the optical fiber 54rc.

In the receiving device 53, the optical fiber 5 is connected from the transmitting device 52.
The modulated signal outputted at 4 is given to the demodulator 72 via an optical/electrical converter 671. The demodulator 72 demodulates a pulse signal, a synchronization signal, and each piece of information from the modulated signal and outputs them individually.

The pulse signal and each piece of information from the demodulator 72 are given to the shift register 26. Each piece of information is PFI loaded into the shift register 26 in response to a pulse signal. Demodulator 7
The pulse signal and synchronization signal from the second control circuit 73
given to. ! The second control circuit 73 is configured in the same manner as the second control circuit 27 shown in the first diagram, and starts counting in response to a synchronization signal, and outputs a low-level write signal only when the count value is "23". to the determination circuit 74 via line 35.
Give 1C.

In the shift register 26, the address bus 31 is -
It is also connected to WJ75 several times. Address bus 76 for sending inverted address information from shift register 26
is passed through an inversion circuit 77 for further inverting the inverted address information bit by bit, and then connected to a -number circuit 75VC.
Connected. The output of the -number circuit 75 is provided to the decision circuit 74 via line 78.

The data bus 32 is also connected to the minus number circuit 791C. A data bus 80 for sending the inverted data information from the shift register 26 is connected to a matching circuit 79 via an inverting circuit 81 for further inverting the inverted data information bit by bit.

-FjI several times! The output of J79 is provided via line 82 to the decision circuit 740 input. The output of decision circuit 74 is connected via line 83 to the input for writing to memory 28 .

A data bus 84 for transmitting acoustic information from the shift register 26 is connected via a digital/analog converter 85 to an acoustic transducer 86 for generating sound. A data bus 87 for transmitting switch information from the shift register 26 is connected to a display 88 having a light emitting element.

Let us assume that each piece of information from the transmitting device 52 is loaded into a predetermined position in the shift register 26rc without error. That is, the address information is sent to the address bus 31 without any code error, the inverted address information is sent to the address bus 761C, the data information is sent to the data bus 32, the inverted data information is sent to the data bus 80, and the acoustic information is sent to the data bus 84. and switch information is output from the shift register 26 to the data bus 87.

In this case, the address information given to i75 -several times and the inverted and further inverted address information match. Only when this match occurs, the minus number circuit 75
Outputs an 8VC low level signal. Also - number circuit 79
The data information given to and the inverted and further inverted data information match. Only when this matches,
- number circuit 79 outputs a low level signal on line 82.

At this time, line 35 is also at low level. Judgment time 1i7
4 outputs a low level signal to line 83 only when each line 35, 78, 82 is at low level. Therefore, valid, error-free data information is stored in the memory 28 at error-free addresses.

Assume that each piece of information from the transmitting device 52 is loaded into the shift register 26VC by mistake or out of the predetermined position. In this case, the outputs of the -number circuit 75mah and the coincidence circuit 79 remain at high level. Or line 3
The timing when 5 becomes low level is different. Therefore, the output of the determination circuit 74 remains at high level. Accordingly, data information from the memory 7 of the transmitting device 1i52 is not stored in the memory 28.

Data information from the memory 7 of the transmitting device 52 is therefore stored in the memory 28 of the receiving device 53 with improved reliability. Also, the transmitter @52 may be the receiver 5.
3, which is convenient.

FIG. 4 is a block circuit diagram of another embodiment of the present invention,
Parts corresponding to those in the embodiment shown in the first figure are given the same reference numerals. What should be noted in this embodiment is that address information is not transferred from the transmitting device 102 of the information forwarding device 101 to the receiving device [103VC].

In the transmitting device 102, the first control circuit 104 counts the pulse signals from the pulse generating circuit 5 from "0" to "3", and outputs a low-level readout signal to the line 16 only when the total Wi value is "3". Output.

The period from count value "0" to "3" is a predetermined second cycle T4. Further, the first control circuit 104
A low level signal is output to the line 17 only when the count value is "3" every cycle T4. Furthermore, the control circuit 104
outputs an address signal in which the address is incremented by "+1" to the address bus 15 every cycle T4.

The shift register 8 loads the addressed data information from the memory 7 with the load signal.

The loaded data information is sequentially output from the shift register 8 to the data line 4 in response to a pulse signal via the line 9.

In the receiving device 103, the data information from the transmitting device 2 via the data line 4 is sequentially tff-loaded to the shift register 26VC in response to the pulse signal from the transmitting device 2 via the line 9 and the inverting circuit 29. line 9
A pulse signal from the transmitter 102 via the second control circuit 105Vc is applied.

The second control circuit 105 is configured in the same manner as the first control circuit 6 of the embodiment shown in the first figure, and has counters 106, 1
It has 07. The counter 106 responds in synchronization with the pulse signal via the line 9, counts from "0" to "3", and when the count is 1iik r3J, a low level write signal is sent to the line every second cycle T4. Output to 35.

Counter 107 responds to the pulse signal via counter 106 and line 9, and every period T4 i'(r+IJ
f×rOJ is incremented to “15” and outputs a separate sequentially repeated address signal to an address bus 108 connected to memory 28. Therefore, the data information in the memory 7 of the transmitting device 102 is stored in the receiving device 103.
28VC of memory is stored.

Note that in each of the embodiments shown in FIGS. 1, 3, and 4, the processing devices 21 and 39 may be the same processing device 1,
It may also be a central processor unit (CPU). Further, the processing device 21.39 and the information transmission device 1, 51, 101 can be used in an online computer system, a computer network, a remote control monitoring device, a centralized control system, a disaster prevention monitoring device, a communication device, etc. Furthermore, the memory 7.28 does not have to be a dual-port memory, and may be made to look like a dual-port memory by using a general random access memory in a time-sharing manner, or by temporarily stopping the processing device. The memory may also be accessed by In addition to double reverse reverse opening, parity pit, checksum, CR
Reliability may be further improved by using a combination of a C check, a parity word, a pit, or the like, or an alarm may be issued when verification fails. Also, by combining the transmitting device and the receiving device,
Data information may be transmitted bidirectionally. In this case, the processing unit and memory can be shared, and the data line can be an electric wire, optical fiber, or coaxial cable. Further, optical fibers allow wavelength multiplexing and round trip, and electric wires and coaxial cables allow frequency multiplexing.

Also, a plurality of receiving devices may be provided in parallel,
A selection address for selecting one of the plurality of addresses may be provided to transfer data information individually. Furthermore, by specifying the address specification order in advance according to the writing frequency of the data information in the memory 28,
The order of address specification may be changed.

In the embodiments described above, the pit configuration of data information between the processing device and the memory was explained using four pits, but other pit configurations may be used.

As described above, according to the present invention, data information stored in the first storage means of the transmitting device can be easily stored in the second storage means of the receiving device without imposing a burden on the processing device.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram of one embodiment of the present invention, Fig. 2 is a waveform diagram for explaining its operation, Fig. 3 is a block circuit diagram of another embodiment of the invention, and Fig. FIG. 3 is a plug circuit diagram of another embodiment of the invention. 1.51,101... Information transmission device, 2,52゜10
2... Transmitting device, :'(,53,103... Receiving device, 4... Data line, 5... Pulse generation circuit,
6,62.104...first control circuit, 7. , 28...
・Memory, 8.26...Shift register, 21.31
...processing device, 27,73. 1os...Second control circuit, 54...Optical fiber agent Patent attorney Kei Nishi Partial procedural amendment October 71, 1982 1. Display of case Patent application 1982-103595 2. Transmission of information on the name of the invention Apparatus 3, Relationship with the case of the person making the amendment Applicant's address Name: Bonn Electric Co., Ltd. Representative 4, Agent address: 1-13-38 Nishihonmachi, Nishi-ku, Osaka Shinkosan Pill 6, Invention of the invention in the statement of contents of the amendment In the Detailed Description column, the Brief Description of Drawings column, Drawing 7, and the 3rd line of page 6 of the specification subject to amendment i11, the phrase ``From evening 12'' is corrected to ``From evening 11''. (2) On page 8, line 19 of the specification, "control circuit" is corrected to "second control circuit." (3) "Control circuit" on page 12, line 17 of the specification
Correct the statement to "first control circuit." (4) In the 18th negative line 7 of the specification, "control circuit" is corrected to "first control circuit." (6) In page 22, line 6 of the specification, r21,31・
・・Processing device” 'r-r21,39...Processing device''
Correct. (6) Figures 10, 11 and 4 will be revised as shown in the attached sheet. that's all

Claims (1)

[Scope of Claims] A transmitting device having a first storage means into which data information is read and written by a processing device, a receiving device having a second storage means into which data information is read and written by the processing device or another processing device, and a transmission device. An information transmission device comprising a single data line interposed between the device and the receiving device for storing data information stored in the first storage device in the second storage device, wherein the transmitting device has a predetermined a pulse generating circuit for deriving a pulse signal of a first constant period; a first control circuit for deriving a read signal and a separate sequentially repeated address signal and for deriving a second periodic load signal; and responsive to said load signal, addressing from said first storage means. In addition to temporarily storing the data information in parallel,
The receiving device includes first temporary storage means for sequentially and serially deriving the temporarily stored data information to the data line in response to the pulse signal, and the receiving device extracts the data information from the data line in synchronization with the pulse signal. a second temporary storage means for sequentially and serially temporarily storing and deriving in parallel, in synchronization with the pulse signal;
Addressed data information from the second temporary storage means or addressable data information from the second temporary storage means to the second storage means by individually sequentially and repeatedly addressing each second fixed period. An information transmission device characterized in that it includes a second control circuit that derives a write signal for storage at every second constant period.