JPS5821983B2 - Channel selection display device for television receivers - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel selection display device using a dorato scanning method, and in particular to a channel selection display device that is equipped with a minimum number of character generators and can perform multipurpose displays other than numerical channel display. It is related to the device.

The channel selection display device displays the received television channels by driving a display disk on which 1 to 12 and UHF are displayed in conjunction with channel selection.

However, a channel display device with such a configuration,
Since only the periphery of the display disk is used, there is a limit to the number of display channels, which has the disadvantage that it cannot be used in TV multiplex broadcast receivers, CATVs, etc. that have a large number of channels.

Therefore, it is an object of the present invention to provide a channel selection display device for a television receiver that can easily display a large number of channel selections and also display other characters using other characters. That's true.

Hereinafter, a channel selection display device for a television receiver according to the present invention will be explained in detail using the drawings.

FIG. 1 shows a front view of a cable television receiver to which a channel selection display device according to the present invention is applied, and 1 shows a group of push button switches for channel selection consisting of a total of 30 push button switches. , 2 shows a dot pattern indicator for indicating the receiving channel.

As shown in an enlarged view in FIG. 2, for example, when channel 12 is selected, the dot pattern display 2 displays the selected channel using a dot pattern drawn by a combination of dots. is configured to do so.

In this example, water? 5 horizontal dots, 7 vertical dots
The first digit and any character are displayed by a combination of 35 bits of dots, and a vertical column of 7's is displayed to the left of these 35 bits.
Arrange the dots to display the second digit ``1'' for a total of 4.
Combinations of 2-bit dots are used to display numbers "1 to 19" and arbitrary characters.

Such a dot pattern display 2 is constituted by a dot matrix in which light emitting elements such as LEDs are assembled, and is driven by a circuit as shown in FIG.

3 is a well-known device (not shown); for example, key A taken out from a flyback transformer in a television receiver circuit.
a terminal into which a pulse with a horizontal deflection period for GC is injected;
4 is a clock signal generation circuit that shapes the waveform of this pulse without changing its cycle and sends out a first clock signal; 5 is a first counter driven by this first clock signal; here, a quinary counter is used; It is being

6 is a first decoder that converts the output of the first counter 5 into scanning pulses for 5 horizontal dots of a dot matrix that ultimately constitutes the dot pattern display 2;
Also, G1 to G are gate circuits that sequentially scan the five horizontal dots of this dot matrix to emit light.
Character generator (hereinafter referred to as CG) 7 to be described later
The pixel signal sent from is injected.

Reference numerals 8□ to 83o denote channel selection terminals, which correspond to the channel selection pushbutton switch 1 described above, and a constant voltage is applied to any selected terminal.

9□～9. is an external terminal for displaying things other than channel selection, such as visitor display, incoming call display, washing machine completion display, toilet empty display, etc. In this case, external terminal 9 is connected to a visitor detection sensor. is connected, an incoming call detection sensor of the telephone is connected to the external terminal 92,
Furthermore, external terminal 9. The following explanation assumes that a washing completion detection sensor is connected to the washing end detection sensor.

10 is all external terminals 9□~9. 11□~113o are each channel selection terminal 8□~88
AND gates 12 provide AND gates 11 to 11 which respectively provide a match between the output signal of o and the output of the NOR gate 10;
The output of 3o and the output of external terminals 9□ to 92 are respectively input in parallel, and a predetermined code corresponding to the input signal supply position,
For example, based on the code table shown in Figure 4, 1 to 12
Display data consisting of 8 bits corresponding to each input of a total of 30 channels and external terminals 91 to 9. This 8-bit display data is converted into T-Z1% display data corresponding to A.
.

The 6-bit output of -, -A6 is used as address data for CO2, the 1-bit output of Bo is used as 2-digit display data that means the second digit "1", and the remaining 1-bit output of B1 is used as the first digit. It is configured as 1" display data which means "1".

Also, 13 is CG? and a line that branches one of the outputs of the first decoder 6 as a second clock signal for driving the second counter 4.

Here, a decimal counter is used as the second counter 14.

Reference numeral 15 denotes a second decoder which converts the count output of the second counter 14 driven by the second clock signal into a row switching timing pulse of the dot matrix, and its No. 0 output is housed in the CO2 as described later. Due to the time delay characteristic of the clock vs. output of the line selector counter (not shown), the "empty" output is assumed and the "9" output is injected as a mask reset pulse which has priority over the CO2 clock pulse.

Therefore, outputs No. 1 to No. 7 of the second decoder 15 are used as row switching timing pulses of the dot matrix.

Further, the terminal 16 is a power supply terminal for supplying power to the light emitting elements forming the dot matrix.

Here, for the CO2 mentioned above, a 5x7 dot matrix scattering generator is used here, and the numerical alphabet is the 5th one.
As shown in the figure, horizontal lines T1 to T9, vertical line 01
~A for O5.

-A, and sends out 5-bit picture element signals of vertical lines 01-05.

Further, the horizontal lines T0 to T are switched by the second clock signal, and in order to do this, a 9-ary line selector (not shown) is particularly built in the CO2.

This line selector counter is therefore driven by the second clock signal to switch each horizontal line T1-T.

On the other hand, as mentioned above, the line switch left counter is injected with a mask reset pulse of the second data [rQJ] output, and when this master reset pulse is injected, the line switch (not shown) are all 0FF (no designation) and are given priority over the second clock signal.

That is, this line select counter is kicked at the falling edge (Low) of the mask reset pulse, giving priority to the first horizontal line T1 of the 9-ary counter over the second clock signal, and at the rising edge (High) of the mask reset pulse.
The count is increased to 1 horizontal line T2, and the second
Sequentially driven by a clock signal.

As a result, the pixel signals selected from CO2 can match the switching timing of the horizontal lines T2 to T8 with the row switching timing of the dot matrix.

CO2 configured in this manner can be realized by a single well-known integrated circuit without using many integrated circuits.

In this way, in this device, CO2 sends out pixel signals of one-digit numbers and alphabetic characters, but as already mentioned, the dot pattern display 2 in this embodiment has signals of 910 to 12".
The two-digit channel number shall be displayed.

Therefore, B is sent from the encoder 12 as two-digit display data that commands the display of this second digit.

The 1-bit output of is injected into the gate circuit G1.

The gate circuit G□ is connected to the Bo output of this encoder 12,
It consists of a NOR circuit that injects a second link signal which is ultimately converted into a row switching timing pulse of the dot matrix.

The output of the gate circuit G□ is 5×7 dots of 35
Seven dots arranged in a left horizontal and vertical row of a dot matrix made up of bits are injected to emit light.

Here, the second clock signal injected into this gate circuit G□ is not limited to this, and the same operation can be obtained even if it is an arbitrary scanning pulse extracted from any one of the outputs of the first decoder 6. It will be done.

In this way, a two-digit number can be realized with a simple configuration without particularly providing another CG.

Furthermore, by appropriately changing the configuration of the encoder 12, it is possible to display two-digit numbers from 710 to 19''.

In this way, the second digit number "1" simply becomes a pattern of one vertical bar, so for example, as in the case of the number "11", the pixel signal sent from the first digit number, that is, CG7 It is desirable to match the second digit in the pattern.

For this reason, in the device of this embodiment, the gate circuit G4 corresponding to the center of the horizontal dot of the 35-dot matrix that displays the first digit is constructed from a NAND circuit, and further a circuit is constructed by combining three NOR gate circuits 07 to G9. is connected.

This circuit is different from other gate circuits G, , G3 ., except when the first digit is "1". G5. G.
Perform exactly the same action as .

In addition, in the case of displaying '1', the encoder 12 outputs B as '1' display data that instructs to emit only the 7-dot pattern in one vertical row in the center of the 35-dot matrix.
A 1-bit output of 1 is injected into the gate circuit G7.

At this time, the picture element signal sent from CG7 is controlled by the encoder 12 in advance by determining the address data of CG7 so as to address the non-character display, so that the pixel signal sent from gate circuit G3 and G2. .

G3. It is not injected into G5 and G6.

As a result, when the numbers "1" and "11" are displayed, CG7
does not send out a pixel signal, and matches the pattern of the second digit and the first digit on the display of the dot pattern display 2.

The operation of the above configuration will be explained in detail below.

FIG. 6 is a waveform diagram showing the operation timing of this device.
Pl indicates a first clock signal, which is generated by waveform-shaping a keyed AGC pulse or the like having a horizontal deflection period injected from the terminal 3 by the clock signal generating circuit 4.

This first clock signal CP1 passes through a second quinary counter 5 and is converted into the output of a first decoder 6 as shown in FIG. 6A.

One of the outputs of the first decoder 6 is branched off as the second clock signal CP2 by the line 13, as described above, and is injected into the gate circuits G0 and CG7 and the second decimal counter 11.

Therefore, each of the output pulses 1 to 5 shown in FIG. It is used as a scanning pulse to scan 5 horizontal dots.

As a result, CG7 addressed by encoder 12
Based on the pixel signal sent from the bottom, the valley gate circuit causes the dot matrix connected to its output to emit light.

On the other hand, the second clock signal CP2 continues as shown in FIG.

Then, the output of the second counter 14 is sent out sequentially by the second encoder 15 as output pulses 0 to 9 having timings as shown in FIG. 6.

The output pulses 0 to 9 of this second encoder 15 are
7'' is used as the row switching timing pulse of the dot matrix.

Therefore, when the dot matrix scans 5 horizontal dots by the pulse shown in FIG. 6A, the rows of 7 vertical dots are sequentially switched from the upper row by the pulse shown in FIG.

On the other hand, the output pulse number "9" of the second encoder 15 is
It is injected as a mask reset pulse for CG7.

Therefore, as already mentioned, this CG7 drives the built-in line select counter by the second clock signal CP2 shown in FIG. 6A, and sequentially switches the horizontal lines T1 to T as shown in FIG. 6C. Second encoder 15
When a mask reset pulse is injected at the timing of output pulse "9", the line select counter is switched to the horizontal line T1 at the falling edge of the mask reset pulse.

As long as this master reset pulse is injected, the line select counter will not be driven even if the second clock signal CP2 is injected.

As a result, since the timing at which the mask reset pulse is no longer injected matches the timing of the 10th second clock signal CP2, the time delay of the rise of the master reset pulse and the 10th second clock signal CP2 coincide with each other.
2, the line select counter is not driven by the 10th second clock signal CP2, and the horizontal line T0 is maintained as shown in FIG. 6C.

Further, the horizontal lines T0 and T of CG7 are used as an interval as shown in FIG. 5, and no picture element signal is sent out.

Therefore, the 10" scraping force of the second decoder 15 is "empty".
It is used as output.

Similarly, the "8" output of the second decoder 15 is also set as the "empty" output.

Then, by using the "9" scraping force as a mask reset pulse, as shown in FIG. Synchronized with horizontal scanning.

In this way, the reception channel corresponding to the output of the push button switch 1 for channel selection is displayed.

In this case, the types of display reception channels can be increased according to the capacity of the CG 7, regardless of the display space.

The above explanation is for external terminals 9□-9. There is no signal in any of them, and accordingly, the output of the gate 10 is always “1”.
", and one of the AND gates 11 to 113o
This is an explanation of the operation when a reception channel is displayed by supplying a "1" signal to the input.

Next, in this state, for example, a visitor display sensor (not shown) detects a visitor, and this detection signal "1" is sent to the external terminal 9.
When supplied to □, the output of the NOR gate 10 becomes "0".

As a result, each of the AND gates 11 to 113o, which has the output of the NOR gate 10 DEG as one gate input, blocks all outputs of the push button switch 1 and stops displaying the receiving channel.

On the other hand, the visitor detection signal supplied to the external terminal 9□ is supplied to the input terminal of the encoder 12 corresponding to the external terminal 9□, and is decoded into a code signal of "110010".

This decoded signal A is “110010”.

-A addresses CG7 to generate a display output of the English letter "S" as shown in FIG.
``S'', which means a visitor, is displayed.

In addition, when an incoming telephone signal is supplied to the external terminal 9□, rTJ indicates an incoming telephone call as shown in FIG.
will be displayed.

In this way, by displaying the signal supplied to the external terminal in a pattern using the portion of the CG that is not used for channel display, the channel selection display can also be used as a multi-purpose display.

As explained above, in the channel selection display device for a television receiver according to the present invention, the character generator is addressed by the output of the channel selection switch, and the output of the character generator drives the display having a dot matrix configuration to receive the signal. In addition to displaying the channel, it also serves as a display for other purposes by addressing and displaying a portion of the character generator other than the channel display using a signal for other purposes other than the reception channel display, and its utility value is extremely high. It is.

[Brief explanation of the drawing]

FIG. 1 is a front view of a television receiver using the present invention, FIG. 2 is a front view of a dot pattern display device according to an embodiment of the present invention, and FIG. 3 is an embodiment of a channel selection display device according to the present invention. Figure 4 is a code table for the encoder that converts the selected channel and external signals for other purposes into display patterns, Figure 5 is an address diagram of a character generator showing an example, and Figure 6 is shown in Figure 3. FIG. 4 is a waveform chart showing the operation of each part of the circuit. 1...Push button switch, 2...Dot pattern display, 4...Clock signal generation circuit,
5...First counter, 6...First decoder, 7...Character generator, 8-8
...Tuning terminal, 9□~1 80 9, ...External terminal, 10...Noah gate, 11□~11 ......And gate, 12.
...Encoder, 0 14...Second counter, 15...Second
decoder.

Claims (1)

[Claims] 1. A channel selection switch provided for each channel, a character generator addressed by the output of the channel selection switch, a display having a dot matrix configuration for displaying the output of the character generator, and a display for displaying the output of the channel selection switch. A channel selection display device for a television receiver, comprising an external input terminal for displaying other purposes, which addresses the character generator with priority over output.