CA1080349A - On-screen channel display - Google Patents
On-screen channel displayInfo
- Publication number
- CA1080349A CA1080349A CA193,843A CA193843A CA1080349A CA 1080349 A CA1080349 A CA 1080349A CA 193843 A CA193843 A CA 193843A CA 1080349 A CA1080349 A CA 1080349A
- Authority
- CA
- Canada
- Prior art keywords
- character
- signal
- circuit
- accordance
- horizontal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Television Systems (AREA)
- Studio Circuits (AREA)
Abstract
Abstract An on-screen television display including means internally of the receiver for generating characters to indicate the channel number, time of day or other data. The system includes circuit means respon-sive to the horizontal and vertical sync signals of a television receiver for positioning and timing of the display. BCD data is coupled to a character generator, and the output of the character generator is then multiplexed with positioning and timing signals. The multiplexed output is coupled to a video interface which supplies the video signal to the cathode ray tube.
Description
108~3~9 The field of art to which this invention pertains is on-screen display of characters in a television receiver with character generation locally in the receiver.
The use of on-screen display of a channel number, for instance, has been proposed in an article entitled "Broadcast and Television Receivers", IEEE, Vol. BTR-15, No. 2, July 1969, however, the character generators which are available commercial-ly are generally "read only memories" designed to display either 16 or 64 alpha-numeric characters. These character generators require 350 memory bits for 10 characters. In such a device, all 35 possible positions in a 5 x 7 font are used for the numerals.
The character generator is the most expensive element of such a system.
The present invention provides an improved system for the display of characters on the screen of a television receiver using character generating means locally in the receiver.
According to one aspect of the present invention there is provided a system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plur-ality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decod-ing means into a given line segment generated video signal and comprising means for multiplexing the outputs of said decoding means in accordance with the line of scan of the beam of the cathode ray tube of said broadcast television receiver, and means for adding the generated video signal in a video circuit of said broadcast television receiver to develop a character display on . I .
~08034g the raster of the television receiver in addition to any other signal being processed by said video circuit.
According to another aspect of the invention there is provided a system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plur-ality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decoder ;;
into a given line segment generated video signal and comprising an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver and means responsive to the horizontal synchronization signal of received broadcast television signals for keying said oscillator, I and means for adding the generated video signal in a video cir-i cuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.
The features and advantages of the present invention will be understood in greater detail from the following descrip-tion and the associated drawings wherein reference numerals are utilized to designate a preferred embodiment.
Figure 1 is a general block diagram of an on-screen display system according to the present invention.
Figure 2 is an illustration of the line segments used to form the characters in the seven segment decoder according to the present invention.
Figure 3 is a block diagram of the character generator illustrated in Figure 1. ~ -i :, .. .
~ '' ~ ; ~' ' ' ', - ' - - : , ^` 108~349 Figure 4 is a more detailed block diagram of the circuit illustrated in Figure 1.
Figure 5 is an illustration of the screen of a tele-vision receiver showing the positioning of character windows on the screen.
Figure 6 is a schematic of the digital circuit used in the block diagram of Figure 4.
Figure 7 is a detailed illustration of one of the win-dows shown in Figure 5. ;
Figure 8 is a schematic similar in many respects to Figure 6 but including additional circuitry to produce character displays for the proper time of day.
Referring to Figure 1, there is shown a display system according to the present invention. In this figure, a position- -ing and timing circuit 10 is used to position the display on the raster and to provide timing signals to a character generator 11 and to a multiplexer 12.
The output of the multiplexer 12 is coupled to a TV
interface system which is not shown in detail herein, but is the least expensive circuit in the system. Interface would be obvious to a skilled person and can be achieved by simply super-imposing the display over the program video and keeping the display in white or black. Other interface systems could offer variations on the theme by providing the display to be in a given color. The channel number information is provided in the form of a code that iB recognizable by the character generator. In this case, the channel number information is provided in Binary Coded Decimal form. In the present system, BCD code is provided on eight parallel lines, one group of four lines for each channel number digit.
l The data input block 14 in Figure 1 performs the I function of multiplexing the two groups of four lines into one ,''~
~ ,. :
'.t.` ~, ., ., .. , ....... . ' .. ' . ' .. ..... ' ., ,.. :. ', ' .' :,'' .: ' i:' ... .', ' ,. ,', ' ', ,. . :. : . ' ~08~349 group of four lines. In other words, the data input circuit 14 is switching the inputs of the character generator between the two channel number digits.
The character generator is the most expensive part of the system shown in Figure 1. Prior art character generators available for this function are designed to display either 16 or 64 alpha-numeric characters in a 5 X 7 font. The requirement for a channel display is that it be capable of dis-playing the numerals 0 through 9, thus making the 16 character numeric generator a logical choice. However J such a device is too costly for this type of a sys~em. In such character generators, 350 ~5 X 7 X 10) memory bits are required for 10 characters. This device uses all 35 possible positions in a 5 X 7 font of the type shown in Figure 2.
The present invention utilizes the seven segment numeral. In Figure 2, it can be seen that all numerals are constructed from a combination of four vertical straight line segments and three straight horizontal line segments.
The four vertical segments occupy only two of the five vertical columns. Each vertical segment occupies four positions in a column of seven horizontal positions. The center position in columns 1 and 5 are shared by the upper and lower vertical segments.
Each horizontal segment in the font shown in Figure 2 occupies a complete row of five positions. The extreme positions of each horizontal segment are shared with the extreme positions of each vertical segment. Only 23 positions, out of a possible 35 are actually utilized. If the numeral is being scanned horizontally as in a conventional television receiver, it can be seen that if any horizontal segment is selected there is no change in that I row for the entire period that the numeral is being scanned. Accordingly, the 15 positions in the three horizontal rows can be reduced to three positions. The total number of positions required can be reduced to t4 X 4) ~ 3 = 16 ~ 3 = 19 positions. Also, columns 2, 3 and 4 can be ' 30 eliminated from the memory because there will never be any change in those three columns as any row is being scanned.
With the above view of the font shown in Figure 2, memory can be : ' , , 4 :` T~L
`' ~L : : -~, ... , , .. - . - - - .' . ,, .. , . . . - . ~ -1~8~349 eliminated if a seven segment decoder is used to select the segments which are required to construct a given numeral. The selec*ion is accomplished in accordance with a code in BCD form provided at the input to the decoder.
Referring to Figure 3, which further illustrates the character generator 11, a seven segment decoder 15 has seven output lines 17 through 23, one for each of the segments 24 through 30 shown in Figure 2. The three out-put lines 21, 22, and 23 are for the top, center and lower horizontal segments 25, 27 and 29 respectively. The four vertical segment output lines 17, 18, 19 and 20 must first be coupled through gating and isolating circuitry 38.
Such circuitry provides switching action to switch on and off the horizontally scanning electron beam in order to reproduce the vertical segments 24, 26, 28 and 30.
Referring to the block diagram of Figure 4, the timing and positioning function performed by circuit 10 of Figure 1 is initiated by the use of two delay circuits, namely, a horizontal delay circuit 39 and a ' vertical delay circuit 40. The horizontal delay circuit 39 produces a delay during each scan of the cathode ray beam between points 41 and 42 as shown in Figure 5. The vertical delay circuit 40 produces a delay during the vertical time interval indicated between points 43 and 44 of Figure 5. When the scanning beam reaches a point 46 to begin the scan of the display windows 47 and 48, the vertical delay has lapsed and an output is produced on a line 47 (Pigure 4). A line counter 48 then begins counting raster lines as indicated by a series of pulses delivered to the counter 48 at an input 49. The pulses delivered to the input 49 a~e coupled from a gate 50 which has its inputs coupled from like identified inputs of a timing counter 51.
The horizontal delay circuit 39 enables the timing counter 51 ' each time the scanning beam reaches a horizontal position indicated by the dashed line 52 in ~igure 5. When the counter has counted 16 pulses from a keyed osclllator 53, the gate 50 produces the required output pulse which is then fed to the line counter 48. This output pulse indicates the scanning of a single line on the raster.
At the same time that the timing counter 51 is enabled by the ~ ' ".
lapse of the delay associated with the circuit 39, the keyed oscillator 53 is started through a gate 54 which has an output from the vertical delay circuit 40 coupled thereto. With the timing counter started, outputs coupled to AND
gates 55 and 56 provide gating signals to the character generator 11. The gates 55 and 56, in turnJ enable gates in the character generator 11 to couple the signals indicative of the four vertical segments 24, 26, 28 and 30 (Figure 2) to a multiplexer 57.
A seven segment decoder 58 has a series of outputs 59 through 65 ~ -which are coupled to the character generator 11. The first four of these outputs, 59 through 62 represent the four vertical segments, 24, 28, 26 and 30 of the seven segment character of Figure 2. The remaining three outputs represent the three horizontal segments of the character.
The multiplexer 57 has a series of inputs 66 through 72 which are scanned by virtue of timing signals coupled at additional inputs 73 through 75 and derived from the line counter 48. The seven inputs 66 through 72 represent the gated vertical segments and the three horizontal segments derived from the decoder 58. Additional gates 76 and 77 as well as ~' gate 78 and a flip flop circuit 79 are used in performing the blanking function which is described further in conjunction with Figure 6.
, 20 The final output of the circuit is derived at a circuit line 79a which is a digital signal which may be coupled to a suitable video interface , circuit to provide the proper amplitude and isolation.
A data multiplexer 80 is shown in Figure 4 and illustrated in greater detail in Pigure 6. The data multiplexer has units digits and tens digits gates 81 through 88 as shown in Figure 6. Switching from the tens digits to the units digits gates is accomplished at the beginning of the ninth count from the output of the timing counter 51 by way of circuit lines 89 and 90. This permits shifting of the display from the tens display window 47 to the units display window 48 (Figure 5).
The video output from the multiplexer 57 is blanked for all portlons of the scan outslde of the display windows 47 and 48. Firstly, it is blanked by a signal from the vertical delay circuit 40 through the gate ~'~ ' ' ' ' ', - 6 ~-108V3~9 111 and a line 99 to a gate 100 which has an output 101 coupled directly to a seven segment decoder 102. This blanking is accomplished during the verti-cal delay from the top of the raster to the top of the display window as illustrated by the 3 m.s. delay shown in Figure 5.
Two gates lQ3 and 104 provide blanking in the 000 and 111 hori-zontal time intervals as shown in the enlarged display window of Figure 7. ~
The inputs from these gates are derived by the proper combination of signals ~ ;
from the timing counter 51 which includes a gate 105 and a four bit binary counter 106. This blanking is required at the beginning of the horizontal scan and at the end of the scan for each window. The blanking is accomplished ~-by producing '0' inputs to the gate 100 which in turn produces all ones at the output of the decoder 102. The result is that all logic inputs to the multiplexer 57 become logic '1', and there is a '0' logic output.
Blanking is also accomplished after the line counter 48 reaches the last line of the display by producing a logic '1' at the C input of a flip flop 107. This develops a logic '0' at the Q output of the flip flop 107 which, in turn, produces a logic '0' input to the gate 54. The output of the gate 54 turns off the keyed oscillator 53 causing the desired blanking.
The keyed oscillator 53 includes a monostable multivibrator 108. Similar monostable multivibrators 109 and 110 are provided in the circuits 39 and 40.
respectively~. Multivibrators 109 and 110 are adjustable to adjust vertical and horizontal delays.
Blanking to the left of the display window 47 is accomplished by utilizing the Q output of the horizontal delay circuit 39. At the beginning of the horizontal scan, the Q output is '0', producing a '0' output at the gate 111. The output of the gate 111, being '0', then develops a '0' output at the gate 100. This produces all ones at the output of the seven segment .~ .
, decoder 102 resulting in an '0' output for the multiplexer 57.
At the end of the horizontal count, a gate 112 produces a '0' output to generate blanking in the space after the display area. This space is illustrated as 113 in Figure 5. The output of the gate 112 is coupled to the gate 111 which produces blanking in the same manner as described in con- -~ ~ .
~ ~ - 7 -.-- - . . ' .-, ~ - . ~, ~8~349 nection with the blanking in the space to the left of the display window area.
It is also desirable to blank the numeral 0 which would other- -wise appear in the tens digits display window so that Channel 2 appears as "2" rather than "02". This is accomplished by way of a circuit line 113 which is coupled from the input of ~he unit digit gates 81 through 84. The line 113 is connected to an input 114 of the seven segment decoder 102.
During display of the tens digits, the input to the units digits gates is logic '0', and when a 0 would normally be displayed in the tens digit display window, a logic '0' would appear at the output of gates 115 through 118. The seven segment decoder 102 produces a '1' at each output 119 through 125 when a logic '0' appears at its inputs. The result is all logic ones at the input to the multiplexer 57 and a '0' output to the video interface.
The outputs 119 through 122 of the decoder 102 are coupled to gates 126, 127, 128 and 129. These gates provide the switching action for the outputs 119 through 122 which carry the data for the vertical segments of the seven segment font shown in Figure 2. The switching is accomplished further through a pair of gates 130 and 131 which have the proper inputs coupled thereto from the counter 106.
The output of the gates 126 through 129 are coupled to selected 20 inputs of the multiplexer 57, and a plurality of isolation diodes such as the diode 132 are provided as shown.
, The multiplexer 57 receives timing signals from a counter 133 which may be a Eour bit binary counter. This is part of the line counter circuit 48 illustrated in Pigure 4. In this way, the data available at the ~
input to the multiplexer 57 is sampled at the proper time intervals as the ~ ~ -beam scans the raster.
In Figure 8 the digital circuit is modified from that shown in Pigure 6 and includes additional circuitry to provide for a two line, six digit d~,splay ~or the purpose of displa~ing lnformation in addition to the 30 channel nuP~be~, In this part~cula~ emaodi~ent, t~e addit~onal information d~splayed i`s the time of da~.
The time is displayed on the second line of the display in either ~: ' r - .
: . - . , ~ ., - .. . .- . : .
108~349 4 digits (hours and minutes) or six digits (hours, minutes and seconds).
Referring first to the seven segment decoder 102, the data input including gates 81 through 88 and 115 through 118 have been omitted for simplicity. In the embodiment shown in Figure 6, 8 data lines were multi-plexed into 4 lines. In this embodiment, the input data multiplex circuit must now multiplex an additional number of lines into 4 lines. This is accomplished by circuitry similar to that shown in Figure 6.
Counter 106 in Figure 6 was a four bit binary counter. This has been replaced in Figure 8 by an expanded seven bit counter 134 to accommodate a six digit display. The stages 135, 136 and 137 comprise the horizontal character counter and the stage 138 is the "stop" stage. Two positions of the stages 135 through 137 are blanked to provide character spacing.
In the embodiment shown in Figure 6, four bit counter 133 and flip flop 107 comprise the vertical line counter. The vertical line counter in Figure 8 has been expanded to a six bit binary counter to accommodate a second horizontal line of information. This counter is identified by the reference numeral 139. The stage 140 is the vertical character counter, and the stage 141 is the "stop" flip flop. The stage 140 can be switched from modulo 1 to modulo 2 to select channel display only or channel plus time by the logic level of thea "mode" line. Gates 142, 143 and 144 select the output of either the stage 140 for channel only or the stage 141 for channel plus j time display as the "stop" pulse to disable a gate 145 which is similar to the gate 54 of Figure 6.
Gates 146 and 147 decode horizontal character position 000 in the second line of display, causing blanking if the data input at that time is a decimal 0. This position would correspond to the hours tens digits and it is desired to blank a 0 in this digit position for the same reason the 0 is blanked in the tens channel position in Figure 6., Gates 148 and 149 de-code horizontal character positions 011 and 100 respectively. The outputs of these t~o gates are cc~h~ned ~n an OR gate 150 and fed to an lnput of a further gate 151, Gate 152 decodes horiz~ntal character positions 110 and 111, The four~six digit select lines select the output of either gate 151 or ~ E g ... . . .
-8~349 152. The selected output is fed to NOR gate 153. The output of NOR gate 153 when a logic 'O' is the "enable" pulse. This enable pulse is fed to the channel number data multiplexer. When the enable pulse is logic 'O' during line 1, multiplex channel number data will be present at the data inputs of the decoder 102. When the enable line is logic '1' during line 1, 'O' will be present at the data inputs of the decoder 102.
A logic '1' at the four-six digit select line enables gate 152, causing the enable line to be logic 'O' during horizontal character positions 110 and 111. The channel number thus appears in positions 110 and 111. A
logic 'O' on the four-six select line enables gate 151, and the channel number appears in position 011 and 100.
Gate 154 decodes horizontal character position 101. With a logic 'O' on the four-six digit select line, gate 154 is enabled causing the stage 138 of counter 134 to be "set" to logic '1' at the beginning of horizontal ~ character position 101. This is the 'stop' stage of the counter 134. Hence, ; the display is stopped at the end of five hori70ntal character positions or four display digits. When the four-six digit select line is logic '1', gate 154 is disabled thus allowing counter 134 to stop at the end of eight hori-zontal character positions or six display digits. Hence, the signal applied to the four-six select line controls the number of digits to be displayed.
Gate 155 decodes horizontal character position 111. Decoded horizontal position 100 from gate 149 is fed to one input of gate 156 by way of line 157 with the selected output being fed through OR gate 15~ to an in-put 159 of the decoder 102, A logic 'O' at the input 159 disables decoder 102 only if its data input is 'O'. A logic '1' at input 159, enables decoder 102 for any decimal number at the data input.
A logic '1' on the four-six digit select line enables gate 155 whlch in turn, enables decoder 102 during horizontal character position 111.
~ lo~ic ~0~ on the four~six d~git select line enables gate 156, thereby en-abling decoder 102 during posit~on 100.
Gates 160, 161 and 162 supply a ~'select" pulse to the channel number data multiplexer similar to that shown in Figure 6. The stage 135 of ' ' ~ - 10 -counter 134 is fed directly with 'six' digit selected or inverted with 'four' digit selected in order to read out the channel number digits in the correct order.
Gates 163 and 164 decode horizontal character position 010 and 101 which are combined in NOR gate 165 and fed to one input of an AND gate 166. These gates "blank" decoder 102 during those two positions. This pro- -vides the required spacing between characters as discussed in conjunction with the circuit of Figure 6.
Accordingly, it can be seen that the circuit shown in Figure 8 represents an expanded circuit to provide additional character display posi-tions and an additional line of display. A similar system could of course be provided to include additional display information, however, the complexity would increase accordingly.
The function of the output from the decoder 102 is basically the same as that shown in conjunction with Figure 6. The horizontal segment lines . . .
167, 168 and 169 are directly fed to the multiplexer 57, and the vertical -lines 170, 171, 172 and 173 are fed through the gates 126 through 129 to pro-vide the required gating of the vertical segments during the horizontal sweep. Through this system, an effective and realistically priced digital circuit for display of channel number and other information, such as time of day, is provided. This type of circuit then becomes an effective system when used in combination with a varactor tuner operated by electronic channel .
switching.
' .1 :, ....
.. ~''
The use of on-screen display of a channel number, for instance, has been proposed in an article entitled "Broadcast and Television Receivers", IEEE, Vol. BTR-15, No. 2, July 1969, however, the character generators which are available commercial-ly are generally "read only memories" designed to display either 16 or 64 alpha-numeric characters. These character generators require 350 memory bits for 10 characters. In such a device, all 35 possible positions in a 5 x 7 font are used for the numerals.
The character generator is the most expensive element of such a system.
The present invention provides an improved system for the display of characters on the screen of a television receiver using character generating means locally in the receiver.
According to one aspect of the present invention there is provided a system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plur-ality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decod-ing means into a given line segment generated video signal and comprising means for multiplexing the outputs of said decoding means in accordance with the line of scan of the beam of the cathode ray tube of said broadcast television receiver, and means for adding the generated video signal in a video circuit of said broadcast television receiver to develop a character display on . I .
~08034g the raster of the television receiver in addition to any other signal being processed by said video circuit.
According to another aspect of the invention there is provided a system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plur-ality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decoder ;;
into a given line segment generated video signal and comprising an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver and means responsive to the horizontal synchronization signal of received broadcast television signals for keying said oscillator, I and means for adding the generated video signal in a video cir-i cuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.
The features and advantages of the present invention will be understood in greater detail from the following descrip-tion and the associated drawings wherein reference numerals are utilized to designate a preferred embodiment.
Figure 1 is a general block diagram of an on-screen display system according to the present invention.
Figure 2 is an illustration of the line segments used to form the characters in the seven segment decoder according to the present invention.
Figure 3 is a block diagram of the character generator illustrated in Figure 1. ~ -i :, .. .
~ '' ~ ; ~' ' ' ', - ' - - : , ^` 108~349 Figure 4 is a more detailed block diagram of the circuit illustrated in Figure 1.
Figure 5 is an illustration of the screen of a tele-vision receiver showing the positioning of character windows on the screen.
Figure 6 is a schematic of the digital circuit used in the block diagram of Figure 4.
Figure 7 is a detailed illustration of one of the win-dows shown in Figure 5. ;
Figure 8 is a schematic similar in many respects to Figure 6 but including additional circuitry to produce character displays for the proper time of day.
Referring to Figure 1, there is shown a display system according to the present invention. In this figure, a position- -ing and timing circuit 10 is used to position the display on the raster and to provide timing signals to a character generator 11 and to a multiplexer 12.
The output of the multiplexer 12 is coupled to a TV
interface system which is not shown in detail herein, but is the least expensive circuit in the system. Interface would be obvious to a skilled person and can be achieved by simply super-imposing the display over the program video and keeping the display in white or black. Other interface systems could offer variations on the theme by providing the display to be in a given color. The channel number information is provided in the form of a code that iB recognizable by the character generator. In this case, the channel number information is provided in Binary Coded Decimal form. In the present system, BCD code is provided on eight parallel lines, one group of four lines for each channel number digit.
l The data input block 14 in Figure 1 performs the I function of multiplexing the two groups of four lines into one ,''~
~ ,. :
'.t.` ~, ., ., .. , ....... . ' .. ' . ' .. ..... ' ., ,.. :. ', ' .' :,'' .: ' i:' ... .', ' ,. ,', ' ', ,. . :. : . ' ~08~349 group of four lines. In other words, the data input circuit 14 is switching the inputs of the character generator between the two channel number digits.
The character generator is the most expensive part of the system shown in Figure 1. Prior art character generators available for this function are designed to display either 16 or 64 alpha-numeric characters in a 5 X 7 font. The requirement for a channel display is that it be capable of dis-playing the numerals 0 through 9, thus making the 16 character numeric generator a logical choice. However J such a device is too costly for this type of a sys~em. In such character generators, 350 ~5 X 7 X 10) memory bits are required for 10 characters. This device uses all 35 possible positions in a 5 X 7 font of the type shown in Figure 2.
The present invention utilizes the seven segment numeral. In Figure 2, it can be seen that all numerals are constructed from a combination of four vertical straight line segments and three straight horizontal line segments.
The four vertical segments occupy only two of the five vertical columns. Each vertical segment occupies four positions in a column of seven horizontal positions. The center position in columns 1 and 5 are shared by the upper and lower vertical segments.
Each horizontal segment in the font shown in Figure 2 occupies a complete row of five positions. The extreme positions of each horizontal segment are shared with the extreme positions of each vertical segment. Only 23 positions, out of a possible 35 are actually utilized. If the numeral is being scanned horizontally as in a conventional television receiver, it can be seen that if any horizontal segment is selected there is no change in that I row for the entire period that the numeral is being scanned. Accordingly, the 15 positions in the three horizontal rows can be reduced to three positions. The total number of positions required can be reduced to t4 X 4) ~ 3 = 16 ~ 3 = 19 positions. Also, columns 2, 3 and 4 can be ' 30 eliminated from the memory because there will never be any change in those three columns as any row is being scanned.
With the above view of the font shown in Figure 2, memory can be : ' , , 4 :` T~L
`' ~L : : -~, ... , , .. - . - - - .' . ,, .. , . . . - . ~ -1~8~349 eliminated if a seven segment decoder is used to select the segments which are required to construct a given numeral. The selec*ion is accomplished in accordance with a code in BCD form provided at the input to the decoder.
Referring to Figure 3, which further illustrates the character generator 11, a seven segment decoder 15 has seven output lines 17 through 23, one for each of the segments 24 through 30 shown in Figure 2. The three out-put lines 21, 22, and 23 are for the top, center and lower horizontal segments 25, 27 and 29 respectively. The four vertical segment output lines 17, 18, 19 and 20 must first be coupled through gating and isolating circuitry 38.
Such circuitry provides switching action to switch on and off the horizontally scanning electron beam in order to reproduce the vertical segments 24, 26, 28 and 30.
Referring to the block diagram of Figure 4, the timing and positioning function performed by circuit 10 of Figure 1 is initiated by the use of two delay circuits, namely, a horizontal delay circuit 39 and a ' vertical delay circuit 40. The horizontal delay circuit 39 produces a delay during each scan of the cathode ray beam between points 41 and 42 as shown in Figure 5. The vertical delay circuit 40 produces a delay during the vertical time interval indicated between points 43 and 44 of Figure 5. When the scanning beam reaches a point 46 to begin the scan of the display windows 47 and 48, the vertical delay has lapsed and an output is produced on a line 47 (Pigure 4). A line counter 48 then begins counting raster lines as indicated by a series of pulses delivered to the counter 48 at an input 49. The pulses delivered to the input 49 a~e coupled from a gate 50 which has its inputs coupled from like identified inputs of a timing counter 51.
The horizontal delay circuit 39 enables the timing counter 51 ' each time the scanning beam reaches a horizontal position indicated by the dashed line 52 in ~igure 5. When the counter has counted 16 pulses from a keyed osclllator 53, the gate 50 produces the required output pulse which is then fed to the line counter 48. This output pulse indicates the scanning of a single line on the raster.
At the same time that the timing counter 51 is enabled by the ~ ' ".
lapse of the delay associated with the circuit 39, the keyed oscillator 53 is started through a gate 54 which has an output from the vertical delay circuit 40 coupled thereto. With the timing counter started, outputs coupled to AND
gates 55 and 56 provide gating signals to the character generator 11. The gates 55 and 56, in turnJ enable gates in the character generator 11 to couple the signals indicative of the four vertical segments 24, 26, 28 and 30 (Figure 2) to a multiplexer 57.
A seven segment decoder 58 has a series of outputs 59 through 65 ~ -which are coupled to the character generator 11. The first four of these outputs, 59 through 62 represent the four vertical segments, 24, 28, 26 and 30 of the seven segment character of Figure 2. The remaining three outputs represent the three horizontal segments of the character.
The multiplexer 57 has a series of inputs 66 through 72 which are scanned by virtue of timing signals coupled at additional inputs 73 through 75 and derived from the line counter 48. The seven inputs 66 through 72 represent the gated vertical segments and the three horizontal segments derived from the decoder 58. Additional gates 76 and 77 as well as ~' gate 78 and a flip flop circuit 79 are used in performing the blanking function which is described further in conjunction with Figure 6.
, 20 The final output of the circuit is derived at a circuit line 79a which is a digital signal which may be coupled to a suitable video interface , circuit to provide the proper amplitude and isolation.
A data multiplexer 80 is shown in Figure 4 and illustrated in greater detail in Pigure 6. The data multiplexer has units digits and tens digits gates 81 through 88 as shown in Figure 6. Switching from the tens digits to the units digits gates is accomplished at the beginning of the ninth count from the output of the timing counter 51 by way of circuit lines 89 and 90. This permits shifting of the display from the tens display window 47 to the units display window 48 (Figure 5).
The video output from the multiplexer 57 is blanked for all portlons of the scan outslde of the display windows 47 and 48. Firstly, it is blanked by a signal from the vertical delay circuit 40 through the gate ~'~ ' ' ' ' ', - 6 ~-108V3~9 111 and a line 99 to a gate 100 which has an output 101 coupled directly to a seven segment decoder 102. This blanking is accomplished during the verti-cal delay from the top of the raster to the top of the display window as illustrated by the 3 m.s. delay shown in Figure 5.
Two gates lQ3 and 104 provide blanking in the 000 and 111 hori-zontal time intervals as shown in the enlarged display window of Figure 7. ~
The inputs from these gates are derived by the proper combination of signals ~ ;
from the timing counter 51 which includes a gate 105 and a four bit binary counter 106. This blanking is required at the beginning of the horizontal scan and at the end of the scan for each window. The blanking is accomplished ~-by producing '0' inputs to the gate 100 which in turn produces all ones at the output of the decoder 102. The result is that all logic inputs to the multiplexer 57 become logic '1', and there is a '0' logic output.
Blanking is also accomplished after the line counter 48 reaches the last line of the display by producing a logic '1' at the C input of a flip flop 107. This develops a logic '0' at the Q output of the flip flop 107 which, in turn, produces a logic '0' input to the gate 54. The output of the gate 54 turns off the keyed oscillator 53 causing the desired blanking.
The keyed oscillator 53 includes a monostable multivibrator 108. Similar monostable multivibrators 109 and 110 are provided in the circuits 39 and 40.
respectively~. Multivibrators 109 and 110 are adjustable to adjust vertical and horizontal delays.
Blanking to the left of the display window 47 is accomplished by utilizing the Q output of the horizontal delay circuit 39. At the beginning of the horizontal scan, the Q output is '0', producing a '0' output at the gate 111. The output of the gate 111, being '0', then develops a '0' output at the gate 100. This produces all ones at the output of the seven segment .~ .
, decoder 102 resulting in an '0' output for the multiplexer 57.
At the end of the horizontal count, a gate 112 produces a '0' output to generate blanking in the space after the display area. This space is illustrated as 113 in Figure 5. The output of the gate 112 is coupled to the gate 111 which produces blanking in the same manner as described in con- -~ ~ .
~ ~ - 7 -.-- - . . ' .-, ~ - . ~, ~8~349 nection with the blanking in the space to the left of the display window area.
It is also desirable to blank the numeral 0 which would other- -wise appear in the tens digits display window so that Channel 2 appears as "2" rather than "02". This is accomplished by way of a circuit line 113 which is coupled from the input of ~he unit digit gates 81 through 84. The line 113 is connected to an input 114 of the seven segment decoder 102.
During display of the tens digits, the input to the units digits gates is logic '0', and when a 0 would normally be displayed in the tens digit display window, a logic '0' would appear at the output of gates 115 through 118. The seven segment decoder 102 produces a '1' at each output 119 through 125 when a logic '0' appears at its inputs. The result is all logic ones at the input to the multiplexer 57 and a '0' output to the video interface.
The outputs 119 through 122 of the decoder 102 are coupled to gates 126, 127, 128 and 129. These gates provide the switching action for the outputs 119 through 122 which carry the data for the vertical segments of the seven segment font shown in Figure 2. The switching is accomplished further through a pair of gates 130 and 131 which have the proper inputs coupled thereto from the counter 106.
The output of the gates 126 through 129 are coupled to selected 20 inputs of the multiplexer 57, and a plurality of isolation diodes such as the diode 132 are provided as shown.
, The multiplexer 57 receives timing signals from a counter 133 which may be a Eour bit binary counter. This is part of the line counter circuit 48 illustrated in Pigure 4. In this way, the data available at the ~
input to the multiplexer 57 is sampled at the proper time intervals as the ~ ~ -beam scans the raster.
In Figure 8 the digital circuit is modified from that shown in Pigure 6 and includes additional circuitry to provide for a two line, six digit d~,splay ~or the purpose of displa~ing lnformation in addition to the 30 channel nuP~be~, In this part~cula~ emaodi~ent, t~e addit~onal information d~splayed i`s the time of da~.
The time is displayed on the second line of the display in either ~: ' r - .
: . - . , ~ ., - .. . .- . : .
108~349 4 digits (hours and minutes) or six digits (hours, minutes and seconds).
Referring first to the seven segment decoder 102, the data input including gates 81 through 88 and 115 through 118 have been omitted for simplicity. In the embodiment shown in Figure 6, 8 data lines were multi-plexed into 4 lines. In this embodiment, the input data multiplex circuit must now multiplex an additional number of lines into 4 lines. This is accomplished by circuitry similar to that shown in Figure 6.
Counter 106 in Figure 6 was a four bit binary counter. This has been replaced in Figure 8 by an expanded seven bit counter 134 to accommodate a six digit display. The stages 135, 136 and 137 comprise the horizontal character counter and the stage 138 is the "stop" stage. Two positions of the stages 135 through 137 are blanked to provide character spacing.
In the embodiment shown in Figure 6, four bit counter 133 and flip flop 107 comprise the vertical line counter. The vertical line counter in Figure 8 has been expanded to a six bit binary counter to accommodate a second horizontal line of information. This counter is identified by the reference numeral 139. The stage 140 is the vertical character counter, and the stage 141 is the "stop" flip flop. The stage 140 can be switched from modulo 1 to modulo 2 to select channel display only or channel plus time by the logic level of thea "mode" line. Gates 142, 143 and 144 select the output of either the stage 140 for channel only or the stage 141 for channel plus j time display as the "stop" pulse to disable a gate 145 which is similar to the gate 54 of Figure 6.
Gates 146 and 147 decode horizontal character position 000 in the second line of display, causing blanking if the data input at that time is a decimal 0. This position would correspond to the hours tens digits and it is desired to blank a 0 in this digit position for the same reason the 0 is blanked in the tens channel position in Figure 6., Gates 148 and 149 de-code horizontal character positions 011 and 100 respectively. The outputs of these t~o gates are cc~h~ned ~n an OR gate 150 and fed to an lnput of a further gate 151, Gate 152 decodes horiz~ntal character positions 110 and 111, The four~six digit select lines select the output of either gate 151 or ~ E g ... . . .
-8~349 152. The selected output is fed to NOR gate 153. The output of NOR gate 153 when a logic 'O' is the "enable" pulse. This enable pulse is fed to the channel number data multiplexer. When the enable pulse is logic 'O' during line 1, multiplex channel number data will be present at the data inputs of the decoder 102. When the enable line is logic '1' during line 1, 'O' will be present at the data inputs of the decoder 102.
A logic '1' at the four-six digit select line enables gate 152, causing the enable line to be logic 'O' during horizontal character positions 110 and 111. The channel number thus appears in positions 110 and 111. A
logic 'O' on the four-six select line enables gate 151, and the channel number appears in position 011 and 100.
Gate 154 decodes horizontal character position 101. With a logic 'O' on the four-six digit select line, gate 154 is enabled causing the stage 138 of counter 134 to be "set" to logic '1' at the beginning of horizontal ~ character position 101. This is the 'stop' stage of the counter 134. Hence, ; the display is stopped at the end of five hori70ntal character positions or four display digits. When the four-six digit select line is logic '1', gate 154 is disabled thus allowing counter 134 to stop at the end of eight hori-zontal character positions or six display digits. Hence, the signal applied to the four-six select line controls the number of digits to be displayed.
Gate 155 decodes horizontal character position 111. Decoded horizontal position 100 from gate 149 is fed to one input of gate 156 by way of line 157 with the selected output being fed through OR gate 15~ to an in-put 159 of the decoder 102, A logic 'O' at the input 159 disables decoder 102 only if its data input is 'O'. A logic '1' at input 159, enables decoder 102 for any decimal number at the data input.
A logic '1' on the four-six digit select line enables gate 155 whlch in turn, enables decoder 102 during horizontal character position 111.
~ lo~ic ~0~ on the four~six d~git select line enables gate 156, thereby en-abling decoder 102 during posit~on 100.
Gates 160, 161 and 162 supply a ~'select" pulse to the channel number data multiplexer similar to that shown in Figure 6. The stage 135 of ' ' ~ - 10 -counter 134 is fed directly with 'six' digit selected or inverted with 'four' digit selected in order to read out the channel number digits in the correct order.
Gates 163 and 164 decode horizontal character position 010 and 101 which are combined in NOR gate 165 and fed to one input of an AND gate 166. These gates "blank" decoder 102 during those two positions. This pro- -vides the required spacing between characters as discussed in conjunction with the circuit of Figure 6.
Accordingly, it can be seen that the circuit shown in Figure 8 represents an expanded circuit to provide additional character display posi-tions and an additional line of display. A similar system could of course be provided to include additional display information, however, the complexity would increase accordingly.
The function of the output from the decoder 102 is basically the same as that shown in conjunction with Figure 6. The horizontal segment lines . . .
167, 168 and 169 are directly fed to the multiplexer 57, and the vertical -lines 170, 171, 172 and 173 are fed through the gates 126 through 129 to pro-vide the required gating of the vertical segments during the horizontal sweep. Through this system, an effective and realistically priced digital circuit for display of channel number and other information, such as time of day, is provided. This type of circuit then becomes an effective system when used in combination with a varactor tuner operated by electronic channel .
switching.
' .1 :, ....
.. ~''
Claims (25)
1. A system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plur-ality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decoding means into a given line segment generated video signal and com-prising means for multiplexing the outputs of said decoding means in accordance with the line of scan of the beam of the cathode ray tube of said broadcast television receiver, and means for adding the generated video signal in a video circuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.
2. A display system in accordance with Claim 1 wherein said decoding means comprises a seven segment decoder.
3. A display system in accordance with Claim 2 wherein a line counter is provided to count horizontal scans of the cathode ray beam and wherein the output of said counter is coupled to said multiplexer to control the same.
4. A display system in accordance with Claim 1 wherein said decoding means is a seven segment decoder and wherein means are provided to gate the data output of said decoder which re-present the vertical segments of the character to be displayed during given horizontal scans of the beam of the cathode ray tube.
5. A display system in accordance with Claim 1 including timing circuit means, means for multiplexing coded data repre-senting each of said characters in accordance with timing signals from said timing circuit means, a seven segment decoder for decoding said multiplexed data, and means for using said decoded data to apply a video signal to the cathode ray tube of the tele-vision receiver.
6. A display system in accordance with Claim 5 wherein there is provided an oscillator, means for keying the operation of the oscillator to the horizontal sync of the television re-ceiver, and a counter for counting an output of said oscillator and for producing said timing signals.
7. A channel number display system in accordance with Claim 6 wherein said data multiplexer has units digits gates and tens digits gates, said timing signal multiplexing data between said units and tens digits gates into at least four output lines, and means for coupling said multiplexed data to inputs of said seven segment decoder.
8. A channel number display system in accordance with Claim 7 wherein means are provided to blank the display system output for a time interval between the switching of said data multiplexer from the units digits gates to the tens digits gates to provide spacing between the units and tens characters on the raster of the cathode ray tube.
9. A channel number display system in accordance with Claim 8 wherein select means are provided to select one of a greater number of variable character displays, said means in-cluding a BCD signal responsive select circuit.
10. A channel number display system in accordance with Claim 9 wherein said select means includes a four-six character select circuit for selecting either four or six character display.
11. A display system in accordance with Claim 1, said receiver comprising a horizontal scanning circuit, a vertical scanning circuit, a video signal circuit, and a display device coupled to said scanning and video signal circuits, the channel-indicating character on said display device being in the form of line segments oriented in generally horizontal and vertical direc-tions and superimposed over other information displayed thereon, said decoding means producing at each of its said outputs a signal representative of the presence of a corresponding line segment in the character to be displayed; said signal processing circuit means further comprising:
an oscillator coupled to said horizontal scanning circuit and synchronized to the operation of said horizontal scanning circuit and producing a signal at a frequency greater than the horizontal scanning frequency;
counting means coupled to the output of said oscillator and developing signals representative of the position of the horizon-tal scan, gating means coupled to said decoding means and said count-ing means and gating said signals representative of the presence of a corresponding generally vertical line segment in response to the position of the horizontal scan;
matrix means for matrixing said gated signals representa-tive of the presence of corresponding generally vertical line segments and said signals representative of corresponding gener-ally horizontal line segments to form a plurality of line signals each representative of the video signal required to generate said character on said display device during a horizontal scan;
signal selection means for selecting one of said line sig-nals in accord with the position of the vertical scan; and said adding means being coupled to said video signal circuit for combining said selected line signal with a signal representa-tive of said other information being processed by said video cir-cuit.
an oscillator coupled to said horizontal scanning circuit and synchronized to the operation of said horizontal scanning circuit and producing a signal at a frequency greater than the horizontal scanning frequency;
counting means coupled to the output of said oscillator and developing signals representative of the position of the horizon-tal scan, gating means coupled to said decoding means and said count-ing means and gating said signals representative of the presence of a corresponding generally vertical line segment in response to the position of the horizontal scan;
matrix means for matrixing said gated signals representa-tive of the presence of corresponding generally vertical line segments and said signals representative of corresponding gener-ally horizontal line segments to form a plurality of line signals each representative of the video signal required to generate said character on said display device during a horizontal scan;
signal selection means for selecting one of said line sig-nals in accord with the position of the vertical scan; and said adding means being coupled to said video signal circuit for combining said selected line signal with a signal representa-tive of said other information being processed by said video cir-cuit.
12. The display system of Claim 11 wherein said character is displayed in the form of the presence or absence of seven line segments and said decoding means comprises a seven segment decoder having seven outputs and producing at each of said outputs a sig-nal representative of the presence of a corresponding one of said seven line segments in the character to be displayed.
13. The display system of Claim 11 creating at least two characters on said display device wherein said data means develops coded data indicative of the characters to be displayed and said apparatus further comprises multiplex means coupled to said data means, said decoding means and said counting circuitry for apply ing to said decoding means coded data indicative of different characters to be displayed in response to the position of the horizontal scan.
14. The display system of Claim 13 further comprising means for preventing the display of said characters for a time interval including the switching of said multiplex means to provide spacing between said characters.
15. The display system of Claim 11 further comprising a time delay circuit coupled between said oscillator and said hori-zontal scanning circuit and preventing the operation of said oscillator until a predetermined time period has elapsed following the commencement of a horizontal scan.
16. A display system in accordance with Claim 1, said receiver comprising a first scanning circuit for scanning in a first direction, a second scanning circuit for scanning in a second direction generally perpendicular to said first direction, a video signal circuit, and a display device coupled to said scanning and video signal circuits, the channel indicating char-acter on said display device being in the form of line segments oriented in generally said first and second directions and super-imposed over other information displayed thereon, said decoding means producing at each of said outputs a signal representative of the presence of a corresponding line segment in the character to be displayed; said signal processing circuit means further comprising:
timing and gating means coupled to said decoding means and said first scanning circuit and gating said signals representative of the presence of a corresponding line segment in said second direction in response to the position of the scan in said first direction;
matrix means for matrixing said gated signals representative of the presence of corresponding line segments in said second direction and signals representative of corresponding line seg-ments in said first direction to form a plurality of line signals each representative of the video signal required to generate said character on said display device during a scan in said first direction;
signal selection means for selecting one of said line sig-nals in accord with the position of the scan in said second direc-tion; and said adding means being coupled to said video signal circuit for combining said selected line signal with a signal representa-tive of said other information being processed by said video circuit.
timing and gating means coupled to said decoding means and said first scanning circuit and gating said signals representative of the presence of a corresponding line segment in said second direction in response to the position of the scan in said first direction;
matrix means for matrixing said gated signals representative of the presence of corresponding line segments in said second direction and signals representative of corresponding line seg-ments in said first direction to form a plurality of line signals each representative of the video signal required to generate said character on said display device during a scan in said first direction;
signal selection means for selecting one of said line sig-nals in accord with the position of the scan in said second direc-tion; and said adding means being coupled to said video signal circuit for combining said selected line signal with a signal representa-tive of said other information being processed by said video circuit.
17. A system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for pro-cessing the signal on each of said outputs of said decoder into a given line segment generated video signal and comprising an oscillator having a frequency substantially higher than the hori-zontal line frequency of said broadcast television receiver and means responsive to the horizontal synchronization signal of received broadcast television signals for keying said oscillator, and means for adding the generated video signal in a video cir-cuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.
18. A display system in accordance with Claim 17 wherein said circuit means further comprises counting means coupled to the output of said oscillator and developing signals indicative of the horizontal position of the beam of the cathode ray tube of said broadcast television receiver.
19. A display system in accordance with Claim 18 further comprising means coupled to the horizontal scan circuitry of said broadcast television receiver and said counting means for re-setting said counting means.
20. A display system in accordance with Claim 17 further comprising means for multiplexing the outputs of said decoding means in accordance with the line of scan of the beam of the cathode ray tube of said broadcast television receiver.
21. A display system in accordance with Claim 20 wherein a line counter is provided to count horizontal scans of the cathode ray beam and wherein the output of said counter is coupled to said multiplexing means to control the same.
22. A display system in accordance with Claim 21 further comprising means coupled to the horizontal scan circuitry of said broadcast television receiver and said counting means for re-setting said counting means.
23. A channel indicator in a television receiver tunable to a plurality of channels comprising:
a tuning mechanism for tuning the receiver to any one of the channels;
a channel character generator for providing a channel character signal in accordance with the tuned channel for all of the tunable channels, each channel character signal comprising a combination of segment signals defined by both horizontal and vertical position signals;
a receiver circuit arrangement for receiving and amplifying trans-mitted video signals;
a cathode ray tube for projecting a picture in accordance with the received video signals;
means for multiplexing the horizontal and vertical position signals in accordance with the line of scan of the beam of the cathode ray tube; and means for adding video signals from the receiver circuit to the generated channel character signal.
a tuning mechanism for tuning the receiver to any one of the channels;
a channel character generator for providing a channel character signal in accordance with the tuned channel for all of the tunable channels, each channel character signal comprising a combination of segment signals defined by both horizontal and vertical position signals;
a receiver circuit arrangement for receiving and amplifying trans-mitted video signals;
a cathode ray tube for projecting a picture in accordance with the received video signals;
means for multiplexing the horizontal and vertical position signals in accordance with the line of scan of the beam of the cathode ray tube; and means for adding video signals from the receiver circuit to the generated channel character signal.
24. A channel indicator in a television receiver tunable to a plurality of channel comprising:
a tuning mechanism for tuning the receiver to any one of the channels;
a channel character generator for providing a channel character signal in accordance with the tuned channel;
a receiver circuit arrangement for receiving and amplifying transmitted video signals;
a cathode ray tube for projecting a picture in accordance with the received video signals;
means for multiplexing the horizontal and vertical position signals in accordance with the line of scan of the beam of the cathode ray tube; and means for adding the video signals from the receiver circuit to the generated channel character signal.
a tuning mechanism for tuning the receiver to any one of the channels;
a channel character generator for providing a channel character signal in accordance with the tuned channel;
a receiver circuit arrangement for receiving and amplifying transmitted video signals;
a cathode ray tube for projecting a picture in accordance with the received video signals;
means for multiplexing the horizontal and vertical position signals in accordance with the line of scan of the beam of the cathode ray tube; and means for adding the video signals from the receiver circuit to the generated channel character signal.
25. The channel indicator of claim 24 wherein said horizontal and vertical signal generators include time delay means providing, respectively, a blocking signal of selected duration to the channel character generator for positioning the displayed character at a desired location on the tube face.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA193,843A CA1080349A (en) | 1974-03-01 | 1974-03-01 | On-screen channel display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA193,843A CA1080349A (en) | 1974-03-01 | 1974-03-01 | On-screen channel display |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1080349A true CA1080349A (en) | 1980-06-24 |
Family
ID=4099349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA193,843A Expired CA1080349A (en) | 1974-03-01 | 1974-03-01 | On-screen channel display |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1080349A (en) |
-
1974
- 1974-03-01 CA CA193,843A patent/CA1080349A/en not_active Expired
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4081797A (en) | On-screen channel display | |
| US5142576A (en) | System for securely providing restricted video information | |
| US4616261A (en) | Method and apparatus for generating subliminal visual messages | |
| US4476464A (en) | Arrangement for reducing the display size of characters stored in a character store | |
| US3919462A (en) | Method and apparatus for scrambling and unscrambling communication signals | |
| US4698677A (en) | Television receiver arrangements | |
| US4155095A (en) | Chroma control for television control apparatus | |
| GB1132303A (en) | Television message system | |
| EP0497235A2 (en) | Improved teletext transmission receiver | |
| US4486779A (en) | Apparatus to display graphic messages transmitted by videotext systems | |
| US3918039A (en) | High-resolution digital generator of graphic symbols with edging | |
| US4019201A (en) | Method and apparatus for scrambling and unscrambling communication signals | |
| US4284989A (en) | Character display apparatus with facility for selectively expanding the height of displayed characters | |
| US4631585A (en) | Apparatus for synchronizing the operation of a microprocessor with a television synchronization signal useful in generating an on-screen character display | |
| GB1309698A (en) | Symbol display system | |
| GB1486772A (en) | Television systems | |
| CA1080349A (en) | On-screen channel display | |
| US4345243A (en) | Apparatus for generating signals for producing a display of characters | |
| US2972009A (en) | Subscription television system | |
| CA1210855A (en) | Synchronization input for television receiver on- screen alphanumeric display | |
| US2548219A (en) | Interlaced scanning in a television system | |
| US2879324A (en) | Video scrambling and unscrambling system | |
| JPS6231553B2 (en) | ||
| GB2068699A (en) | Character display using two ROM-stored character patterns for each character | |
| JPS5773579A (en) | Television receiver |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |