JPS5821967B2 - phase synchronizer - Google Patents

phase synchronizer

Info

Publication number
JPS5821967B2
JPS5821967B2 JP52133182A JP13318277A JPS5821967B2 JP S5821967 B2 JPS5821967 B2 JP S5821967B2 JP 52133182 A JP52133182 A JP 52133182A JP 13318277 A JP13318277 A JP 13318277A JP S5821967 B2 JPS5821967 B2 JP S5821967B2
Authority
JP
Japan
Prior art keywords
amplifier
frequency
output
voltage
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52133182A
Other languages
Japanese (ja)
Other versions
JPS5466058A (en
Inventor
島山博明
矢野一男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP52133182A priority Critical patent/JPS5821967B2/en
Publication of JPS5466058A publication Critical patent/JPS5466058A/en
Publication of JPS5821967B2 publication Critical patent/JPS5821967B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/14Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【発明の詳細な説明】 この発明は基準周波数信号と電圧制御発振器の出力又は
その周波数変換出力とを位相比較器にて位相比較し、そ
の比較出力を直流増幅器を通じ、更に低域泥波器を通じ
て上記電圧制御発振器へ制御信号として供給する位相同
期装置において、特にその直流増幅器と低域F波器との
間に切替器を挿入すると共に直流増幅器の出力が断にな
った時に電圧制御発振器の制御電圧を保持する機能を設
けた装置に関する。
Detailed Description of the Invention This invention compares the phase of a reference frequency signal and the output of a voltage controlled oscillator or its frequency conversion output using a phase comparator, and passes the comparison output through a DC amplifier and further through a low-frequency wave generator. In the phase synchronization device that supplies the above-mentioned voltage-controlled oscillator as a control signal, a switch is inserted between the DC amplifier and the low-frequency F-wave generator, and the voltage-controlled oscillator is controlled when the output of the DC amplifier is cut off. The present invention relates to a device having a function of holding voltage.

通常の位相同期装置においては、何らかの理由で同期ル
ープが開いた場合に電圧制御発振器に対する制御電圧だ
けは上記ループが開く前の状態を保持することが要求さ
れる場合があり、このため従来においては単に切替器を
使用して保持機能を実現していた。
In a normal phase locking device, if the locking loop opens for some reason, the control voltage for the voltage controlled oscillator may be required to maintain the state before the loop was opened. The holding function was achieved simply by using a switch.

第1図は従来の位相同期装置を示し、通常の状態におい
ては入力端子11より入ってくる周波数F、Nの入力信
号と電圧制御発振器12の出力周波数Fvの信号とが周
波数変換器13で周波数変換され、その変換された周波
数F、Fの出力は方向性結合器14により一部が出力端
子20に取出されると共に他の一部は位相比較器15に
おいて端子16からの基準周波数FRの信号と位相比較
される。
FIG. 1 shows a conventional phase synchronization device. In a normal state, input signals of frequencies F and N input from an input terminal 11 and a signal of an output frequency Fv of a voltage controlled oscillator 12 are converted to a frequency by a frequency converter 13. A part of the output of the converted frequencies F and F is taken out to the output terminal 20 by the directional coupler 14, and the other part is sent to the phase comparator 15 as a signal of the reference frequency FR from the terminal 16. The phase is compared with

位相比較器15からの誤差電圧は直流増幅器17で増幅
され、その増幅出力は切替器18を通じ、更にループ特
性を決める低域戸波器19を通じて電圧制御発振器12
の電圧制御端子に加えられて同期状態、即ち周波数FR
とF、Fとが一定の位相差を残した同一周波数になる。
The error voltage from the phase comparator 15 is amplified by a DC amplifier 17, and the amplified output is sent to the voltage controlled oscillator 12 through a switch 18 and a low-frequency wave filter 19 that determines the loop characteristics.
is applied to the voltage control terminal of FR
, F, and F have the same frequency with a certain phase difference remaining.

この時、端子11からの入力周波数としてFtNの他に
1つ以上の周波数が含まれていて、それらが発振器12
の発振周波数FVとの周波数変換後方向性結合器14を
通じて他の回路に供給されている場合を考えると、例え
ば何らかの原因でFtNの入力信号が断になった時、位
相同期装置が開ループとなり、電圧制御発振器12は無
制御状態となるため、上記他の回路に供給される周波数
も又無制御状態になり、使用不能となる。
At this time, the input frequency from the terminal 11 includes one or more frequencies in addition to FtN, and these frequencies are input to the oscillator 12.
Considering the case where the signal is supplied to other circuits through the directional coupler 14 after frequency conversion with the oscillation frequency FV, for example, when the input signal of FtN is cut off for some reason, the phase synchronization device becomes open loop. Since the voltage controlled oscillator 12 is in an uncontrolled state, the frequencies supplied to the other circuits are also in an uncontrolled state and become unusable.

このような欠点を除くため、第1図に示したように切替
器18が挿入され、開ループとなると同時に強制的に回
路を切り離し、低域P波器19にある蓄電器の放電を防
ぐことによって一定期間電圧制御発振器12の制御電圧
を保持するようにされる。
In order to eliminate such drawbacks, a switch 18 is inserted as shown in Fig. 1, which forcibly disconnects the circuit at the same time as it becomes an open loop, and prevents the condenser in the low-frequency P wave generator 19 from discharging. The control voltage of the voltage controlled oscillator 12 is held for a certain period of time.

しかしこの従来の装置においてはFtNの入力信号が復
帰すると共に再び切替器18によって装置を通常状態に
戻した時、その初期条件によっては再引込みが往々にし
て困難になることがある。
However, in this conventional device, when the FtN input signal is restored and the device is returned to the normal state by the switch 18, it is often difficult to re-engage the device depending on the initial conditions.

この様子を第2図を参照して説明する。This situation will be explained with reference to FIG.

直流増幅器17の出力側をA点、低域沢波器19の出力
側をB点とすると、同期状態の時にはA、B点共に同一
電圧vLになっているが、こ5で例えばFANの入力信
号が時点T。
Assuming that the output side of the DC amplifier 17 is point A, and the output side of the low-frequency wave generator 19 is point B, both points A and B are at the same voltage vL in the synchronized state. The signal is at time T.

FFに断となり、これに伴ってF+Fの変換出力も時点
T。
FF is disconnected, and accordingly, the converted output of F+F is also at time T.

FFで断となると、それを直ちに検出して切替器18は
断にされてB点の電圧はそのまま■Lに保持される。
When the FF is disconnected, it is immediately detected and the switch 18 is disconnected, and the voltage at point B is maintained at ■L.

しかしA点の電圧■A1即ち直流増幅器17の出力電圧
は、位相比較器15の一方の入力信号がないため、位相
比較器15の中心電圧に直流増幅器17の利得がかかっ
た電圧となり、これは一般的には零電圧になる。
However, the voltage A1 at point A1, that is, the output voltage of the DC amplifier 17, is the voltage obtained by multiplying the center voltage of the phase comparator 15 by the gain of the DC amplifier 17, since there is no input signal from one side of the phase comparator 15. Generally, the voltage will be zero.

その後再び時点T。NでFtNの入力信号が到来し、F
lFの変換信号が生じると、それを検出すると共に切替
器18は接の状態にされ、通常の閉ループ装置となる。
Then again at time T. An input signal of FtN arrives at F
When a conversion signal of 1F occurs, it is detected and the switch 18 is closed, resulting in a normal closed loop device.

その結果、直流増幅器17の出力側、即ちA点にはまず
F□とFlFの差周波数が現われ、その後位相同期装置
の引込み動作に入るが、この際にA点の直流分電圧VA
s即ち直流増幅器17の出力電圧と、B点の電圧、即ち
低域沢波器19の保持電圧vLとの差電圧の大きさ及び
その極性によって第2図aの動作概念図に示すように再
引込みする場合と、同図すの動作概念図に示すように完
全に同期はずれになる場合とがある。
As a result, the difference frequency between F
s, that is, the output voltage of the DC amplifier 17, and the voltage at point B, that is, the holding voltage vL of the low-frequency wave generator 19. There are cases where the synchronization occurs, and cases where the synchronization completely goes out as shown in the operational conceptual diagram in the same figure.

これは一般的に位相同期装置の引込み周波数範囲がその
保持周波数範囲よりもかなり狭いことによるためである
This is because the phase synchronizer's pull-in frequency range is generally much narrower than its holding frequency range.

従って第2図a、bの対比でも明らかなように従来の位
相同期装置においてその難点を解決し保持状態後の再引
込みを確実にするためには、保持状態TOFF”TON
間においてのA点の電圧■いとB点の保持電圧vLとの
差電圧が引込み時にループを閉じた瞬間において、その
ループの引込み周波数範囲の値を満足する程度以上率さ
いことが必要である。
Therefore, as is clear from the comparison of Fig. 2 a and b, in order to solve the problems with the conventional phase synchronizer and ensure retraction after the holding state, it is necessary to adjust the holding state TOFF”TON.
It is necessary that the voltage difference between the voltage at point A and the holding voltage vL at point B be set at least to an extent that satisfies the value of the pull-in frequency range of the loop at the moment the loop is closed during pull-in.

なお従来の位相同期装置の構成例を示す第1図では周波
数変換器13を使用しているが、例えば電圧制御発振器
12の出力の一部を直接位相比較器15に入力する位相
同期装置においてFRの基準信号が断となった場合につ
いても同様の動作をし、又同じような問題が生じること
は明らかである。
Although the frequency converter 13 is used in FIG. 1 showing an example of the configuration of a conventional phase synchronization device, for example, in a phase synchronization device in which a part of the output of the voltage controlled oscillator 12 is directly input to the phase comparator 15, the FR It is clear that the same operation will occur and the same problem will occur even when the reference signal is disconnected.

このように一度完全に同期はずれを生じた場合は同期不
能となるため、従来の装置では自動周波数制御回路や掃
引回路等を併用することが必要となり、一般的には再同
期までの時間が長くなる。
Once completely out of synchronization, synchronization becomes impossible, so with conventional equipment it is necessary to use automatic frequency control circuits, sweep circuits, etc., and it generally takes a long time to resynchronize. Become.

この発明の目的はこのような従来の位相同期装置での難
点を解決し入力信号又は基準信号が断になる保持状態時
に、電圧制御発振器の入力電圧をはり一定に保持すると
共に、上記入力信号又は基準信号が回復した時に、確実
に再引込みできる位相同期装置を提供することにある。
The purpose of the present invention is to solve the problems with the conventional phase synchronization device, and to maintain the input voltage of the voltage controlled oscillator at a constant level during the holding state in which the input signal or the reference signal is cut off, and to maintain the input voltage of the voltage controlled oscillator constant. It is an object of the present invention to provide a phase synchronization device that can reliably retract when a reference signal is restored.

この発明によれば位相比較器の出力を増幅する直流増幅
器の出力と、電圧制御発振器の制御信号を供給する低域
ろ波器の出力との差を差動増幅器にてとり、入力信号又
は基準信号、つまり位相比較器の入力が断になると切替
え手段を動作させて所定電位から、上記差動増幅器の出
力を切替えて上記直流増幅器へこれに対する基準電位と
して供給する。
According to this invention, the difference between the output of the DC amplifier that amplifies the output of the phase comparator and the output of the low-pass filter that supplies the control signal of the voltage controlled oscillator is taken by the differential amplifier, and the input signal or reference signal is When the signal, that is, the input to the phase comparator is cut off, the switching means is operated to switch the output of the differential amplifier from a predetermined potential and supply it to the DC amplifier as a reference potential for this.

このようにして入力信号又は基準信号が断になった場合
に、直流増幅器の出力は低域P波器の出力と常に等しく
なるように動作し、従って位相比較器への入力が回復し
ループを閉じた瞬間において直ちに同期状態となって、
同期保持状態となるため、等制約に引込み範囲が同期保
持の周波数範囲まで拡大されることになり、確実に再引
込みが行なわれる。
In this way, when the input signal or reference signal is interrupted, the output of the DC amplifier always operates equal to the output of the low-pass P-wave generator, thus the input to the phase comparator is restored and the loop is closed. The moment it closes, it immediately becomes synchronized,
Since the synchronization is maintained, the pull-in range is expanded to the frequency range of the synchronization with equal constraints, and re-lock is reliably performed.

この発明による位相同期装置の一例を第3図に第1図と
対応する部分に同一符号を付けて示す。
An example of a phase synchronization device according to the present invention is shown in FIG. 3, in which parts corresponding to those in FIG. 1 are given the same reference numerals.

この発明によれば直流増幅器17の出力及び低域F波器
19の出力が分岐されて差動増幅器21へ供給される。
According to this invention, the output of the DC amplifier 17 and the output of the low-frequency F-wave generator 19 are branched and supplied to the differential amplifier 21.

この差動増幅器21の出力と所定電位、この例では接地
電位を切替器22にて切替えて直流増幅器17に基準電
位として供給される。
The output of the differential amplifier 21 and a predetermined potential, in this example the ground potential, are switched by a switch 22 and supplied to the DC amplifier 17 as a reference potential.

こ5で差動増幅器21の伝達特性はこの装置の周波数特
性、応答速度、安定性等を考慮して選ぶ必要があるが、
一般的に充分大きな直流利得と共に適当な低域ろ波特性
が要求される。
In this case, the transfer characteristics of the differential amplifier 21 must be selected taking into account the frequency characteristics, response speed, stability, etc. of this device.
Generally, a sufficiently large DC gain and appropriate low-pass filtering characteristics are required.

切換器22は切換器18と連動して動作されることが好
ましい。
Preferably, the switch 22 is operated in conjunction with the switch 18.

こ\で連動とは時間的に全く同時と云うことではなく、
一方が先になることもあるが、一方が動作すれば他方も
必ず動作することである。
Here, interlocking does not mean exactly the same time,
One may come first, but if one works, the other will always work as well.

切替器22の一方の入力となる所定電位は、この位相同
期装置が通常の動作状態にある場合に直流増幅器17の
基準電圧を必要とする端子に与える電圧で、一般的には
零電圧である。
The predetermined potential that becomes one input of the switch 22 is the voltage applied to the terminal that requires the reference voltage of the DC amplifier 17 when this phase synchronization device is in a normal operating state, and is generally zero voltage. .

この構成において切替器18が位相同期装置を閉じる通
常の動作状態の側にある場合は切替器22は所定電位側
にあり、これが直流増幅器17の基準端子に寿えられる
In this configuration, when the switch 18 is on the side of the normal operating state in which the phase synchronization device is closed, the switch 22 is on the predetermined potential side, which is served as the reference terminal of the DC amplifier 17.

切替器18が位相同期装置のループを開き保時状態に入
ると共に切替器22も切替って差動増幅器21の出力電
圧を直流増幅器17の基準端子に与えるように連動動作
の制御が行なわれている。
The interlocking operation is controlled such that when the switch 18 opens the loop of the phase synchronization device and enters the time keeping state, the switch 22 also switches to apply the output voltage of the differential amplifier 21 to the reference terminal of the DC amplifier 17. There is.

従って、通常の状態においては差動増幅器21の出力側
はこの装置から切り離されて位相同期装置のみとなって
いるが、保持状態においては、直流増幅器17の出力電
圧が挙動増幅器21及び切替器22を通って直流増幅器
17の基準端子に戻る負帰還回路が構成される。
Therefore, in a normal state, the output side of the differential amplifier 21 is separated from this device and becomes only a phase synchronization device, but in a holding state, the output voltage of the DC amplifier 17 is A negative feedback circuit that returns to the reference terminal of the DC amplifier 17 through the negative feedback circuit is configured.

よって差動増幅器21の一方に入っているB点の電圧、
即ち低域泥波器19の出力が直流増幅器1Tの基準電圧
となり、この直流増幅器17の入力電圧の変動を、その
基準端子側の電圧によって補正し、直流増幅器17の出
力、即ちA点の電圧がB点の電圧と等しくなるように動
作する。
Therefore, the voltage at point B entering one side of the differential amplifier 21,
That is, the output of the low-frequency muddy waver 19 becomes the reference voltage of the DC amplifier 1T, and fluctuations in the input voltage of the DC amplifier 17 are corrected by the voltage on the reference terminal side, and the output of the DC amplifier 17, that is, the voltage at point A, is corrected by the voltage on the reference terminal side. It operates so that the voltage becomes equal to the voltage at point B.

即ち保持状態においてA点の電圧とB点の電圧とが常に
等しくなるように帰還がかかる。
That is, feedback is applied so that the voltage at point A and the voltage at point B are always equal in the holding state.

この結果、先の動作説明から明らかなように保持状態後
の再引込みの場合に必らず同期が確立する。
As a result, as is clear from the previous explanation of the operation, synchronization is always established in the case of retraction after the holding state.

従って位相比較器15の入力信号が回復すると切替器1
8.22を適当な時定数で通常の状態に戻すことにより
同期保持状態によって通常の位相同期装置となる。
Therefore, when the input signal of the phase comparator 15 is restored, the switch 1
By returning 8.22 to the normal state with an appropriate time constant, it becomes a normal phase synchronizer in the synchronization holding state.

以上説明したようにこの発明では保持機能を有する位相
同期装置に差動増幅器21及び切替器22を付加するこ
とによって保持後の再引込み可能な周波数範囲を、この
位相同期装置の持っている引込み周波数特性の範囲から
保持周波数特性の範囲まで拡大することによって同期不
能の状態を防ぐことができ、このことは保持機能を有す
る位相同期装置の応用分野を格段に広げるものであり、
しかも簡単な構成を付加すればよくその効果は極めて太
きいものである。
As explained above, in the present invention, by adding the differential amplifier 21 and the switch 22 to the phase synchronization device having a holding function, the frequency range in which retraction can be performed after holding can be adjusted to the retraction frequency that the phase synchronization device has. By expanding the range of characteristics to the range of holding frequency characteristics, it is possible to prevent synchronization failure, which greatly expands the field of application of phase synchronizers with holding functions.
Moreover, it is only necessary to add a simple configuration, and the effect is extremely large.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の保持機能を備えた位相同期装置を示すブ
ロック図、第2図は保持後の再引込みの際の動作説明図
、第3図はこの発明による保持機能を備えた位相同期装
置の一実施例を示すブロック図である。 11:入力端子、12:電圧制御発振器、13:周波数
変換器、14二方向性結合器、15:位相比較器、16
二基準信号入力端子、17:直流増幅器、18:切替器
、19:低域泥波器、20:出力端子、21:差動増幅
器、22:切替器。
Fig. 1 is a block diagram showing a conventional phase synchronization device with a holding function, Fig. 2 is an explanatory diagram of the operation during retraction after holding, and Fig. 3 is a phase synchronization device with a holding function according to the present invention. FIG. 2 is a block diagram showing one embodiment of the present invention. 11: Input terminal, 12: Voltage controlled oscillator, 13: Frequency converter, 14 Bidirectional coupler, 15: Phase comparator, 16
Two reference signal input terminals, 17: DC amplifier, 18: switching device, 19: low frequency muddy wave device, 20: output terminal, 21: differential amplifier, 22: switching device.

Claims (1)

【特許請求の範囲】[Claims] 1 基準信号と電圧制御発振器の出力信号又はこの出力
信号及び入力信号を周波数変換器で周波数変換して得ら
れた周波数変換出力とを位相比較器にて位相比較し、そ
の出力を直流増幅器及び低域F波器を通じて上記電圧制
御発振器へ供給する位相同期装置に対して上記直流増幅
器と低域泥波器との間に切替器を備え、上記基準信号も
しくは上記入力信号が遮断される保持状態において上記
低域沖波器と上記直流増幅器間を電気的に遮断し、上記
低域沖波器の出力信号を保持する保持機能を持たせた装
置において、上記直流増幅器の出力信号及び上記低域P
波器の出力信号が2つの入力端子にそれぞれ与えられる
差動増幅器と、その差動増幅器の出力信号と所定電位と
を切替えて上記直流増幅器の基準電圧端子へ供給する切
替え手段とを具備し、上記保持状態において上記直流増
幅器の出力信号が上記低域沖波器の出力信号と等しくな
るように作動することを特徴とする位相同期装置。
1 A phase comparator compares the phases of the reference signal and the output signal of the voltage controlled oscillator or the frequency conversion output obtained by frequency converting this output signal and the input signal with a frequency converter, and the output is compared with the output signal of the DC amplifier and the frequency converter. A switch is provided between the DC amplifier and the low-frequency wave generator for the phase synchronization device that supplies the voltage controlled oscillator through the F-frequency wave generator, and in a holding state in which the reference signal or the input signal is cut off. In a device having a holding function of electrically interrupting the low-frequency wave transducer and the DC amplifier and holding the output signal of the low-frequency wave transducer, the output signal of the DC amplifier and the low-frequency P
a differential amplifier to which output signals of the DC amplifier are applied to two input terminals, and switching means for switching between the output signal of the differential amplifier and a predetermined potential and supplying the same to the reference voltage terminal of the DC amplifier, A phase synchronization device characterized in that it operates so that the output signal of the DC amplifier becomes equal to the output signal of the low-frequency wave transducer in the holding state.
JP52133182A 1977-11-07 1977-11-07 phase synchronizer Expired JPS5821967B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52133182A JPS5821967B2 (en) 1977-11-07 1977-11-07 phase synchronizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52133182A JPS5821967B2 (en) 1977-11-07 1977-11-07 phase synchronizer

Publications (2)

Publication Number Publication Date
JPS5466058A JPS5466058A (en) 1979-05-28
JPS5821967B2 true JPS5821967B2 (en) 1983-05-06

Family

ID=15098593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52133182A Expired JPS5821967B2 (en) 1977-11-07 1977-11-07 phase synchronizer

Country Status (1)

Country Link
JP (1) JPS5821967B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2515902B1 (en) * 1981-11-03 1985-12-06 Telecommunications Sa DIGITAL CLOCK SYNCHRONIZATION DEVICE AND ITS APPLICATION TO CONNECTION NETWORKS

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5225551A (en) * 1975-08-22 1977-02-25 Nippon Telegr & Teleph Corp <Ntt> Phase synchronization oscillator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5225551A (en) * 1975-08-22 1977-02-25 Nippon Telegr & Teleph Corp <Ntt> Phase synchronization oscillator

Also Published As

Publication number Publication date
JPS5466058A (en) 1979-05-28

Similar Documents

Publication Publication Date Title
US4835481A (en) Circuit arrangement for generating a clock signal which is synchronous in respect of frequency to a reference frequency
EP0583804B1 (en) A phase locked loop circuit
GB2317279A (en) Frequency synthesisers
EP0698313B1 (en) Method for starting a radio transmitter and a radio transmitter
JP2003051742A (en) Clock generating circuit
KR20000022354A (en) Method of and arrangement for controlling oscillator
JPS5821967B2 (en) phase synchronizer
JPH04369927A (en) Pll oscillator
US5461345A (en) Frequency synchronous circuit for reducing transition period from power on state to stable state
US5018015A (en) Adaptive keyed synchronous detector
US3534284A (en) Automatic phase-locking circuit
JPS60248022A (en) Frequency synthesizer
JPH02305024A (en) Phase locked loop circuit
JP2907639B2 (en) Phase locked loop
JPS63276921A (en) Pll circuit
JP2705544B2 (en) Phase locked loop
JPH01141419A (en) Pll circuit
GB1490849A (en) Phase shift circuits
KR900002355B1 (en) Phase synchronous loop filter circuit for survey audio tone
JPS59133734A (en) Phase locked circuit
JPS581574B2 (en) Multiplex wireless relay device
JPH02272913A (en) Pll circuit
JPH0575590A (en) Synchronizing clock generating circuit
JPS5915235B2 (en) phase synchronizer
JP2859037B2 (en) Double PLL circuit