JPS58218792A - Method of producing thin film el element - Google Patents

Method of producing thin film el element

Info

Publication number
JPS58218792A
JPS58218792A JP57100963A JP10096382A JPS58218792A JP S58218792 A JPS58218792 A JP S58218792A JP 57100963 A JP57100963 A JP 57100963A JP 10096382 A JP10096382 A JP 10096382A JP S58218792 A JPS58218792 A JP S58218792A
Authority
JP
Japan
Prior art keywords
insulating layer
thin film
pinhole
transparent electrode
producing thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57100963A
Other languages
Japanese (ja)
Inventor
雅行 脇谷
謙次 岡元
佐藤 精威
三浦 照信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57100963A priority Critical patent/JPS58218792A/en
Publication of JPS58218792A publication Critical patent/JPS58218792A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (al  発明の技術分野 本発明は薄膜EL素子の製造方法に係り、特に薄II!
jiEL素子の下部電極と発光層との間に介装された絶
縁層のピンホールに起因する絶縁破壊の発生を防止する
ための製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for manufacturing a thin film EL device, and particularly to a method for manufacturing a thin film EL device.
The present invention relates to a manufacturing method for preventing dielectric breakdown caused by pinholes in an insulating layer interposed between a lower electrode and a light emitting layer of a jiEL element.

(bl  従来技術と問題点 薄膜EL素子は透明絶縁基板上に、下部透明電極、餉l
の絶縁層、ZnS:Mnよりなる発光層。
(bl) Conventional technology and problems Thin film EL devices are made of a transparent insulating substrate, a lower transparent electrode, a
an insulating layer made of ZnS:Mn, and a light emitting layer made of ZnS:Mn.

第2の絶縁層、上部電極とが順次積層された構造を有す
る。
It has a structure in which a second insulating layer and an upper electrode are sequentially laminated.

かかる構成とされたEL素子内部の第1の絶縁層は、E
L素子の動作時に例えば10(V/cm〕という高電界
にさらされるため、ピンポール等の欠陥があるとその部
分で絶縁破壊が生じ易い。
The first insulating layer inside the EL element having such a structure is E
During operation of the L element, it is exposed to a high electric field of, for example, 10 (V/cm), so if there is a defect such as a pin pole, dielectric breakdown is likely to occur at that part.

即ち、このような欠陥を有する素子は、駆動電圧を印加
されたときに形成される高電界によりピンホール部で絶
縁破壊が起り、ジュール熱のためその部分の膜質が劣化
し、これが更に破壊を招(ため、破壊がますます拡大す
る。そのため画素欠けや電極の断線を生じる。
In other words, in an element with such a defect, dielectric breakdown occurs at the pinhole part due to the high electric field formed when a driving voltage is applied, and the film quality in that part deteriorates due to Joule heat, which causes further breakdown. As a result, the damage is further expanded, resulting in pixel chipping and electrode disconnection.

従ってEL素子の信頼度を向上するためには、ピンホー
ル等の発生を防止しなければならないが、かかる欠陥は
薄膜形成工程において確率的に発生する性格のものであ
4で、これを皆無とすることは極めて困難である。
Therefore, in order to improve the reliability of EL elements, it is necessary to prevent the occurrence of pinholes, etc. However, such defects occur stochastically in the thin film forming process4, so it is necessary to eliminate them completely. It is extremely difficult to do so.

(C)  発明の目的 本発明の目的はかかる事情に鑑みて、上記第1の絶縁層
にピンホールが発生しても絶縁破壊を生じ難い薄膜EL
素子の製造方法を提供することにある。
(C) Purpose of the Invention In view of the above circumstances, the purpose of the present invention is to provide a thin film EL that does not easily cause dielectric breakdown even if a pinhole occurs in the first insulating layer.
An object of the present invention is to provide a method for manufacturing an element.

(d)  発明の構成 本発明の特徴は、絶縁基゛板上に、下部電極とその上に
第1の絶縁層を形成した被処理試料を、該第1の絶縁層
とは反応せず前記下部電極と反応するエツチング液に浸
漬する工程を施すことにより透明電極のピンホール直下
部分を除去し、しかる後前記第1の絶縁層上に発光層と
その上に第2の絶縁層を形成することにある。
(d) Structure of the Invention The feature of the present invention is that a sample to be processed, which has a lower electrode and a first insulating layer formed thereon on an insulating substrate, can be treated without reacting with the first insulating layer. A portion of the transparent electrode directly below the pinhole is removed by immersing it in an etching solution that reacts with the lower electrode, and then a light emitting layer is formed on the first insulating layer and a second insulating layer is formed thereon. There is a particular thing.

(el  発明の実施例 以下本発明の一実施例をその製造工程の順に第1図〜第
3図により説明する。
(el) Embodiment of the Invention An embodiment of the invention will now be described in the order of its manufacturing process with reference to FIGS. 1 to 3.

図において、■はガラス基板、2はIn、O。In the figure, ■ is a glass substrate, and 2 is In and O.

/ S n O@よりなる下部透明電極であって、厚さ
凡そ2000 (人〕、3はY、0.をスパッタ法によ
り凡そ3000 (人〕の厚さに被着せしめて形成した
第1の絶縁層である。この第1の絶縁層3には前述した
如くピンホール41が確率的に発生する。
The first lower transparent electrode is made of / S n O@ and has a thickness of approximately 2000 mm, and is formed by depositing Y and 0.0 by sputtering to a thickness of approximately 3000 mm. This is an insulating layer.As described above, pinholes 41 are generated stochastically in this first insulating layer 3.

前述の如くこのピンホール4をそのままにしでおくと種
々の障害が発生する。そこでこれを防止するために、下
層の透明電極2はエツチングするがその上の第1の絶縁
N3とは反応しないエツチング液、例えば凡そ45(’
C)に加熱した塩酸(HCl)溶液中に上記基板を浸漬
する。
As mentioned above, if this pinhole 4 is left as it is, various problems will occur. Therefore, in order to prevent this, an etching solution that etches the underlying transparent electrode 2 but does not react with the first insulating layer N3 above it, for example, approximately 45%
C) The substrate is immersed in a hydrochloric acid (HCl) solution heated to .

すると第2図にみ、られるようにピンホール4中にエツ
チング液がしみ込み、透明電極2のピンホール4直下部
分が除去され、空隙5が形成される。
Then, as shown in FIG. 2, the etching solution seeps into the pinhole 4, removing the portion of the transparent electrode 2 directly below the pinhole 4, and forming a gap 5.

本工程の間、第1の絶縁層3は上記エツチング液とは反
応しないので、ピンホール4が拡大することはない。な
お本工程を実施するに際し、透明電極2の端部等の露出
部分は、レジスト膜6により被覆し、エツチング液によ
って除去されないよう保護しておく。
During this step, the first insulating layer 3 does not react with the etching solution, so the pinhole 4 does not enlarge. Note that when carrying out this step, exposed parts such as the ends of the transparent electrode 2 are covered with a resist film 6 to protect them from being removed by the etching solution.

このあとは通常の工程に従って進めてよい。即ち、上記
レジスト膜6を除去したのち、ZnS :Mnよりなる
発光層7、スパッタリング法によりY、0.よりなる第
2の絶縁層8 (厚さは例えば凡そ2000 (人〕)
、アルミニウム(/l)よりなる上部電極9を形成する
。かくして第3図に     、i示すような薄膜EL
素子の完成体が得られる。
After this, you can proceed according to the normal process. That is, after removing the resist film 6, a light-emitting layer 7 made of ZnS:Mn is coated with Y, 0. A second insulating layer 8 (thickness is, for example, approximately 2000 (people))
, an upper electrode 9 made of aluminum (/l) is formed. Thus, in FIG. 3, a thin film EL as shown in i
A completed device is obtained.

以上のようにして得られた本実施例による薄膜EL素子
は、ピンホール4直下部分は空隙5とされ、対応する透
明電極2が存在しない。従って駆動電圧が印加された場
合においても、従来構造の素子のようにピンホール4を
介して電流が流れることがなくなり、絶縁破壊を生じ難
い。
In the thin film EL device according to this example obtained as described above, the portion directly below the pinhole 4 is a gap 5, and the corresponding transparent electrode 2 is not present. Therefore, even when a driving voltage is applied, current does not flow through the pinhole 4 as in an element with a conventional structure, and dielectric breakdown is less likely to occur.

なお上記一実施例では第1の絶縁層3をy、o。In the above embodiment, the first insulating layer 3 is y, o.

を用いて形成したが、第1の絶縁層3の材料はこれに限
定されるものではなく、例えばアルミナ(Aj!、O,
)、窒化シリコン<sis N4 ) 、或いは酸化タ
ンタル(T a −Os )等を用いることも出来る。
However, the material of the first insulating layer 3 is not limited to this, for example, alumina (Aj!, O,
), silicon nitride<sisN4), tantalum oxide (T a -Os), etc. can also be used.

要は第1の絶縁層3を透明電極2のみを選択的にエツチ
ングし得るエツチング液が得られる絶縁材料で形成すれ
ばよい。
In short, the first insulating layer 3 may be formed of an insulating material from which an etching solution capable of selectively etching only the transparent electrode 2 can be obtained.

(f)  発明の詳細 な説明した如く本発明によれば、絶縁破壊を生じる恐れ
の少ない薄膜EL素子が得られ、薄膜EL素子の信頼度
が向上する。
(f) Detailed Description of the Invention According to the present invention, a thin film EL device with less risk of dielectric breakdown can be obtained, and the reliability of the thin film EL device can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第3図は本発明の一実施例をその製造工程の順
に示す要部断面図である。 図において、■はガラス基板、2は下部透明電極、3は
第1の絶縁層、4はピンホール、5は空隙、6はレジス
ト膜、7は発光層、8は第2の絶縁層、9は上部電極、
を示す。
FIGS. 1 to 3 are sectional views of essential parts of an embodiment of the present invention showing the manufacturing steps thereof in order. In the figure, ■ is a glass substrate, 2 is a lower transparent electrode, 3 is a first insulating layer, 4 is a pinhole, 5 is a void, 6 is a resist film, 7 is a light emitting layer, 8 is a second insulating layer, 9 is the upper electrode,
shows.

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板上に、下部電極とその上に第1の絶縁層を形成
した被処理試料を、該第1の絶縁層とは反応せず前記下
部電極と反応するエツチング液に浸漬する工程を施した
後、前記第1の絶縁層上に発光層とその上に第2の絶縁
層を形成することを特徴とする薄膜EL素子の製造方法
A process of immersing a sample to be processed having a lower electrode and a first insulating layer formed thereon on an insulating substrate in an etching solution that does not react with the first insulating layer but reacts with the lower electrode. A method for manufacturing a thin film EL device, characterized in that, after that, a light emitting layer is formed on the first insulating layer and a second insulating layer is formed on the light emitting layer.
JP57100963A 1982-06-11 1982-06-11 Method of producing thin film el element Pending JPS58218792A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57100963A JPS58218792A (en) 1982-06-11 1982-06-11 Method of producing thin film el element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57100963A JPS58218792A (en) 1982-06-11 1982-06-11 Method of producing thin film el element

Publications (1)

Publication Number Publication Date
JPS58218792A true JPS58218792A (en) 1983-12-20

Family

ID=14288004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57100963A Pending JPS58218792A (en) 1982-06-11 1982-06-11 Method of producing thin film el element

Country Status (1)

Country Link
JP (1) JPS58218792A (en)

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