JPS58218274A - Vertical deflection circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a titled circuit and to improve the reliability of a vertical deflection circuit which can correspond to plural vertical synchronizing frequencies, by using a transistor to switch the current suction amount. CONSTITUTION:When a vertical synchronizing signal is inputted into an input terminal 1, the grounding voltage for keeping a transistor 32 off is supplied to a switching controlling terminal 33 to generate a sawtooth wave to a terminal 9. On the other hand, when a vertical synchronizing signal of a short cycle is inputted, the voltage for turning on the transistor 32 is supplied to the switching controlling terminal 33 so that a resistor 31 becomes an emitter resistor of a transistor 4 in parallel with a resistor 6. Since the suction current of the transsistor 4 is increased as the result of it, the sawtooth wave appearing in the terminal 9 can be made to the same amplitude so that no switching circuit such as a feedback circuit is required.

Description

[Detailed Description of the Invention] The present invention relates to a vertical deflection circuit of a television receiver.
In particular, the present invention relates to a vertical deflection circuit that can accommodate a plurality of vertical synchronization frequencies.

Figure 1 is a circuit diagram showing a conventional vertical deflection circuit configured to support two types of vertical synchronization frequencies. input terminal of (referred to as "synchronization signal"),
2) is a pnp type first transistor whose base is connected to the input terminal, (3) is a power supply that supplies a constant positive voltage to the emitter of the first transistor, and (4) is a pnp type first transistor whose collector is connected to the first transistor.
A second npn transistor (7) is connected to the collector of the transistor (3), and has a base supplied with a positive voltage from the power supply (5) and an emitter grounded via a resistor (6). Collector 4 of transistor (2)
and the ground point, (8) is the first
The collector of the transistor (2) is connected to the positive input terminal (9
) is connected to the amplifier (9), the vertical deflection coil (11) has one end connected to the output of the amplifier (9), and (11) is the amplifier (8).
A part of the voltage from the other end of the vertical deflection coil uQ to the ground point is transferred to the negative feedback terminal of Negative feedback is provided to the negative feedback terminal (11).(2) is a switch for switching the negative addition IRJt.

2 and 3 are waveform diagrams for explaining the operation of this conventional circuit. In the conventional circuit of FIG. 1, the input terminal (
When a vertical synchronizing signal as shown in FIG. 2 A' is input to 1), the first transistor (2) is turned on during the negative pulse period, and the capacitor is connected from the J power supply (3) through the first transistor (2). j (7J Vi is charged to the □ voltage of the power supply (3). On the other hand, X'' second transistor (4)
:111' During the pulse period, the first transistor (2) is turned off, so the charge t stored in the capacitor (7) is discharged by the constant current. Therefore, the voltage waveform at the positive input terminal (9) of the amplifier (9) becomes a continuous wave as shown in FIG. 2B. This sawtooth wave is subjected to voltage amplification and current amplification for driving the deflection coil by an amplifier (8), and is output to the deflection coil 4. Most of this deflection current is in the deflection coil H.

0 flowing through capacitor 99) and resistor (15)
Therefore, the capacitor cap is usually 100 .mu.F or more, and the resistor 111i) is usually several ohms or less. Resistors IJ4, 03), H and capacitor V constitute a DC feedback circuit, and resistor 02) and capacitor Vt
zryr is a low-pass filter that attenuates the AC component, and the resistance is 0.
2) and the ratio of the bet to the resistance (14) determines the #velocity. The resistors oj>, a7), (18) and the switch (2) constitute an AC feedback circuit, and the voltage appearing across the resistor is proportional to the amount of deflection current; the, the ratio of 0η and the condensation V
Through siυb-CMm(11)′1″^,,) Yayoyo,
picture. □Car. .

It is superimposed with the DC feedback signal and fed back to the negative feedback terminal (□) of the IM amplifier (8).The resistor and switch are used to change the amount of AC feedback. First, as mentioned above, switch (
Suppose that a sawtooth wave as shown in FIG. 2B is obtained at the terminal (9) in response to a vertical synchronizing signal having a period as shown in FIG. In this state, if a vertical synchronizing signal with a short period as shown in Figure 3A is input, the terminal (
9), as shown in FIG. 3B, a sawtooth wave having a smaller amplitude than the waveform of FIG. 2B described above is generated. Therefore, if the loop gain below the amplifier (8) is constant, the vertical deflection current amplitude will also become small, which will cause problems in television reception. In such a case, if switch (2) is turned on, resistor (18) is connected in parallel with resistor (+7)K, so the amount of AC feedback is small and the loop gain increases, as shown in Figure 3. As shown in C, a vertical deflection current amplitude equivalent to the waveform in M2 diagram B is obtained.

As mentioned above, in conventional circuits, the DC component is completely removed from the AC feedback circuit, so transistors cannot be used as switches (A), and relays must be used.
Problems with reliability and price were common. If the capacitor Qυ is short-circuited in order to introduce a DC component into the circuit of the switch (4), the amount of DC feedback will also change depending on whether the switch (2) is turned on or off, so the capacitor eη cannot be omitted.

This statement was made in view of the above points.
Therefore, instead of changing the feedback amount as in the conventional method, the current sinking amount of the constant current sinking circuit for generating sawtooth waves is changed, and by using a transistor for this, a simple configuration is possible. The object of the present invention is to provide a vertical deflection circuit with high reliability and constant amplitude output.

FIG. 4 is a circuit diagram showing an embodiment of Jin's invention, and parts equivalent to those of the conventional example of FIG. 1 are designated by the same reference numerals. Resistor c3 is the second
One end is connected to the emitter of the transistor (4), and the other end is connected to the collector of the third npn transistor (4). The lead of the third transistor (2) is connected to the switching control terminal (g).

In this embodiment circuit, when a duty synchronization signal as shown in FIG. When supplied, nine sawtooth waves as shown in FIG. 2B, which are exactly the same as in the conventional example shown in FIG. 1, are generated at the terminal (9). On the other hand, when a vertical synchronization signal with a short period as shown in FIG. 3A is input, a voltage that turns on the third transistor is supplied to the switching control terminal ■.
A resistor Cρ is connected to the second transistor (4) in parallel with the resistor (6).
) so that it becomes the eminter resistance. As a result, the suction magnetic current of the second transistor (4) increases, so that the sawtooth υ wave appearing at the terminal (9) is as shown in Figure 3C, which is different from the waveform in Figure 2B above. It is possible to buy the same amplitude. Therefore, the loop gain of the amplifier (8) only needs to be kept constant, and a switching circuit such as a feedback circuit is not required, and a relay or an extra capacitor as in the conventional case is not required.

As described above, in the vertical deflection circuit of the present invention, the capacitor is charged to a predetermined voltage during the supply period of the vertical synchronizing signal or pulses synchronized with the vertical synchronizing signal, and the
% to obtain a sawtooth waveform voltage by sinking a predetermined current into the sink circuit, and when the frequency of the vertical synchronization signal is high, the above-mentioned sink current value becomes large, so this switching requires Electronic switches such as transistors can be used, and a highly reliable circuit can be achieved with a simple configuration.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional vertical deflection circuit;
3 and 3 are waveform diagrams for explaining the operation of this conventional circuit, and FIG. 4 is a circuit diagram showing an embodiment of the present invention. In the figure, (2) is the first transistor, (3) is the power supply, (4) is the second transistor, (5) is the constant voltage source,
(6n is the first resistor, (7) is the capacitor, 0υ is the second
The resistor 2) is the third transistor. In addition, the same reference numerals in the figures indicate the same or equivalent parts. 0 Agent Makoto Kuzuno (1 other person) Figure 1 Figure 2 Figure 3 Figure 4

Claims (2)

[Claims] (1) A charging circuit that charges the capacitor to a predetermined voltage by conducting during the supply period of a vertical synchronization signal or a pulse synchronized thereto, and a current sinking circuit that always sucks a predetermined current from the capacitor. , in order to obtain a sawtooth waveform voltage at the end, when the frequency of the vertical synchronizer No. 4 is high, the current value of the current sinking circuit is switched to increase, and the amplitude of the sawtooth waveform voltage is increased. Vertical deflection circuit 0 characterized in that the deflection is substantially constant. (2) The charging circuit uses a first transistor that conducts when the base receives a vertical synchronization signal or a pulse synchronized with this, and a constant voltage is applied to the base of the current sink circuit, the collector is connected to the capacitor, and the emitter is connected to the capacitor. A second resistor is connected in parallel to the first resistor using a second transistor grounded through the first resistor, and a third transistor is controlled to be conductive when the frequency of the vertical synchronization signal is high. 2. The vertical deflection circuit according to claim 1, further comprising a transistor.