JPS58215846A - Data slice circuit - Google Patents

Abstract

PURPOSE:To fetch data effectively, by latching the data sliced by a data fetching clock after the data is sliced at plural slice levels, and using the optimum slice data properly in following to the data change. CONSTITUTION:A pseudo video signal from a VTR applied to an input terminal T1 is amplified to a suitable level at an amplifier 1, clamped 2 and the DC 1 level is made stable. An output of the circuit 2 is applied to comparators 3A, 3B respectively, where each signal is compared with a slice level set with variable resistors VR1, VR2 for slice setting for extracting the digital signal portion only. In this case, the signal is sliced at the optimum level at the comparator 3A when the data changes from 1 to 0. On the other hand, the data is sliced at the optimum level when the data changes from 0 to 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data slicing circuit suitable for use in digital information processing systems, particularly in data communication and digital signal recording and reproducing devices.

Although PCM tape recorders are known in the field of digital audio, a PCM tape recorder that uses a general household VTR as a recording medium, that is, a VTR with recording and playback strings, will be explained here as an example. As mentioned above, in a VTR that uses V'['R for the recording and reproducing thread, the signals of two channels of H are recorded alternately on one diagonal trunk by time division multiplexing. Ru. To this end, the waveform of the PCM signal includes horizontal and vertical synchronization signals, is converted into a signal format similar to a standard television signal, and is recorded on a magnetic tape. Hereinafter, in this specification, the PCM signal converted into a signal form conforming to a standard television signal as described above will be referred to as a pseudo video signal.

First of all, regarding the form of the above pseudo video signal,
This will be explained using the NTSC system as an example.

The above signal format is similar to a standard television signal, and is 1 field (262, 5H).
It includes 245H for carrying a data block and 1H for carrying a control signal block. One data block consists of 6 sampled signal words (6 words for the L channel signal, 6 words for the R channel signal,
There are 6 channel signals (each word is arranged alternately). It consists of 9 words (1 each for error correction words P and Q, and 1σ for error detection word (CRC)), and these are arranged between V of 1H. The control signal block is placed at the beginning of the data section of each field, and includes a start signal word, a content identification signal word, an address signal word, a control signal word, and an error detection word (CR (j 1 each).
These words are arranged in an interval of 1 f-(.The format and arrangement of each horizontal and vertical synchronizing signal are 7, which is the same as that of a standard television signal.

FIG. 1 shows the arrangement and structure of the above-mentioned pseudo video signal within 1H. In the diagram, H is a horizontal synchronization signal, A is a data synchronization signal, B is a data block, and C is a data block.
is the white reference signal. The above 13 data blocks are
Sampling signal word (Ll +R1, L2.■12.L3
．． R3), error correction words (P, Q), and error detection words (CRC), and the waveform of each word is an NRZ signal waveform. As shown in FIG. 1, a data synchronization signal is added to the beginning of each block signal, a white reference signal is added to the end, and the above-mentioned words are added between these signals.
It is arranged within the horizontal synchronization IZ. In addition, in FIG. 1, only the arrangement and structure within the IH interval are shown, but the arrangement and structure within each field (-7) are shown.

An equalization pulse and a vertical synchronization signal are placed at the beginning of each field, and IH with a control signal block placed on the 10th H in odd-numbered fields and 10.5H on even-numbered fields, followed by 245H with data blocks placed in order, The remaining H is configured to be a blank section.

A conventional example of a PCM tape recorder that handles a pseudo video signal having the above-mentioned configuration will now be described. Second
The figure shows a data punching circuit in a conventional PCM precoder. In the figure, TI is an input terminal, to which the above-mentioned pseudo video signal from UVi"R is supplied. 1 is an amplifier for amplifying the above input signal to an appropriate level, and 2 is the above-mentioned amplifier. A clamp circuit is used to obtain direct current stability for the input signal, 3 is a comparator, and 4 is a D Norilag flop.The VRd comparator 6 is used to set the slice level of the input signal. volume for,′
r2 is a clock supply terminal that supplies a clock for data punching to the clock terminal (CK) of the D clip-flop 4;
T3 u Output terminal of the above-mentioned D flip-flop 4 (this is a digital data output terminal from which the digital data output is taken out from Q).

": In the circuit configured as shown below, the first
A pseudo video signal as shown in the figure is input to the input terminal '1'1
supplied to Since the input signal from the input terminal T1 is about 1 V, it is amplified by the amplifier 1 at an appropriate level (about 3 to 4 VP).

Since the output signal of the amplifier 1 described above has an unstable DC level, it is supplied to a clamp circuit 2, and the clamp circuit 2 obtains DC stability. For example, in the circuit shown in FIG.
The level Lc shown in the figure or the Wachibe testal level is O.
It is fixed (clamped) at v to obtain direct current stability. The signal passed through the clamp circuit 2 described above is supplied to a comparator 6.

The coil parator 6 converts the signal supplied from the clamp circuit 2 to a slice level set by a slice level setting volume VR (level Ls shown in FIG. 1).
), only the digital signal part is extracted from its output. The above-described output from the comparator 6 is supplied to the data input terminal (2) of the D flip-flop 4, and in the Norilag flop 4, the original signal is synchronized with the data punching clock supplied to the clock supply terminal 'r2. output terminal 'r
3 as a digital data output.

In the example of the conventional PCM tape recorder mentioned above,
Since the slice level is fixed to one voltage with respect to the original signal, if the amplitude of the above original signal fluctuates for some reason, the optimum voltage range for the slice level is narrow and the accurate The disadvantage is that the data cannot be retrieved.

Well, VTR for general home use as a recording medium for PCM signals.
When using , it is difficult to obtain an ideal reproduced signal due to the influence of frequency characteristics and phase characteristics. Second, the optimal slice level is different for a waveform in which data changes from 1 to 0 and a waveform in which data changes from 0 to 61, but in the conventional method described above, there is only one slice level. Therefore, a level that provides a good compromise between the two is set as the optimum slice level.

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional technology, and it is possible to set a plurality of slice levels and use the optimum data that follows changes in the heel control. It is an object of the present invention to provide a data slicing circuit that enables the extraction of data.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 6 shows an example in which the present invention is implemented in a data punching circuit of a PCM tape recorder. Note that the same parts as in FIG. 2 are given the same reference numerals, and detailed explanation thereof will be omitted. In the figure, 1 is an amplifier, 2 is a clamp circuit, 3A, 31 (are first and second comparators, respectively, 4A, 4B,
4C is the 1st. 2nd and 6th D-flip clocks, 5 is a decision logic circuit, and 6 is an inverter. VR
r is the volume for setting the first slice level when the data changes from 1 to 0, and V R2 sets the slice level when the data changes from 0 to 1. This is a volume for setting the second slice level. A human terminal, T2, to which the aforementioned pseudo video signal from T+ld'V'l'R is supplied.
1 is a clock supply terminal to which a synchronous clock for data punching with a duty of -50% is supplied, and 1 and 3 are output terminals from which digital data output is taken out. The above amplifier 1. The signal (d) passed through the clamp circuit 2 is supplied to the first comparator 3A and the second comparator 6B, respectively.The output of the first comparator 6A is the data input terminal of the first D flip-flop 4A. ■), the output of the second comparator 6B is the second D flip
They are respectively supplied to the data input terminals υ) of the flop 4B.

The outputs of the first and second flip-flops 4A and 4B are supplied to a decision logic circuit 5, which determines the output according to the decision logic table below. The output of the decision logic circuit 5 is supplied to the data input terminal (D) of the third D flip-flop 4C.
The output of the flop 4C is output as data to the digital data output terminal T3 and is also passed to the judgment logic circuit 5. The synchronous clock for data punching is supplied to the clock terminals (CK) of the D flip clocks 4A and 4B, and at the same time, the clock whose phase is opposite to the synchronous clock for data punching by the inverter 6 is supplied to the clock terminal (CK) of the D flip frog 4C. CK).

In the circuit shown in FIG. 5, the pseudo video signal as described above from the VTR supplied to the input terminal T+ is amplified to an appropriate level in the amplifier 1 and then supplied to the clamp circuit 2. In the circuit 2, the pedestal level (see LC in FIG. 1) is clamped, and the DC level is stabilized. The signal that has passed through the clamp circuit 2 is supplied to the first comparator 3A and the second comparator 6B, respectively. 1st and 2nd above
In the comparators 6 and 6B, a comparison is made with the slice level set by the slice level setting volume VR+r VR2, and only the digital signal portion is extracted. At this time, in the first comparator 6A, when the data changes from 1 to O, it is sliced at the optimal level. In fact, in the second comparator 6B, when the data changes from 0 to 1, it is sliced at the optimal level.

Next, for the above optimal slice level, 51 yen 1
This will be explained in more detail with reference to . In the 51st shi 1 (
1) d ideal transmission waveform, (2) actual transmission waveform, (
3) is the synchronization clock for data punching, (4) is the slice data at the level Lo of the ideal transmission waveform shown in (1), and (5) is the slice data at the level L of the actual transmission waveform shown in (2). The slice data (6) is the same (as set in the conventional example) at the turning level L2, and the data to be punched out is also punched out at a position offset from the center. (7) also shows slice data at level L3.

Considering the case of slicing the actual transmission waveform shown in (2) of FIG. 5, the optimum slicing level for changing from 1 to 0 is level L1. The reason for this is as follows. In an actual transmission system, when the data changes from 1 → 0 → 1 due to the influence of frequency tracing characteristics, etc., the level cannot be completely lowered in the O part, so the upper part of the transmission waveform is This is because the position between the two points becomes the optimal slice point. For the same reason as above, 0→
The optimal slice level for a change of 1 is level L3. That is, the D clip frogs 4A and 4B
In selecting the data latched in , the condition for level selection is whether the immediately preceding data is 1 or 0. The data selection conditions are determined by the decision logic table described above. In the judgment logic circuit 5, the outputs of the D7'J soge flops 4A and 4B are 0.0 or 1.1.
The table below determines that the child is 0 or 1 regardless of the previous data.

However, when the outputs of 1) 7 Rig/70 Tub 4A and 4B are 0 and 1, the output of the judgment logic circuit 5 is set to 0 depending on whether the data in front of it is 1 or 0, as shown in FIG. It is decided whether to set it to 1. This is because the data change from 1 to 0 to 1 does not fully drop to 0, as mentioned in Section 2, so the D clip
The output of the frog 4A is determined to be 0°, and the output of the frog 4B is determined to be 1. However, even when the data changes from 0 → 1 → 0, 1 does not rise completely, so the output of the D clip flop 4A → 0. Same 4
The same determination as B→1 is made. Therefore, the output of the D-clip flop 4C that stores the previous data (this is latched by a clock with the opposite phase of the data punching synchronization clock applied to the clock supply terminal T2, so the decision logic circuit 5 is making a logic decision) The previous data is retained.) is used to make the determination.

FIG. 4 shows an embodiment of the m1 decision logic logic circuit 5, which is similar to the decision logic table described above. In Figure 4, 5A is an inverter, 5]315C and 5D are each N
A N 1) Judgment logic circuit 5 for elements with gate size or higher
Configure. Now, l] flip-flop 4A, 4
When the outputs of f3 are both 0, the output of NAND gate 513 is 1, and the output of NAND gate 5C is 1.
] It is 1 regardless of the output of the flip flop 4C. Therefore, the output of 5D (NAND game) is fixed as O. Similarly, when the outputs of D flip frog 4A14B are both 1, the output of NAND gate 5B is 0,
(NAND game) Regardless of the output of 5C, the output of NAND games 1-5D is determined to be 1.

The problem here is D flip frog 4A,
This is a case where the output of 4B is 0 or 1. In this case, NAND
The output of gate 5B is determined to be 1, but the output of NAND gate 5C
The output of is determined by the sixth input, which is supplied with the previous data, the output Q which is the inverse of the output Q of the D flip-flop 4C. Now, if the output of D flip-flop 4C is 1, the 6th input of NAND game) 5C is 0.
Therefore, the output of this NAND gate 5C becomes 1. Therefore, the output of NAND gate 5D becomes 0. Next, if the output of D clip flop 4C is O, then NA
The third input of the ND gate 5C becomes 1, and the output of the NAND gate 5C becomes 0. Therefore, NANI) game)
The output of 5D is 1.

Furthermore, the above-mentioned data punching synchronous clock will be explained. When the original signal is sliced, all pulse-like noise is also output. Therefore, by preparing in advance a clock that has a phase in the time axis direction that is the center of the waveform of the original signal, and latching the center of the slice data, it is synchronized with the above clock (7) to obtain noise-free data. It is possible to do this.

In 4C, the above-mentioned clock supplied from the clock supply terminal T2 is used as a reverse phase clock via the inverter 6. This eliminates the output of noise during switching due to logic judgment.

One embodiment of the present invention described above uses a VTR that plays for a particularly long time (6 hours) as a recording medium for PCM signals.
It has been designed so that stable operation can be expected even in the case of 7.
This can also improve compatibility between different models. In the example described above, the case where the slice level of the data is two is explained as an example, but it is possible to set the slice level of the data by 3 or 4, and to set and calculate multiple selection conditions. This enables more precise data slicing.

Furthermore, the present invention is not limited to application to the above-mentioned VTR,
It can also be used in the field of data communication, and by using it for data transmission reception, whether wired or wireless, it can cover the narrow frequency characteristics of the transmission path.

As described above, the present invention is arranged at the receiving end of a data transmission system in a digital communication circuit and has the function of extracting a digital signal from data containing the digital signal, in which a plurality of comparators 3A are used to extract the digital signal. .

Volume VR+ for setting 6B etc. and multiple slice levels
After setting multiple slice levels using +VR2, etc., and slicing data at the multiple slice levels, the sliced data is latched using the data extraction clock in D flip-flops 4A, 4B, etc., and changes in the data are processed. By using the optimal slice data for tracking/hi, it is possible to extract more accurate data, and as a result, the coverage range of the slice level for the original signal is widened, and the above-mentioned level fluctuations of the original signal can be compensated for. It is also possible to expect stable operation.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the arrangement and structure within 1H of a pseudo video signal in which a PCM signal is converted into a signal form conforming to a standard television signal; Fig. 2 shows a data punching circuit in a conventional PCM tape recorder; 6 and 4 are diagrams showing an example in which the present invention is implemented in a data punching circuit of a PCM tag recorder, and FIG. 5 is a waveform diagram for explaining the optimum slice level. FIG. 6 is a waveform diagram for explaining the determination logic. 3A, 3B: Comparator, 4/4B: D flip/frog, VRtr VH2 slice level setting volume 1st section 2nd figure 3rd figure 5th figure 6th figure 5 Beast: pO5o hydraulic l

Claims (1)

[Claims] A digital communication circuit that is placed at the receiving end of a data transmission system and has a function of extracting a digital signal from data containing the digital signal, sets a plurality of slice levels when extracting the digital signal, and A data slicing circuit characterized in that, after slicing data at a plurality of slicing levels, the sliced data is latched by a data extraction Ronx, and the optimum sliced data that follows changes in data is properly used. .