JPS58214952A - Information processing system - Google Patents

Abstract

PURPOSE:To recover automatically a fault of a main service processor (SVP) without performing a manual operation, by providing an automatic monitor and control function between SVPs. CONSTITUTION:A main SVP10 stops immediately the transmission of a normal signal when the SVP10 has a fault. Then an SVP20 which is newly switched starts immediately to transmit the normal signal to a bus. An SVP30 works as a slave SVP. The SVP20 starts a scan through its own scanning part is order to retrieve a faulty SVP. Then the SVP20 transmits successively a system resetting command, an initial program load command and a diagnosis program starting command to the SVP10 through a bus 40 in order to start the diagnosis of the SVP10. Receiving these commands, the SVP10 resets a system and then performs an initial program loading action to a diagnosis program stored in a floppy disk. Then the diagnosis program is started with a starting command.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to an information processing system, and in particular, to information processing systems that include a plurality of processing devices, each of which is connected to a service processor, and that monitors and controls the service processor. Regarding the information processing method that is operated and managed based on the information processing method.

[Description of prior art]

2. Description of the Related Art Conventionally, among information processing apparatuses, multi-systems, etc., which are configured with a plurality of processing apparatuses, have been known in order to improve reliability and performance of the apparatus. One service processor (hereinafter abbreviated as rsvpJ) is usually connected to each processing device, and controls the power supply, configuration, and initial state settings of the computer system, as well as controlling the startup, stopping, etc. of the processing device. It is an essential device for computer systems. When the above-mentioned multisystem or the like is used, this SVF becomes an element composed of a plurality of units in the system. In this case, the function of SVP is to use multiple SVPs.
If you perform system configuration control and power supply control on a system, the control method and management method will be very complicated, so
One of the VPs is used as the main SVP to manage the system as a whole. In other words, conventionally,
Multiple SVPs are divided into a main SVP and a slave EIVP, and one main SVP takes charge of system operation management, and the other slave SVPs
serves as a backup in case of failure.

However, in the past, there was no direct connection relationship between the main 8VP and the slave SVP, and when a failure occurred in the main SVP, the main SVP could not be automatically switched, and operator or maintenance personnel had to intervene. There were some drawbacks. In addition, an SVP in which a failure has occurred is disconnected from the processing device, and the cause of the failure is determined by an operator or maintenance person. For this reason, there is a drawback that manual operations by an operator or the like are required, and a large amount of time is required for failure recovery.

[Purpose of the invention]

The present invention provides an information processing system that automatically monitors and controls between SVPs and automatically recovers from the failure without manual operation when a failure occurs in the main SVP. With the goal.

[Key points of the invention]

The present invention has a plurality of processing devices, a service processor is connected to each of the plurality of processing devices, one of the plurality of service processors is used as a main service processor, and the main service processor monitors and controls the service processor. In an information processing system in which a service processor is in charge of operation management, and multiple other service processors are reserved, a bus is provided between the multiple service processors, and when a failure occurs in the main service processor, the other multiple service processors are provided with backup services. The processor detects a failure, and any one service processor among the plurality of spare service processors switches to the main service processor, and the switched main service processor identifies all the faulty service processors;
The main service processor in parentheses is characterized in that it provides various instruction signals for diagnosing a faulty service processor via the bus.

[Explanation based on examples]

Next, embodiments of the present invention will be explained in detail with reference to the drawings.
I will clarify.

FIG. 1 is a circuit diagram of an information processing apparatus according to an embodiment of the present invention. 1.2.3 is a central processing unit (hereinafter abbreviated as rOPUJ). 1a, 2a, and 3a are main SVP number storage units in which the BVP number designated as the main SVP is stored. The SVP number is used to select a route when the CPU needs to issue a command related to operation management (for example, power control) to the main SVP. 4.5.6 is a peripheral control device (hereinafter abbreviated as rPcUJ), and s V P 10.2
0.30, and also controls other devices such as line printers, magnetic tapes, etc. Each of these svp i,o, 20.30 has a console function that serves as a man-machine interface and a function that manages the operation and management of the entire system.

The aptrl shown here, PC! U4, 1 in SVPIO
It consists of two processing units. In the example shown in FIG. 1, a multi-system is configured in which CPU 1.2.3 and POU 4.5.6 of three processing units are interconnected.

A bus 40 connects the sv'pio and 20.30, and is used to transfer control information and data.

If there are two or more EIVPs, one EIVP is arbitrarily selected as the main SVP during multi-system construction using keyboard input or the like. In this example, 5vp10 is the main EVP
Assume that As a result, the main svp number is connected to each connection k via the higher-level POU4 to each higher-level 0FU1.2.3.
main svp number storage units 1a, 2a in each CPU
, 3a.

From now on, commands related to system operation will be sent to either CPU.
Route management is performed such that the main SVP number storage section is all referenced from the main SVP number storage section and a command is issued to the main 5vp10.

Figure 2 is a detailed circuit diagram of this svp.
Both IO120 and IO30 have the same configuration.

Here, s v P 10 will be explained as a representative example. 1
01 is an 8V P 10 floppy disk.

This 70-tube disk 101 stores a diagnostic program, etc., which will be described later. 102 is an interface with the host device POU4, 103 is a processor section, 104 is a memory section, 105 is a CRT display, 106 is a serial printer, and 107 is an svp newly added in the present invention. This is an interface control unit. On this day, the VP interface control unit 107 has a main SVP selection unit 108 which has a mechanism for newly designating any one of multiple slave S'VPOs as the main EIVP when a failure occurs in the main SVPO, and a new In order to ensure that the SVP designated as the main SVP is operating normally, a normal signal generation unit 109 sends out a signal to the bus periodically, and the slave SVPs other than the main SVP detect the above-mentioned normal signal. The normal signal detection unit 110 generates an abnormal signal when the normal signal is interrupted, and the SVP that has newly become the main SVP performs a scanning operation on all 8VPs to recognize the faulty SVP and detects each 5VPCV. The scanning unit 111 that collects and decodes status data and this main EIVP give system reset instructions, initial program load instructions, diagnostic program startup instructions, etc. to the faulty SVP, and from the faulty svp#'i main BVP A control unit 112 that resets the system, loads a diagnostic program from a floppy disk, etc. in response to instructions from a floppy disk, and a hardware interface unit 113 with the bus 40. : Consists of:

With such a configuration, the operation of the apparatus of this embodiment will be explained based on the SVP processing flowchart shown in FIG. S V P
10 acts as the main SVP, 5VP20, S V
When P 30 is operating as a slave EIVP, the master S V P 10 periodically sends normal signals to S V P 20 and S V P 30 via bus 40 .

EIVP20.5VP30 always detects and monitors this normal signal. Now, if a failure occurs in the main SVP 10, the main SVP 10 immediately stops transmitting the normal signal. As a result, s V P 20, SVP
30 detects that a normal signal cannot be detected and the main 5vp10 is in an abnormal state.

s V P 20, S V P 30, the main SV immediately
In order to switch P, one of the multiple SVPs is arbitrarily designated as a new main SVP using a certain mechanism. This method includes, for example, implementing timers with different set times and setting the EVP whose timer expires early as the main SVP. Assuming that S VP 20 is newly switched as the main SVP by the above mechanism, S VP
20 immediately begins sending normal signals onto the bus. S V
By detecting P30H normal signal, 8V
The main BVP designation operation that was being performed in synchronization with P20 is immediately stopped, and thereafter the operation returns to the slave SVP. The EI V P 20 notifies the higher-level 0PU1.2.3 of the main SVP number change through the higher-level pt and a5, and rewrites the contents of the main FIVP number storage units 1a, 2a, and 3a, respectively.

This means that s v p 20 is designated as the main SVP.

Next, the SVP 20, which became the main SVP, immediately detects the faulty SVP in order to diagnose the faulty SVP.
In order to search for a VP, a scanning operation is started by its own scanning unit. In this scanning operation, the main SVP 20 polls all other SVPs, collects status data in each SVP each time, and checks the contents of the data to determine whether a failure has occurred. It is for making judgments.

As a result, it is recognized as 5vPhsvP10 where a failure has occurred. Next, the main 8V P 20 issues a system reset command and an initial program load (hereinafter referred to as [engineering PLJ
It is abbreviated as

) command, diagnostic program start command, and then SVP 1
Send to 0. The SVP 10 receives the above command, puts the system into a reset state, performs an engineering PL operation on the diagnostic program stored on the floppy disk, and runs the diagnostic program in response to a startup command. The diagnostic program performs an operation to detect a faulty location, and the results are output to a CRT display, serial printer, or the like.

Note that the number of processing devices Vi shown in the above example is not limited to six, and the number may be increased or decreased.

〔Effect of the invention〕

As described above, according to the present invention, by providing a bus between SVPs, the slave SVP can monitor the status of the master SVP, and when a failure occurs, the master SVP can be automatically and quickly switched. has been performed, and the faulty svp is diagnosed.
It is economical, does not require any manpower, and has an excellent effect in improving the reliability of the system.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an information processing apparatus according to an embodiment of the present invention. FIG. 2 is a detailed circuit diagram of the service processor. FIG. 3 is a processing flowchart of the apparatus according to the embodiment of the present invention. 1.2.3...Central processing unit (CPU), 1a,
2a, 3a... Main SVP number storage section, 4.5.6...
・Peripheral control i[(POU), 10.20.30...
Service processor (8VP), 40... bus, 10
1... Floppy disk, 102... POU interface, 103... Processor section, 104...
Memory section, 105... CRT display, 106.
...Serial printer, 107...Sunday vP interface control section, 108...Saturday and Sunday vP setting section, 109...
- Normal signal generation section, 110... Normal signal detection section, 11
1... Scanning section, 112... Control section, 113... Interface section. Patent Applicant NEC Corporation 1, Attorney: Nao Takashi Ide; Figure 1 Figure 2

Claims (1)

[Claims] (1) Comprising a plurality of processing devices and a plurality of service processors connected to each of the plurality of processing devices, one of the plurality of service processors is designated as the main service processor, and the remaining services are provided. In an information processing method in which a processor is designated as a slave service processor and the plurality of processing units described above are operated and managed by the main service processor, a bus is connected between the plurality of service processors and each The service processor includes a normal signal generator that periodically sends normal signals to other service processors to ensure normal operation when designated as the main service processor, and a normal signal generator that periodically sends normal signals to other service processors when designated as the main service processor. a normal signal detection section that generates an abnormal signal when the normal signal from the main service processor is cut off quickly, and an abnormal signal generated from this normal signal detection section that detects that a failure has occurred in the main service processor. A main service processor setting section that detects and designates any one slave service processor from among the plurality of slave service processors as the main service processor; An information processing method characterized by being fully equipped with a control unit that diagnoses, repairs, and resets the main service processor that has occurred.