JPS58213594A - Processing device of chrominance signal - Google Patents

Abstract

PURPOSE:To give many functions to a flip-flop circuit and to increase the number of elements which can be used commonly for processing signals of both PAL and NTSC systems as many as possible to simplify the circuit and to reduce the cost, by setting the voltage level of the output of the flip-flop circuit at a ternary level. CONSTITUTION:The inverting and noninverting timings of a flip-flop circuit 86 is determined by a gate pulse outputted from a waveform circuit 80, and the circuit 86 can be inverted or noninverted at every horizontal period. Moreover, the flip-flop circuit 86 is set to the operation stopping condition or operating condition by a switching signal from a system switching circuit 79. When TV signals of the NTSC system are processed, the operation of the flip-flop circuit 86 is stopped, and when TV signals of the PAL system are processed, the operation of the circuit 86 is started.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color signal processing device used in a color television receiver or the like, which is capable of receiving television signals of different formats with a single device.

[Technical background of the invention]

There are three color television signal systems currently used in the world: NTSC, PAL, and SECAM. Each of these systems has been uniquely adopted by each tube or region, but with the advancement of color television broadcasting using space satellites and the spread of video tape recorders, signals of these different systems have changed. There is an increasing demand for so-called multi-system color television receivers that can receive the following images with a single color television receiver.

In order to reproduce and process the signals of each system, each television signal processing circuit suitable for each system is independently provided. For this reason, conventional multi-system color television receivers
As the number of component parts increases, there are problems such as an increase in price, an increase in power consumption, and a decrease in reliability.

In order to solve the above problems, multi-system color television receivers have been developed that reduce the number of parts by increasing the number of circuits that can be used in common with each system when the signal systems are similar. . Multi-system color television with
) Yon receiver is capable of receiving images of the NTSC system and the PAL system.

Therefore, the unique parts of NTSC and PAL color television receivers will be explained with reference to FIGS. 1 and 2.

FIG. 1 shows a color signal processing circuit of an NTSC color television receiver. 11 is a chroma signal input terminal, 12
is a band amplification circuit. It includes 12 band amplification circuits, an automatic gain control circuit (ACC), and a burst signal circuit.The automatic gain control circuit detects level fluctuations in the input signal and automatically controls the output so that it is always at a constant level. The main scale circuit is a circuit for separating the color signal component and the burst signal from the input signal. The chroma signal separated by the band amplification circuit 12 is input to the color control circuit 14 via the transmission line 13.
Amplified according to user adjustment. The output chroma signal from the color control circuit I4 is sent to the (B-Y) demodulator 1.
5, (11-Y) is input to the demodulator 17. On the other hand, the Goust signal separated by the band amplification circuit 12 is transmitted to the transmission line 1.
8 and is input to the hue control circuit 19. The hue control circuit 19 has a function of correcting, on the receiver side, a hue error caused by the influence of the television signal on the transmission path, and the amount of correction is adjusted by the user. The burst signal whose phase has been adjusted in the hue control circuit 19 is transmitted to the transmission line 2.
0 and is input to the color synchronization circuit 21. The color synchronization circuit 21 includes a demodulation reference subcarrier generator for generating subcarriers necessary for demodulating color signals, and a killer detector for identifying whether the broadcast is in color or black and white. The output of the killer detector is supplied to the color control circuit 14 or the demodulator, and the circuit function can be stopped so as not to generate color noise during monochrome broadcasting.

The reference subcarrier generator has an automatic phase control function that accurately follows the phase of the input burst signal, generates a subcarrier for demodulation based on the phase of the burst signal, and transmits the subcarrier to the transmission line 22.
．． 23 to each (B-Y) demodulator Js (R-Y) demodulator 17. The demodulators 15 and 17 each have positive and negative outputs, and depending on the polarity of the picture tube drive circuit that drives the color cathode ray tube for image display in the subsequent stage, for example, output the positive polarity to each output terminal 27 and 29. At the same time, the negative polarity signal is sent to the matrix (G-Y) via transmission lines 25 and 26.
(G-Y) to the demodulator 16 and to the G-Y output terminal 28.
get the output.

FIG. 2 shows a color signal processing circuit of a PAL color television receiver. Parts having the same functions as the circuit shown in FIG. 1 will be described with the same reference numerals. The chroma signal output from the color control circuit 14 is input to the IH delay device 3 and also input to the PAL matrix circuit 33 via the attenuator 32. The output of the IH delay device 31 is also added to the IJx circuit 33. PAL matrix circuit 3
3, matrix processing is performed on the IH (one horizontal period) delayed signal of the chroma signal and the non-delayed signal, separating it into a (B-Y) component and a (R-Y) component. The signals are input to the (B-Y) demodulator Js and the (R-Y) demodulator 17, respectively. On the other hand, in the PAL system, the modulation axis of the (RY) component is inverted by 180° every horizontal period and transmitted. This is a feature of the PAL system, and when the PAL matrix circuit 33 performs vector synthesis of the signal one horizontal period before and the direct signal, the influence of subcarrier phase distortion on the demodulated signal is reduced. Since the PAL system is less susceptible to phase distortion in the transmission path, a hue control circuit is not required, and the burst signal separated by the band amplifier circuit 12 is directly input to the color synchronization circuit 21 to generate a reference subcarrier. used for purposes. Color synchronization circuit 2
The subcarrier for (B-Y) demodulation obtained in step 1 is (B-Y
) is input to the demodulator 15. The subcarrier for (RY) demodulation is input to the horizontal retrace switch circuit 34, which is driven by the horizontal retrace pulse and obtains an inverted operation every horizontal period, and the phase is adjusted. The combined subcarriers are input to the (RY) demodulator 17. However, this inversion operation of the pulse switch circuit 34 is controlled by color killer detection output information (obtained from the killer detector in the color synchronization circuit) so that it is in positive phase with respect to the transmission signal. When receiving the PAL system, the cell switch circuit 34 has an internal 7-lip-flop circuit that is inverted or non-inverted by the horizontal retrace/elbow pulse, or when a color killer signal is generated, the inversion operation is so-called -1. It is stopped for one horizontal period by the ident signal, and (R
-Y) The phase of the subcarrier for demodulation is controlled so as to have a normal relationship with the transmission signal phase.

In the above-mentioned color signal processing circuit dedicated to the NTSC system and the PAL system, a shared circuit that allows common functions to be shared by both systems is configured as shown in FIG.

In FIG. 3, parts having the same functions as the circuits shown in FIGS. 1 and 2 will be described with the same reference numerals. In the case of this shared circuit, a switching circuit 35 and a system selection means 36 are further provided, and the output of the switching circuit 35 selects the PAL
Matrix circuit 33. The pulse switch circuit 342 is designed to switch the operation of the hue control circuit 19. During PAL reception, the control operation of the hue control circuit 19 is stopped and the band amplification circuit 1
The burst signal separated in 2 is sent directly to the color synchronization circuit 2.
1 will be introduced.

When receiving the NTSC system, the color control circuit 14
The chroma signal derived from pAr passes through part of the matrix circuit 39 to the matrix 1. /(B-Y) demodulator 75. (RY) is input to the demodulator 17. Still derived from color synchronization circuit 2 (R-Y)
The subcarrier for demodulation also passes through a part of the cell switch circuit 34 and undergoes no phase inversion/processing (RY) demodulator 17
is input.

As described above, according to the color signal processing circuit compatible with both PAL and NTSC systems, the signal processing form is switched depending on the system of the received signal. In the above explanation, the switching circuit 35 determines whether or not to perform matrix processing in the PAL matrix circuit 33 for chroma signals, and the pulse switch circuit 34 determines (R-
Y) It is determined whether or not to invert the demodulation axis by 180° every horizontal period. That is, in the above system, PA
The phase processing function in the color signal processing circuit is switched depending on the reception of the L system and the NTSC system.

Further, if we focus on the differences in signals between the PAL and NTSC systems, they are as shown in Table 1 below.

Table 1 As seen from the table above, (B-Y)/ (R-y)
When the demodulation amplitude ratio is calculated and the NTSC method is set to 1,
The amplitude ratio of demodulated components differs between the NTSC system and the PAL system. This is obtained by detecting the amplitude of the demodulated component when color signals of red, green, and evening reference colors are transmitted. The reason why the demodulation amplitude ratio differs between the PAL system and the NTSC system is that the reference white color (color temperature) on the transmitting side differs between the systems. Therefore, in a color signal processing circuit compatible with PAL and NTSC systems,
It is also necessary to change the circuit gain depending on the C method reception so that the demodulation amplitude ratio as shown in Table 1 above can be obtained.

Next, each component demodulation axis of the PAL system and the NTSC system will be explained. The (B-Y) component and the (R-Y) component are the (B-Y) demodulator 15 and the (R-Y) demodulator 17, respectively.
This (B-Y) demodulator 15, (R-4) input to
For the demodulator 17, the signal generated in the color synchronization circuit 21 (B
-Y) demodulation subcarrier and (RY) demodulation subcarrier are respectively input. When receiving the NTSC method, (B-Y
) Demodulation subcarrier, 1 between (RY) demodulation subcarriers
A phase difference of 0.05° is set and generated. Also, PAL
When receiving the system, (13-Y) demodulation subcarrier and (R-
A phase difference of 90° is set between the Y) demodulation subcarriers, and the (RY) demodulation subcarriers are inverted by 180° every horizontal period by the pile switch circuit 34. In this way, the demodulation axis of the (B-Y) and -(R-Y) components is determined by the subcarrier generated by the color synchronization circuit 2. On the other hand, for demodulation of the (G-Y) component, a (G-Y) demodulator 16 using an IJ wax path is used.

FIG. 4(a) shows a (B-Y) demodulator 15, a (G-Y) demodulator 16, and a (R-Y) demodulator 17. (B-y) In the demodulator 15, 42 is a phase detector using a double-balanced differential amplifier, and 41 is a constant current source. Phase detector 42
The (RY) demodulation subcarrier CWB and the chroma signal CRO are input to the subcarrier CWB for demodulation.

The output terminals 42a and 42b of this phase detector 42 have
The detection outputs having opposite polarities are separated to obtain a (B-Y) demodulated output, which is led out from one end of the (B-Y) demodulated output resistor 43 to the output terminal 27.

The other (B-Y) demodulated output is (a-y) demodulator 16
is input. The (RY) demodulator 17 also has the same configuration as the (B-y) demodulator 15, and includes a phase detector 46 and a constant current source 45. This phase detector 46 has (R
-Y) Demodulation subcarrier CwB and chroma signal CRO are input. An output terminal 46g of this phase detector 46,
46b has detection outputs with mutually opposite polarities, that is, (RY)
A demodulated output is obtained, and one (RY) demodulated output is led out from one end of the resistor 47 to the output terminal 29. The other (R-Y) demodulated output is input to the (G-Y) demodulator 16. (G'-, Y) The demodulator 16 has a resistor of 48°49 and a constant current source 50 between the power supply line and the reference ground potential line.
are connected in series, the (B-Y) demodulated output is input to the connection point of the resistor 4!3.49, and the (R-Y) demodulated output is input between the resistor 49 and the constant current source 50. . Then, the (G-y) demodulated output is sent to the output terminal 2 via the resistor 51.
8.

/G-Y) demodulation output is (B-Y) demodulation output and (R-
Y) Obtained by matrix processing with demodulated output.

This is because in television signal transmission, the ratio between the luminance Y signal representing brightness and each of the three primary colors R, GXB signals is determined, so (R-Y), (B-Y)
If the demodulated output is determined (G-Y), the demodulated output will be uniquely determined.

Now, in FIG. 4(a), if the demodulation conversion conductance of the phase detector 15.17 is tossed by q, l2gR, the demodulation output amplitude E of the output terminals 27, 29.2FI, IEllll
E, and DC voltage vB, vR, voke, input signal as ei, En-ei' 17 n "a's
-(1) VB = Vcc 2 'u・R4s
-(2) En-eVQn”47
-(3)VB:VCC-7■I
i5°R4,-(4)Eo-e,:・q,1-R48+
eZ-g8・(R48+R4,)・(5)1 ■O:vCC'41°R48-'Tl45°(R48+
R49)' so (R43+R47)
・-(6).

The above R43'R47' R4B "49" has a resistance of 43.47. (The value is 48, 49, '44.
45'I5o is the current value flowing through the constant current sources 41, 45.50. In the above circuit, each DC voltage V! l・
If the values of the constituent elements are selected so that vRlvc is equal, even if the PAL reception state is switched to the NTSC reception state, there will be no fluctuation in the DC level and the brightness on the picture tube surface will not change significantly.

Now, assuming that the above demodulator is of the PAL system, VB and VRlvc are set equal, and E, /ER = 18, Eo / ER so that the amplitude ratio of Table 1 is satisfied.
=0.6. As a result, the demodulated component vector is (B-Y)/(
R-Y)-1,,8,(G-Y)/(R-Y)=0
．． 6. The phase difference between the (RY) and (B-Y) axes is 90°, (
The phase difference between the a-y) and (B-Y) axes is demodulated at 240°. Next, when switching from the PAL reception state to the NTSC reception state, a vector of demodulated components as shown in FIG. 4(c) is obtained. Here, since the demodulator is set to suit the PAL system, (B-Y) /
The amplitude ratio of (RY) and the amplitude ratio of (G-Y)/(RY) are different from those in Table 1. Furthermore, due to the difference in the amplitude ratio, the phase of the '+(G-Y) axis deviates from the normal position (vector indicated by a broken line). Therefore, the phase of the (G-'Y) component is returned to the normal phase, and at the same time, (B-Y)/(R-Y
), (G-4)/(R-Y) also needs a means to change the amplitude ratio to the values shown in Table 1.

Note that (a-y>demodulated output is (B-Y) demodulated output and (R-
Y) What is obtained by 4 vector combination with the demodulated output is based on the color preview signal transmission method. In other words, there is a relationship between the luminance Y signal and the signals of the three primary colors R, G, and H: Y=0.30)1+O,'59G+0.11B, and Y and (R-Y) and (B-Y ), (G-Y) = -0,51(R-Y) -0,19(
The (GY) demodulated output can be obtained from the relationship (B-Y).

[Problems with background technology]

When designing a multi-system color television receiver as described in [7] above, in the color signal processing circuit, (R
-Y), (B-Y) (G-Y), PAL
, NTSC, and (B-Y)/(R-Y), (G-Y)/(R-
Many problems remain, such as setting the amplitude ratio of Y) to an appropriate value for each system.

A multi-system common color preview receiver is configured so that its internal signal processing format can be switched to suit each system. However, when switching the signal processing format, it is necessary to avoid large changes in the output signal level due to the switching. However, the more elements that can be used for processing signals of each type, the more the circuit will be simplified and the cost will be reduced.

[Purpose of the invention]

The invention focuses on the relationship between a flip-flop circuit whose operation mode is switched depending on the processing status of the PAL system and the NTSC system, and a phase switching means in a phase synthesis circuit controlled by the flip-flop circuit.
It is an object of the present invention to provide a color signal processing device which is convenient for processing signals of various methods by making the flip-flop circuit multi-functional by making it possible to set the voltage level of the second output to three levels. shall be.

[Summary of the invention]

In order to achieve the above object, the invention allows the phase inversion operation of the flip-flop circuit 86 during PAL signal processing, and uses its first and second outputs to switch the output phase of the phase synthesizer. However, if the high level and low level are used as the first and second voltage levels, in the stopped state during NTSC signal processing, the first and second outputs are set to a third voltage level that is lower. The third voltage level is sufficiently lower than the voltage applied to the phase synthesis circuit from the system switch circuit.

[Embodiments of the invention]

Embodiments of the invention will be described below with reference to the drawings.

FIG. 5 shows the overall configuration of the color signal processing circuit section in the Colorite L/Pinoyon receiver of the present invention. 61 is an input terminal for a chroma signal including a burst signal, and the chroma signal input thereto is input to a variable gain amplifier 62. The chroma signal subjected to gain control in the variable gain amplifier 62 is input to a first chroma signal separation circuit 63. The burst chroma signal separated by the burst chroma signal separation circuit 63 is transferred to the hue control circuit 8.
1 and the chroma signal is still input to the color control circuit 64. Furthermore, the burst signal separated by the burst chroma signal separation circuit 63 is input to an automatic color control ACC detection circuit 71, where the amplitude is detected. A DC voltage obtained by amplitude detecting the burst signal is applied to the gain control terminal of the variable gain amplifier 62. Therefore, the chroma signal output from variable gain amplifier 62 is always controlled to a stable level. In order to separate the burst signal in the burst chroma signal separation circuit 63, the gate/P pulse shaping circuit 7
Dart pulses from 2 are used.

This dart pulse is phase-synchronized with the burst signal period, and is output after, for example, a horizontal synchronizing signal is delayed and adjusted to a constant arm pulse width.

The chroma signal separated by the burst chroma signal separation circuit 63 is amplified by the color control circuit 64.

The gain of the color control circuit 64 is varied by adjusting the adjustment zerium 65 by the user. The chroma signal from the color control circuit 63 is sent to the IH delay device g66, which has a delay time of one horizontal period.
Via the coupling capacitor 67/Armator, Kume circuit 7
5 is added to the delay input line 751, and
The signal is applied via an attenuator 68 and a coupling capacitor 69 to a direct input line 76b of a normal matrix circuit r5.

The specific operation of the IJ wax passage 76 will be explained in detail in FIG. In this chroma signal circuit 75, when the system is processing a PAL television signal, the chroma signal IH
(The IH delayed chroma signal delayed by one horizontal period and the undelayed direct chroma signal are subjected to matrix processing.
Y) component and (RY) component are separated, and this component is
(RY) demodulator 16 and (RY) demodulator 7r, respectively.
is input. On the other hand, when the system is processing an NTSC television signal, the operation switch 14
is turned on, and the IHf' erase chroma signal on delay input line 75 is passed to ground. Therefore, only the direct chroma signal is input to the norm and task circuit 16. When the operation switch r4 is turned on, the pulse circuit 75 switches its internal signal path, and accordingly, the output state of the system switch circuit 19 is also switched. (The specific configuration of the system switch circuit 19 is explained in detail in Figure 6.)
When processing TSC system television signals,
A noise matrix circuit 75 separates the direct chroma signal into two transmission paths, which are input to a (B-Y) demodulator 76 and a (R-Y) demodulator rrK, respectively. No 4 matori! The waveform shaping circuit 80 outputs pulses synchronized with the horizontal synchronizing signal period.
Luz can also be added. J
When it is 1, the arm matrix circuit 75 outputs a chroma signal and interrupts. The waveform shaping circuit 80 generates a target signal using, for example, a flypack signal synchronized with a horizontal synchronizing signal. This r-to-root is the timing pass/L=su for the Furi, Pflo, 7' circuit 86, which will be described later, to obtain a phase inversion operation. It is also used.

The signal output from the Nosenru matrix circuit r5 is (
Demodulation processing is performed in a B-Y) demodulator 76, a (R-Y) demodulator 77, and a (G-Y) demodulator 78.

This (B-Y) demodulator 76, (R-y) demodulator 77, (
The specific configuration and operation of the GY) demodulator 78 will be described in detail in FIG.

On the other hand, the burst signal whose phase has been adjusted in the hue control circuit 81 is transmitted to a color killer detection circuit 83 (hereinafter referred to as a killer detection circuit) and an automatic phase control detection circuit 84.
(hereinafter referred to as the Arc detection circuit). When the hue control circuit 81 is to be adjusted, the adjustment circuit 82 is operated by the user. In the killer detection circuit 83, phase detection is performed between the Norst signal and the subcarrier for killer detection, and a voltage corresponding to the phase difference is output as a killer detection voltage. APC detection circuit 8
In step 4, phase detection is performed between the Norst signal and the automatic phase control subcarrier, and a voltage corresponding to the phase difference is obtained as the oscillation frequency control voltage. Killer detection circuit 8
3. The APC detection circuit 84 performs a detection operation in synchronization with the burst signal, and its timing is determined by the dart pulse from the spinning dart norse shaping circuit 72.

The voltage from the killer detection circuit 83 is input to the ident and killer circuit 85. The identification and killer circuit 86 is detailed in FIGS. 9 and 10. The ident and killer circuit 85 controls on/off of chroma signal transmission of the color control circuit 64 and inversion/non-inversion of the flip-flop circuit 86 according to the level of the killer voltage. Furthermore, the ident and killer circuit 8 with
The chroma signal transmission path of the chroma matrix circuit 75 can also be controlled on/off by its output. Ident and killer time #SS can distinguish between color broadcast reception state and black and white broadcast reception state according to the killer voltage signal.Furthermore, when receiving a PAL television signal, flip-flop.

It is possible to determine whether the inverting or non-inverting operation of the switching circuit 86 is in the correct phase or in the incorrect phase. The inversion/non-inversion timing of the flip-flop circuit 86 is as follows:
It is determined by the dart pulse output from the waveform shaping circuit 80, and can be inverted or non-inverted every horizontal period. Furthermore, the flip-flop circuit 86 is set to an inactive state or an active state by a switching signal from the system switch circuit 79. When an NTSC television signal is being processed, the operation of the flip-flop circuit 86 is stopped, and when a PAL television signal is being processed, the operation of the flip-flop circuit 86 is stopped. is started.

The reference oscillation output from the voltage controlled oscillator 87 is introduced into the phase synthesizer 88, and the phase synthesizer 88 outputs, for example, four subcarriers depending on the purpose of use. This phase synthesizer 88 includes a (B-Y) demodulation subcarrier to be added to the (B-Y) demodulator 76 and a (R-Y) demodulation subcarrier to be added to the (R-Y) demodulator 77. carrier wave,
(G-Y) A correction subcarrier to be added to the demodulator 78 and a killer detection subcarrier to be added to the killer detection circuit 83 are generated. The target correction subcarrier is used when an NTSC television signal is being processed.
Y) Utilized in demodulator 78. Phase synthesizer 88
The operating mode is switched by the output of the system switch circuit 79, and is switched between PAL mode reception and NTSC mode.
At the time of system reception, the phase state of the (RY) demodulation subcarrier is switched, and the (RY) demodulation carrier is
The phase is inverted every horizontal period by the output of the FRI, PFLO, and PF circuits 86. The specific configuration and operation of the phase synthesized wave fll g s will be described in detail in FIG. is input, and is used to generate various subcarriers. Since the voltage controlled oscillator 87 has its oscillation frequency controlled by the detection output from the APC detection circuit 84, it is controlled so as to always obtain an oscillation output phase-synchronized with the burst signal.

(1) Explanation regarding the nominal matrix circuit 76. Fig. 6 shows the nominal matrix circuit 75', system switch
The configuration of the terminal circuit 79, operation switch, and cheerer 4 is specifically shown. The IJ wax path 76 functions as a matrix circuit that performs vector addition and subtraction between the direct chroma signal and the delayed chroma signal when receiving the PAL system, and functions as a separate transmission line for the direct chroma signal when receiving the NTEIC system. do. Operation switch, cheer 4, turns off when receiving PAL system, and turns on when receiving NTSC system. The pace of the transistor Q88g is supplied with a negative horizontal planking normal (
P-)No#rus)Kakararareru.

This horizontal blanking pulse turns off the transistor Q839, and the nodal matrix circuit 76 has the function of blocking input signals during the horizontal blanking period. Transistor Q839 (meaning to remove the burst signal) is on and transistor Q840 is on.
When the chroma signal is turned on by the color signal, the pulse circuit 75 has the function of cutting off the transmission path of the chroma signal.

(1)-1 Operation when receiving PAL system - When receiving PAL system, the operation switch and cheer 4 are turned off, which causes transistor Q817゜Q818
turns on. As a result, transistor Q #17,
The collector potential of QIjllJ drops. The collector potential of transistor Q818 is V, (diode-P
The reduced voltage (potential drop due to the connection) appears at the emitter of transistor Q842, and this voltage is applied to transistor QRR9°Q822. Added to QIJII's pace. As a result, transistor Ql#9. QII
2jl.

Q821 is turned off. (Transistor QII22゜Q
821 is (R-Y), (B-
This is a transistor that functions to transmit the 4-way signal, but it is turned off when receiving the FAT signal.
A vector addition direct chroma signal in the pulse matrix is added to the pace of transistor QRIO. The direct negative (l-ji) added to the pace of transistor QlilO is the collector of transistor Q810 → resistor R876 → transistor Q/I:! 0→
It passes through the path of resistor R823 and is guided to resistor R823.

In this case, the direct chroma signal is the transistor QI
The phase is inverted at IIO.

Also, the direct chroma signal added to the pace of transistor QIJIO is transmitted from the emitter of transistor Q810 → resistor R816 ~ gloss R817 → transistor Q813
→ Resistor R876 → Transistor Q823 → Resistor R882
→It also leads to R826.

Next, the delay chroma signal is transmitted through transistors QRIR and Q.
Added to R17's pace. After this, the delay chroma signal is transferred from the bottom of transistor Q817 to resistor R81.
9→R818→Transistor Q814→Resistor R877→
It is guided to the collector of this transistor Q824 via the path of transistor Q/124, and the emitter of transistor Q817 → resistor R819 → R818 → transistor Q814 → cylindrical R878 → transistor Q82
5 → guided through the path of resistor R823. As a result, the direct chroma signal and the inverted delayed chroma signal are added at the connection point between the collector of the transistor Q824 and the resistor R82B. That is, vector subtraction between the direct chroma signal and the delayed chroma signal is performed.

At the connection point between the resistor R826 and the resistor R883 connected to the collector of the transistor Ql12δ, vector addition of the direct chroma signal and the delayed chroma signal is performed. The (B-Y) component of the vector addition result is
The (RY) component of the result of the 4-act' subtraction is applied to the base of transistor Q826.

(1) Operation when receiving the -3NTSC method When receiving the NTSC method, the A matrix circuit 75 performs amplification and separation processing of the direct chroma signal.The operation switch and cheer 4 are turned on at this time. Therefore, the base potential of the transistor QB111°QRlr constituting the system switch circuit 7g becomes low, and the base potential of the transistor Q81
11. QIIIj3. QRlr is turned off.

Therefore, the transistors Q81J, Q8R8, and QR84゜98 constituting the system switch circuit 7g
Among the 1g transistors, the collector potential of transistor Q818 is high, while the collector potential of transistor Q819 is low.

Since the collector potential of transistor Q818 is high, the emitter potential of transistor Q842 is also high, and this emitter potential is added to the bases of transistor Q889 and transistor Q821.

This causes transistor Q889. Qllll! 2.
QIJII transitions from off state to on state. on the other hand,
As the collector potential of transistor Q819 becomes lower, the emitter potential of transistor Q841 also becomes lower, and the emitter potential of transistor QII23 becomes lower.
It is applied to the base of base transistor Q820 of QR24 and Q826, turning off these transistors.

As a result, NTSG! At the time of system reception, the transistor Ql! which forms the transmission path of the delayed chroma signal. 1
The 15°Q824 is turned off and the delay chroma signal is cut off. Therefore, when receiving the NTSC system, the base and collector of transistor fiQI110 → resistor R87
5→transistor Q821→resistor R880 to the base of transistor Q826, and also the base of transistor QRIO, ri→resistor R816→
Resistor R817 → Transistor Q818 → Resistor R876 →
It is applied to the base of transistor Q827 via a path from transistor QIIM2 to resistor R881.

The signal applied to the base of transistor QIJ2r is
The structure of transistor Q827, T → DC power, capacitance for G → transistor CRoJ. 832 4-S・ENG? , and is input to the next stage (B-Y) demodulator 76 via the data path.

Further, the signals applied to the 4th terminal of the transistor Q826 are the capacitance 1cRO1 for the transistor Q826, the DC power, and the transistor. The signal is inputted to the next stage (RY) demodulator 77 via the 83 base line path.

(The gain in the matrix circuit 75 is the same as when receiving the PAL system and when receiving the NT
The gain is automatically switched depending on when receiving the SC system. However, the output DC potential does not change in response to system switching. During PAL mode reception, vector addition between the direct chroma signal and the direct chroma signal is performed on the collector side of transistor Q826, and vector subtraction is performed on the collector side of transistor Q824. Vector addition is performed by extracting the (B-Y) component, but the resistor R825 acts as a load for the transistor Q81g that amplifies the direct chroma signal, and the transistor Q82 that amplifies the delayed chroma signal
5, (resistors RR2B-4-RR26) becomes the load. On the other hand, regarding vector subtraction, vector subtraction extracts the (RY) component υ, and resistor R822 is a load for transistor QIIIO, which inverts the direct chroma signal, and amplifies the delayed chroma signal. For the through transistor Qg14, the resistor RR
22.

R823 becomes a load.

Next, when receiving the NTSC system, the transistor IQI
j12F) negative fjh resistor R11B, RIPt6°, and the load of transistor Q821 is resistor RRx2, R
R; t3, Ray9.

As mentioned above, 1. It is possible to switch the load for the (B-Y) component and the (R-Y) component in the -P matrix circuit.By switching this load, the output DC potential does not fluctuate (,13 The relative amplitude ratio (B - Y )/(RY) of the -Y axis and RY axis components can be set to 1 when receiving the PAL system and 0.56 K when receiving the NTSC system. An amplitude ratio suitable for each method can be automatically switched and obtained.

(1) -5 no? In the Lumatrix circuit 75.

During PAL system processing and NTSC system processing,
Although it operates to switch the amplitude ratio of (B-Y)/(R-Y), the vectors of the direct chroma signal and the delayed chroma signal will now be described as α and β.

FIG. 11C) shows the vector of the direct chroma signal during PAL reception, and FIG. 11C) shows the vector of the delayed chroma signal. The (B-Y) component is shown in Figure 11 (
, ), the amplitude can be expressed as α(R825)−1−β(RR25).

However, R825 is the value of resistor R826 in FIG. Next, the (RY) component is derived by inverting the phase every horizontal period, and as shown in FIG. 11(d), -
2(RY) or 2(RY). At this time, the amplitude is ~β(1'l,?ff)-α(R82z)
It can come as a rain. However, R822 is the 6th
This is the value of resistor R822 in the figure.

Next, when the system is switched to NTSC processing, only the direct chroma signal shown in FIG. 12 (R) is processed. The chroma signal applied to the (B-Y) demodulator consists of 2 (R-Y) components and 2 (
The amplitude in this case can be expressed as α(RII26+Bttzr;). However, R112g and R82fj are the values of the resistor RII j 6゜μ826 in Fig. 6. be.

Also, the chroma signal applied to the (RY) demodulator is the first
As shown in Figure 2, the 3.56 (B-Y) component and 3.
It is derived as a composite vector of 56 (TI-Y) components,
The amplitude in this case is -α(R822+R82J+R87
9) As a result, there is a hailstorm. However, R822,R
II23°R879 is the resistor R822 and R823 in Figure 6.
It is a value of °R879.

(1) Modification example 13 of -6 pulse matrix circuit 75
Figure (#I) (b) shows other embodiments of the pulse matrix circuit.

To explain from the circuit of FIG. 13(A), 91 is a reference ground potential line, 92 is a constant current setting noise line,
93 is a pace noise line, rsb is a direct chroma signal input line, and 751 is a delay chroma signal input line.

Furthermore, 94 is a switching signal input line from the system switch circuit, and 95 is supplied with a reference voltage.

During NTSC reception, the switching signal input line 94 reaches a low level. For this reason, transistor Q111. Q
3B, QJj6. Q34 is turned off. Therefore, the direct clock 4 signal passes through the emitter-collector path of the pace collector transistor Q31 of transformer NXI'Q11 and is led to the (RY) component output line 96 6b. Also, the pace emitter of transistor d
lR12, passes through the emitter-collector path of the emitter-collector transistor Q33 of the transistor Qfj, and (B
-Y) component output line 91.

Next, when receiving the PAL system, the switching signal input line 94 becomes high level. Therefore, transistor Q315*
Q! 16. Q34 turns on and transistors QJJ, Q
JJ is off. Therefore, the direct chroma signal is led out to the (RY) component output line g6 via the transistor QII→transistor Q31→resistance R32, and also via the transistor Qll→resistance R11→R1jl→
Transistor Qljl → Transistor QJ4 → Resistor R3
4 to the (B-Y) component output line. On the other hand, the delay chroma signal is as follows: transistor Q21 → resistor R21 → R2'2 → transistor Q? After passing through j,
It is distributed to the transistor Q, 96 side and Q3S side, and guided to the (RY) component output line 96 and (Fl-Y) component output line 97 sides, respectively. This allows matrix and matrix processing during FAI/method processing to be obtained.◎ Let the signal applied to transistor QjJ be F(p)n, and the signal applied to transistor Qll be F(p)n
+ 1, the signal that appears on the output line (27) is ``'(Tl)n +F(p)n++ = (α'(B-
Y) ±jβ'(RY)1+(α'(B-Y) hand Jβ'
(RY))=2α'(n-y) Similarly, the signal that appears on the output line (q/) is "(P)"
n''(p)n++ =±j2β(RY).

Next, the nominal matrix circuit shown in FIG. 13(b) will be explained. In FIG. 13(b), FIG. 13(TI)
In this circuit, the constant current source 1 of the transistors Q41 and Q42, which can receive and amplify the delayed chroma signal, is designated by the same reference numerals.
It is configured to be turned off or on depending on C system or PAL system processing.

During NTSC processing, constant current source ■1 is turned off, so only the direct chroma signal is transmitted through transistor Q4J.
During 6PAL processing, the delay chroma signal is outputted to the collector side of the transistor Q41 and the collector side of the transistor Q44 by turning on the constant current source 1.
4g, Q46 to enable matrix processing.

(2) 1-y)tut-y)t(a-y) demodulator and phase synthesizer.

Figure Wc7 shows the (B-Y), (R-Y), (G-Y) demodulator rfJ, 77.78, and Figure 8 shows the phase combination -8
8 is shown.

(211 (B-Y) (R-Y) (G-Y) Demodulator (PA
L method reception) Derived from the emitter of transistor Q832 (B-
Y) component is each (
The (RY) component supplied to the - source and derived from the emitter of transistor Q831 is
Pace fed. (B-Y) In the demodulator 76,
Transistor Q 854, Q J 55. Q/
? 62, QIj63゜Qfi64. Q865 constitutes a multiplication circuit, and transistors QII64,
QFII; 3 common pace with phase synthesis B from #88
-Y demodulation subcarrier (B -YCW) is added.

The demodulated signal (B-Y) of the (B-Y) component is transmitted by the transistor Q862. It is derived through the common collector of Ql164 through the path emitter of transistor Q874→resistor R866. Also, the demodulated signal of opposite polarity -(B
-Y) is derived from the common collector of transistors QB6B' and Q86B to resistor R868 for matrix and
1]-ru. On the other hand, in the (RY) demodulator 78, transistors Q856, Q857, Q866, QR
67, "Q868 and QR69 also constitute a multiplication circuit, and the common 4-path of transistors Q867 and Ql!6B is connected to the RY demodulation subcarrier (R
-YCW) is added. (RY) component demodulated signal (
RY) is derived through a path from the common collector of transistor QR67°Q869 to the pace emitter of transistor Q875 to resistor Bs7o. Moreover, the demodulated signal (R-Y) of opposite polarity is transmitted through transistors QIJ66 and QR61.
1 to the matrix resistor R871. Therefore, the demodulated signals (B −, Y ) and (R
−Y ) resulting demodulated signal (G−
Y) is derived through a path from the base emitter of transistor Q876 to resistor R872. transistor Q8
The demodulated signal obtained at the transistor Q869 and the demodulated signal obtained at the collector of the transistor Q866 whose load is the resistor R868 have a phase difference of 1806 points.
The phase difference between the 1m signal obtained at the collector resistor R867 and the W@ signal obtained at the collector of the transistor Q862 is 1800 degrees. The demodulated signal (G-Y) is obtained by vector synthesis of the multi-picture signal (B-Y) and the demodulated signal (R-Y).

(2)-2(R-Y)(B-Y)(G-Y) Demodulator(N
When receiving TSC method) (B-Y) rear body when receiving NTSC method"Li2,
The operation of the (RY) demodulator 77 is the same as when receiving the PAL system. However, during NTSC reception, the collector potential of transistor Q844 decreases due to the operation of system switch circuit 79, and transistor Q8
The collector potential of 43 becomes high. Transistor Q843
When the collector potential of transistor Q FJ 59. which constitutes the (G-Y) demodulator 28 decreases, QR60 is off stone. As a result, the transistor Q II 61°Q86
B turns on, and the chroma signal from matrix circuit 75 is led out to the collector via the pace of transistor Q861. At this time, transistors Q85B and QII61
, G87 (7°QR7!1, G872, QF17
3 functions as a multiplication circuit, and transistor Q/17.9
, G871 has a $1 calculation output of the (G-Y) demodulation subcarrier (G-YCW) (actually for vector phase correction of the G-Y axis) and the (B-Y) component. A demodulated signal for correction (G2-Y) is obtained. Therefore, when receiving the NTSC system, the return pl signal (87Y) is received.

A matrix operation is performed on the three signals (RY) and (G2-Y), and the resulting signal is the normal demodulated signal (G2-Y).
−Y).

(3) Description of phase synthesizer 88 and demodulation axis FIG. 8 shows a phase synthesizer f188. and the phase synthesizer 88 of (B-Y) and (R-Y).

The relationship between the demodulation axes of the (G-Y) demodulators 76, 77, and 78 will be explained with reference to FIGS. 7 and 8.

(3) The subcarrier necessary for demodulation axis color demodulation when receiving -1 PAL system is not obtained by the automatic phase control (APC) loop, but is also generated by the phase synthesizer 88 using the burst signal as a reference.
It will be done. R-Y demodulation subcarrier for the B-Y axis (B-Y
CW) is a transistor Q that constitutes the phase synthesizer 88.
Second reference oscillation signal (b) added to the pace of 784
is made using This second reference oscillation signal (b) is
This is a signal created by K, also known as a stone, that delays the first reference oscillation signal (^), and the first reference oscillation signal (tortoise) is: ・9-
This signal is generated in an APC loop including a voltage controlled oscillator 87 in phase synchronization with the strike signal. When the second reference oscillation signal (b) is applied to the pace of transistor Q734, a signal (b) of the same phase is applied to the collector of transistor Q735. This signal (b) is transmitted to the subcarrier B-Y for B-Y demodulation via the transistor Q739.
CW is derived from its collector and added to the common space of transistors QFI6B and QFI64 shown in FIG.

Next, looking at the R-Y axis subcarrier (R-YCLV), the R-Y demodulation subcarrier (R-YCW) is the first
This is generated by the phase synthesis circuit 88^. The first phase synthesis circuit 88 includes transistors Q742. Q743
．． Qr44. Q14s.

G746. Q747%.

A first reference oscillation signal (A) is applied to the pace of the transistor Q742, and a second reference oscillation signal (b) is applied to the pace of the transistor IIQ74s. transistor Q
742 and G743 are connected in common to the transistor Q740 forming a constant current source. Therefore, the collector of the transistor Q742 receives a signal of -(--b)=b-, and the collector of the transistor Q743 receives a signal of (^-b). The signal (b-IL) can be led out to the collector side of the transistor Q746, and the round signal (A-b) can be led out to the collector side of the transistor Q747 using the resistor R729 as a load. Here the signal (b
-A) or the signal (Lue b) is derived from the transistor Q746. The signal applied to the common base of Q746 is determined by the state of the output from the Pfrog circuit 86. That is, the inverted and non-inverted output P4. of the free lag prop circuit 86. When the output P4 of P5 is at a high level, -(^-b) is output through the transistor Q745.
=b-b is led to resistor R729, and when output P4 is at a low level, ^-b is led to resistor R729 via transistor Q747. Buri, I'm not talkative.

As explained in FIG. 5, the state of the switching circuit 86 is inverted every horizontal period, so when receiving the PAL system, the signals (b-^) and (a-b) are It is output alternately every time. The phase of the R,Y 1I11114 subcarrier R-YCW is inverted every horizontal period, and the demodulation of the R-Y component is performed.

The R-Y demodulation subcarrier (R-YCW) is added to the pace of transistors Q867 and QR61J shown in FIG. During PAL reception, a phase difference of 906 is established between the BY-axis and the RY-axis regarding the subcarrier.

During PAL reception, the transistor Q818 in the system switch circuit 79 shown in FIG.
The black level is high and the collector potential is low. Then, the emitter potential of transistor Q842 also becomes low, and therefore the collector potential of transistor Q844 becomes high.
The collector potential of transistor Q843 is increasing.0 Transistor Q84 of the above system switch circuit 79
The collector potential of 3 is also applied to the paces of transistors Q751 and Q755 in the phase synthesizer 88.

Therefore, during PAL reception, the pace potential of the transistors Q'151 and Q75B in the phase synthesizer 88 becomes low, and the pace potential of the transistors Q'151 and Q76 becomes low.
5 is off. Therefore, when transistor Q765 is turned off, its collector is turned off by resistor R729, so the signal (^-b).

Only (b-^) is derived as a subcarrier.

Next, the G-Y axis during PAL reception will be explained. P
At the time of AL system reception, the transistor Q s J B configuring the system switch circuit 7g shown in Fig. 6
, Q 8 J y , Q 841 , QFI42
Depending on the states of QR43 and Qli44, the transistor Qli61Q858 of the 90-Y demodulator shown in FIG. 7 is turned off. Therefore, the chroma signal (B-Y component) obtained through the emitter of transistor Q832 is
It is blocked by Q861. As a result, in the G-Y demodulator, the subcarrier for G-Y demodulation (G-YCW)
The multiplication operation between and (BY) component is not performed. However, in this case, a predetermined DC voltage is applied to the collector of transistor Q873. When receiving the PAL system, as explained in Figure 4), -(B-Y)
A (G-Y) demodulated signal is obtained by a matrix of the demodulated signal of and the demodulated signal of -(RY). In one-way sum synthesizer 88, the signal (λ) (also) is transmitted to transistor Q764. input to the pace of Q765, and the mixed result is the subcarrier for G-Y demodulation (,G-YCW)
However, the loss does not affect the demodulation function and is bypassed through the capacitor c8os shown in FIG.

(3) -2 NTSC system reception - axis When receiving the NTSC system, it was used when receiving the PAL system. 4
Since the chroma signal circuit 75 is shared, it functions as a chroma signal transmission path as well as a separation path. N.T.
SC method reception method, Furi, Pfrog circuit 86
The operation of is stopped by the system switch circuit 79.

In the case of NTSC reception method, the rear body phase of the demodulation axis is P.
Different from that during AL system reception, the relative phase difference between the BY axis and the RY axis is set to about 105°. The relative amplitude ratio of demodulated signals also differs between the NTSC system and the PAL system. This is because the setting of the white color temperature is different between the PAL system and the NTSC system. This system is switched to satisfy such conditions.

For NTSC reception, the state of each transistor constituting the system switch circuit 79 is reversed from the state at the time of PAL reception. Therefore, in the phase synthesizer 88, transistors Q741, Q761, Q7
1 and 5 turn on and transistor Q760 turns off. When transistor 9741 is turned on, transistor Q 7
42°Q743 is off. Next, transistor Q7
When 51 is turned on, the transistor Q 7 S 2゜Q7
53 is turned off. R-Y when receiving NTSC system
The sub-liquid carrier wave for Qll (-YC'W) is extracted in the same way as when receiving in the PAL system.

On the other hand, transistors Q749 and Q110.

Q761, QrgR. QrgR and Q766 cape form a second phase synthesis circuit 1j8b. transistor Q
Since the resistor Rr33 is connected to the base of the 750, the reference oscillation signal (A) is kl・a (0<k+ (
t), the absolute value of which is varied, and the transistor Q750
applied to the base of

Also, a resistor R731 is connected to the base of transistor Q249.
is connected, the reference oscillation signal (b) is applied to the base of the transistor Qr49 with its absolute value varied to kI-b. As a result, a b-kl loop is applied to the vector signal at the emitter of the transistor Qrg6.

When receiving the NTSC system, the operation of the clip prop circuit 86 is stopped and the output P4. Since P6 is at a low level, transistors Q7/156 and Q752
, Q7ko6, CJ14B.

Q764. QrgR, Q147. Q744 is off. Therefore, on the collector side of transistor Q755,
A signal with a phase set at about 105° with respect to the B-Y axis (1% in kl a-) is G-YfJl! It is derived as the subcarrier for the key subcarrier -YCW). Since phase adjustment is based on vector synthesis, resistor R73
2, by selecting the value of R731.

In this way, the 90-Y demodulation subcarrier (G-
YCW) is the transistor QB67°Q shown in FIG.
Added to the 868 common base. In this way, R-Y
The axis subcarrier (R-ycw) is 1 with respect to the B-Y axis.
A phase difference of 0.056 is generated in a haze.

Furthermore, in the R-Y demodulator 77, the (R-Y) component is 1. f in the matrix circuit 79.

Since the amplitude for the '(B-Y) component is adjusted and input, ff1ll compatible with the NTSC system is performed.

Next, the G-Y axis during NTSC reception will be explained. Even when receiving signals using the NTSC method, the G-Y axis needs to have the same phase as when receiving signals using the PAL method. However, when the system switches from the PAL system processing state to the NTSC system processing state, the gain for (R-Y)m in the norm) The size is larger when processing the PAL method.Therefore, as with the PAL method processing, the G-Y demodulator 78 simply performs matrices.

The G-Y
The axis does not reach the desired phase. Therefore, when receiving the NTSC system, it is necessary to correct the G-Y axis phase of the G-Y signal.

The G-Y axis correction means during NTSC reception will be explained. When receiving the PAL system, the G-Y demodulated signal is demodulated by performing matrix processing on the BY demodulated signal and the R-Y demodulated signal, but when receiving the NTSC system, the B-Y demodulated signal and the R-Y demodulated signal are demodulated. In addition to the Y demodulated signal, (B-y
) component is demodulated using the detection output of the G-Y demodulation subcarrier (G-YCW). ntJ, phase synthesizer.

At 88, transistor Q y e 4 , Qr
gR.

Q767, QrgR, Q769, etc. constitute the third phase synthesis circuit R8a. Since the resistor R737 is connected to the base of the transistor Q264, the reference oscillation signal (PN) is attenuated to tl''ll (0<tt<1) and applied to the base of the transistor Q764. A resistor R is connected to the base of the transistor Q765.
739 is connected, the reference oscillation signal (b) is
1.・b (0 (ta < 1)) is attenuated and applied to the base of transistor Q765. Therefore, to the collector of transistor Q764, t, ta b - t
, ・・ﾾ vector signals are obtained, and the signals are converted into G-Y demodulation subcarriers (G-Y demodulation subcarriers) to generate correction vectors.
YCW), the transistor Q of the G-Y demodulator 78
/? y2. Added to the common pace of Q, II 71. As a result, in the G-Y demodulator 28, the chroma signal obtained from the base of the transistor Q861 [710] is multiplied by the G-Y demodulation subcarrier (G-YCw), and the resulting vector is The signal becomes one of the matrix elements as a correction vector signal. With this operation, a 90-Y rear body signal having a correct demodulation axis can be obtained during NTSC reception.

In other words, if the correct G-Y axis cannot be obtained in the matrix circuit adapted for PAL processing, the correction subcarrier (G-y
cw ), and as shown in FIG. 14, the correction vector (G-Y) is
It is what creates UD. This makes it correct (G
−Y) axis demodulated output can be obtained.

(3)-3 In the phase synthesis stabilizing phase synthesis circuit in the second phase synthesis circuit 88b and the third phase synthesis circuit 88e, phase synthesis of the reference oscillation signal (N) (b) is performed. It is necessary to ensure that the output is not affected by the hfe of the transistor.

Now transistor Q749. Detailed measures taken for the phase synthesis circuit made up of Q750 will be explained.

Now, in this phase synthesis circuit, if the resistor R733 was not provided, the following problem would occur.

FIG. 15 (tortoise) shows a simplified phase synthesis circuit when the resistor R731 is removed, but with this configuration, the phase synthesis output is unstable.

In FIG. 15 (tortoise), the reference signal (e) is input to the R-s of the transistor Q760 via the path from the pace emitter of the transistor Q1 to the resistor R732, and the reference signal (b)
) is input to the base of transistor Q749 via the pace emitter of transistor Q2.

The value of resistor R732 is lkΩ, and the value of resistor R733 is 6Ω.
shall be. FIG. 15(b) shows an equivalent circuit as seen from the reference signal turtle, and FIG. 15(o) shows an equivalent circuit as seen from the reference signal. Using this circuit, transistor Q7
49. Let's find the base input voltage of Q7so.

K...Holmann constant, (1,38x 10-" J
/K)q ・-・electron, child charge 11 (1,6xl
o-19ri-* y) T... Absolute temperature 27f + room temperature 27°) KYq,... 26 mV Pace input t'lu-u of transistor Q760 Base input vInb of transistor Q749 is null as υ1nb=b. H. When changing the value to 50, 100, and 300, the input vectors are 0.733"a, respectively.

The color subcarrier composite vector J of 0.792m, 0.818"a, and different output powers is resistively divided and amplified by 9 times λ and L, and its phase error ΔQ changes by about 7°. - That is, it will be affected by hfe as shown in the composite pattern AOIHe2t2g shown in FIG. 15(d).If the subcarrier fluctuates like this, accurate color demodulation cannot be obtained. Further, when the phase synthesis output is used in a killer detection circuit, a malfunction may occur in the color killer operation.

In order to prevent the above-mentioned phase fluctuations, in the system of the present invention, a resistor Rrsl is further provided as shown in FIG. This is done to obtain a stable phase synthesis output.

That is, the simplified circuit configuration in this case is better than that shown in Figure 16 (tortoise), and the equivalent circuit is as shown in Figure 16 (b).
(1) Ic is shown. From this circuit, the base input voltages of transistors Qr49 and Qr5ρ are determined as follows.

Resistor R732 = 1 to Ω, resistor R73B = 5 to Ω resistor R7
, vJ=800Ω.

KT 1 r = −X −= 0.045 ke b
1 The base input voltage of transistor Q750 is %-, and the pace input vInb of transistor Q749 is. hf@
The input vector when changing to 50, 100, 300 is 0.744'*, 0.896b.

0.794λ, 0.953, 0.818 turtle, 0.9
81"b, and the phase synthesis of the output (P)J2 is resistively divided at the input and differentially amplified, and the phase error is within about 1@. That is, as shown in Fig. 16 (d ), the phase synthesis pek 1.7te is almost 6 to 'fe'.
Therefore, the phase becomes stable without being affected.

It is used for accurate color demodulation and phase detection operations.

(4) In the color killer detection and O-killer operation phase synthesizer, 8H, the color killer detection subcarrier (K11ler-CW) is also generated. -C
W) is) 57') ZtaQ762. Q756 (derived from the D collector side and manually input to the killer detection circuit 83.

(4) -1 Color killer operation when receiving the NTSC method When receiving the NTSC method, the phase synthesizer 88
Transistor Q765 is on, and transistors Q766 and Q764 are off. For this reason, the resistance R
734 acts as a load for transistor Q762. The collector of transistor Q262 receives the signal (b)
This is the killer detection circuit 83.
Subcarrier for color killer detection (K, 11er-CW)
1 is added.

FIG. 9 shows the killer detection circuit 83 ident and the killer circuit 85. Killer detection subcarrier (K11l@r-C
W) is added to the pace of Tora:/JiXriQ 633, Q684. The killer detection subcarrier (K1l@r-CW) added to the transistor q633 and the burst signal added to the pace K and t of the transistor Q630 are multiplied by these transistors, and the output thereof is applied to the transistor Q634. The potential of the resistor R629 is controlled through the path of 4-semitter→resistor R621→pace collector of the transistor Q641.

This resistor R629 is connected to the killer filter υ, and its filter voltage is equal to the ident and killer circuit 8.
It is added to the pace of transistor Q663 which constitutes 5.

Now, when a burst signal exists and the voltage of the Qler filter increases, the transistor Q663, which constitutes the ident and killer circuit 86, turns on. (Currently, NTSC
(Since this is an explanation of system processing, the identification operation itself will be explained later.) When transistor Q663 is turned on, transistors Q659. Q660 current increases,
Since the N current in transistors Q65R and Q661 decreases, the current in transistors Q65 and Q666 decreases. In this way, during NTSC processing, when a node signal is detected, the output of the transistor Q665 is applied to the transistor Q840 of the nine node matrix circuit 75 as explained in FIG. 6, and this is turned off. There is. When the transistor Q840 is off, the pulse matrix circuit 75 functions as a transmission path and separation path for NTSC chroma signals.

On the contrary, the burst signal is not detected in the killer detection circuit 83, and the resistor R in the killer detection circuit 83
When the terminal voltage of 629 decreases.

The terminal voltage of the killer filter also decreases. Therefore.

From the terminal voltage of the killer filter, transistor Q66
3 minus the base-emitter voltage V, is applied to the pace of transistors Q660, Q659; Q659 turns off. Therefore, the collector currents of transistors Q661 and Q65B increase, and accordingly, the collector currents of transistors Q661 and Q65B increase.
The collector current of 66°Q665 will also increase.

When the collector current of transistor Q665 increases, transistor Q840 in the pulse train circuit 75 increases.
When the pace potential of the transistor Q840 is high, the transistor Q840 turns on. When this transistor QIj40 turns on,
Regardless of the NTSC system or PAL system processing, the transistors QR10, QF113 . Q814. Ql
All i17 are turned off and a color killer operation is performed.

In this way, all the chroma signal transmission paths of the /4' matrix circuit 75 can be cut off by the collector output of the transistor Q665. It is also supplied to a switch circuit (not shown) that turns on and off the output of the /J noise filter, and the output of the /J noise filter itself is also cut off, making it possible to perform the color killer operation twice.

FIG. 10 shows a flip-flop circuit 86.

During NTSC reception, the collector potential of the transistor Q844 of the system switch circuit 79 is high, and therefore the transistor QJ4 in FIG.
5v Q Fl 46+ Q R" +Q667 is on. Therefore, the switch composed of transistors Q66R and Q669 is on during NTSC reception, and therefore transistor Q610 is off. Transistor Q670 is off. Then, the energizing voltage is not applied to the flip-flop circuit 86 and the operation stops. Therefore, the output P4 of the flip-flop circuit 86
．． Both P5 become low level during N,TSC method processing.

(4) Color killer operation and identification operation during -2PAL system reception During PAL system processing, the color killer detection subcarrier (Kl 11er-CW) output from the phase synthesizer 88
, ) are inverted in phase every horizontal period and input to the killer detection circuit 83. This is because in the PAL system, the phases of the burst signal and the R-Y axis are inverted every horizontal period. The subcarrier (Kl
This is to synchronize the 11er-CW). P.A.
During L method processing, the collector potential of transistor Q843 of system switch circuit 79 shown in FIG. 6 is low. For this reason, the phase synthesis circuit 88 shown in FIG.
In , transistor Q761.

Q755 turns off. Therefore, transistor Qf/8
2. Q163. Q764. Q766 can be on, but one set of transistors Q 75 J +Q754 and transistor Q71y! .

Whether one set of Q756 will be turned on or not, it is a matter of free f.
It is determined by the states of outputs P4 and P5 of the flop circuit 86. That is, the output P4 of the FRI, GFR, and P circuit 86
is added to the pace of transistors Q752 and Q756, and the output P6 is added to the pace of transistors Q753 and Q754. Now, output P4 is at high level,
When the output P5 is low level, the transistor Q750
The Klb-KI II signal is derived as a killer detection subcarrier (K11ler-CW) through the collector of the transistor Q756 and the emitter collector of the transistor Q756. When the output P4 is at a low level and the output P5 is at a high level, the Collector → transistor Q754
A signal of KIk-K@b is derived as a killer detection subcarrier (Kllll.r-CW) through the emitter collector of . υ, the output p4 of the flip-flop circuit 86. Depending on the state of P6, the subcarrier (K11le
r-CW) is (Kl to * b ) * (Kt
It is derived by inverting the phase as ＾− and b). Also,
During PAL reception, the collector potential of transistor Q844 in system switch circuit 79 is high, so transistor Q760 in phase synthesizer 88 is turned on, and transistors Q76B and Q759 are turned off. Therefore, transistor Q762 is also turned off. The resistor R734 is connected to the transistors Q756 and Q7S2.
A load is applied to the load alternately every horizontal period.

The color killer detection subcarrier (K
11l@r-CW) is added to the common 4-path of transistors Q63J and Q634 of the killer detection circuit 83 shown in FIG. When receiving the PAL system, the burst signal input to the color killer detector 1 path 83 is -(B
-Y) axis is input with a phase deviation of ±400 every horizontal period.

On the other hand, in the flip-flop circuit 86 shown in FIG.
Since the collector potential of transistors QR46°QF146. QII47. Qf;157
is turned off, and the transistor Q66 forming the switch is turned off.
/? , Q669 is also turned off. Therefore, the transistor Q670 is turned on, and an energizing voltage is applied to the flash drive circuit 86, making it in an operating state. Also.

This is the transistor Q677 of the frog circuit 86.
A periodic f-) pulse is added to the horizontal synchronization signal to pace output p4. The state of pi is inverted every horizontal period.

In the killer detection circuit 83 shown in FIG. 9, as described above, the killer detection subcarrier (K11l@r-CW
) and a burst signal whose phase swings every horizontal period. Therefore, the output from the two-layer killer detection circuit 83 during PAL processing includes information on whether or not to perform the color killer operation, as well as the inversion and non-inversion phases of the flip-flop circuit 86, which are the correct phases. It also includes information on whether or not.

Now, in the color killer detection circuit 83, transistor Q633. There is a correct relationship between the phase inversion of the killer detection subcarrier (K port 1st -CW) added to the pace of Q634 and the swing of the burst signal (±40° swing). -C%V) and (R
-Y) components are in phase, transistors Q634.
The current flowing through Q641 increases. transistor Q64
1 increases, the terminal voltage of resistor R629 rises, and the terminal voltage of the killer filter also rises.

This increases the emitter current of transistor Q663 of ident and killer circuit 85, causing transistor Q660. Q659 turns on. transistor Q660
．． When Q659 turns on, transistors Q661 and Q
I558 turns off, and along with this, transistor Q66
g.

Q665 turns off. Therefore, transistor Q66
No current is supplied from the collector of transistor Q675 to the emitter of transistor Q675 constituting the circuit 86. This means that the inversion of the flip-flop circuit 86,
86
teeth.

Means to continue the current operation. One oshi.

Subcarrier (K11ler-CW) and burst signal (
When the RY) components are in phase, the state of flip-flop circuit 86 is not controlled. During PAL reception, the (R-Y) demodulation subcarrier (R-YCW) obtained from the second phase synthesis circuit ssb in FIG. Furthermore, if the flip-flop circuit 86 operates in the correct phase as described above, the transistor Q661
.

Since Q688 is turned off, transistor Q666゜Q6
6δ turns off. When the transistor Q665 is turned off, the collector output of the transistor Q666 is also applied to the pulse of the transistor QR40 of the pulse circuit 75, but the transistor Qli40 remains turned off.

Therefore, the )4 matrix circuits 75 operate normally without the killer operation being applied. During PAL reception, the PAL matrix circuit 75, as described above,
The chroma signals are added and subtracted to derive the (RY) and (Fl-Y) components.

Next, during PAL reception, the phase inversion situation of the killer detection subcarrier (Klll@r-CW) and the phase inversion situation of the (R-Y) component of the -st signal are opposite in phase. I will explain what would happen if it was different.

When the phase state of the killer detection subcarrier (Klll.r-Cw) and the (RY) component of the burst signal is in an opposite phase relationship, in the killer detection circuit 83 of FIG.
The detection voltage becomes low.

The terminal voltage of the resistor R629 is low, and the terminal voltage of the killer filter is low. Therefore, the emitter potential of transistor Q663 of the ident and killer circuit 86 becomes low, and the emitter potential of transistor Q660. Ql;69 is turned off, and transistors Q661 and Q65B are turned on. Transistor Q661. When Q661J is turned on, transistors Q666 and Q66B are also turned on. When the transistor Q666 is turned on, its collector current flows through the emitter of the transistor Q676 of the f-frog circuit 86,
That is, it is supplied to the →− side of transistor Q674,
As a result, the phase of the 71J quadruple circuit 86 is inverted.

That is, the transistor Q674 in the flip-flop circuit 86 follows the pace of the transistor Q676 and is turned on regardless of the presence or absence of the L normal. In this state, the terminal voltage of the killer filter has dropped by V and Q.
The pace voltage of 660 is further V,
The reduced voltage VL-V continues in a higher trench.

On the other hand, the phase of the killer detection subcarrier (Kl 1lpr-CW ) supplied to the killer detection circuit 83 is large when the (RY) axis component of the Norst signal is positive, and small when it is negative. The flip-flop circuit 86 is set close to the (RY) axis so that the killer detection circuit 83
When the flip-flop circuit 86 enters the stop mode due to the ident signal applied to It is set. Therefore, from the moment the flip-flop circuit 86 stops, the killer detection output in the killer detection circuit 83 generates a large positive output and a small negative output, and as a result, the killer filter output voltage v0 increases. do. ■This filter output voltage. is V for the above V. At the moment when it becomes 2vL, 1 ident and transistor Q66 of killer circuit 85
0. Qg61 is inverted, thereby causing transistor Q
When 666 is off, the pace voltage of transistor Q674 of prop circuit 86 is
As controlled by 7, the flip-flop circuit 86 starts inverting and non-inverting operations from the next horizontal synchronization node. At this time, (R
-Y) component and killer detection subcarrier (K11ler-C
If W) is in the correct phase relationship, the killer detection voltage will further increase and the voltage of transistor Q669 will increase.

The killer comparator of Q66B is inverted, thus transistor Q665 is turned off, the color killer condition is removed, the color receive mode is entered, and the correct color appears on the screen.

Next, as mentioned above, if we go back to the point in time when the flip-flop circuit 86 started inverting and non-inverting operations when Vo > VL, we can see that (R-
Y) component and subcarrier for killer detection (K11ler-C
W ) does not always have the correct phase relationship, and 18
There is also a probability that the phase difference will be Q6. At this time, the killer detection output starts to drop again from VL on vo, and after several horizontal periods, the transistor Q as an ident comparator returns again.
661, Q660 is inverted, which turns on transistor Q666 and turns on flip-flop circuit 86.
The pace of the transistor Q674 is forcibly set to a high level, and the operation of the flip-flop circuit 86 is stopped. As a result, the terminal voltage of the killer filter is V again, as described above. It started to rise towards Fivt, and Vo,>
V, the burst signal (R-Y) again
Depending on the phase relationship between the component and the subcarrier (K11ler-C%V), it is determined whether vo further increases or decreases again. Realistically, if the flop circuit 86 stops (E
It is said that the state has been released, and the //- strike signal (17,-
Whether the phase relationship between the Y) component and the subcarrier (K11ler-CW) is correct or incorrect is statistically estimated to be 5096, and is always incorrect.

The probability that the gray circuit 86 is released decreases in inverse proportion to the number of times it is repeated, and a correct color reception state can be obtained within a finite time.

As mentioned above, if the phase relationship between the (RY) component of the burst signal and the subcarrier (Kl 1ler -CW) is incorrect, the ident comparator by the transistors Q661 and Qf; As a result of this action, the flip-flop circuit 86 is temporarily stopped and then turned on again. Furthermore, in the ident and killer circuit 86,
A killer voltage rake is also configured by the transistor Q669.066B, and a killer voltage can also be output via the collector of the transistor Q66B.

Incidentally, the state reversal operations of the ident comparator and killer controller of the ident and killer circuit 85 shown in FIG. 10 do not occur at exactly the same timing, but are set at different operation levels. t#), the pace of a transistor Q664 that supplies the pace current of the transistor Q661 is connected to the pace collector of a transistor Q645 forming a bias circuit of the killer detection section. On the other hand, the pace of transistor Q662 that supplies the pace current of transistor Q658 is
Connected to 46 pace collectors.

As a result, during PAL reception, the subcarrier (K1
If the (R-Y) component of the burst signal is out of phase with the (R-Y) component of the burst signal, the killer detection voltage becomes a low voltage (also lower than the set voltage vL), and the FRI, PFLO, G circuit 86 is stopped ( (starts operation as the killer detection voltage rises), and.

Color killer action can be obtained. In addition, when a burst signal is not detected during PAL reception, a color killer operation is first obtained, and then a killer detection voltage V of the lips is obtained. U, v, , <vo≦■8. Therefore, in this case, the operation of the flip-flop circuit 86 continues. Next, the (RY) component of the burst signal and the subcarrier (Kl l
When l@r-GW ) is in a phase relationship with iE L, a high voltage of 78 or more is obtained as the killer detection voltage, and the transistor Q665. Both Q666 are off.

That is, as shown in FIG. 17, if the detection output is v)1 or more, the color killer operation and the stoppage of the flip-flop circuit cannot be obtained, and the detection output vo becomes v, > v, 〉
If it is vL, only color killer operation can be obtained. Next ■. <vL, the color killer operation and the control of the flip-flop circuit are performed.

〔Effect of the invention〕

As described above, the present invention is particularly advantageous in that during NTSC signal processing, the power supply is cut off by the ident and killer circuits so that both outputs of the flip-frog circuit are at their lowest level, so there is no need to worry.

Transistor Q to which the output of the Gutsu4vpu circuit is added
If the pace voltage of Q764 is sufficiently lower than the pace voltage of Q756 to which the output of the system switch circuit is applied, the switching of the phase synthesis circuit can be performed in an accurate and safe switching state. Then, it can be used to safely output the subcarrier generated by the phase synthesis circuit.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a color signal processing circuit for the NTSC system, Figure 2 is a block diagram showing a color signal processing circuit for the FAI system, and Figure 3 is a color signal processing circuit for both the PAL and NTSC systems. Figure 4 (A) is a circuit diagram showing the color demodulation circuit of the circuit in Figure 3, and Figure 4 (b) (,) shows the operation of the circuit in Figure 4 (1%). 5 is a block diagram showing an embodiment of the present invention, FIG. S is a circuit diagram specifically showing the pulse matrix circuit and system switch circuit of FIG. 5, and FIG. is a circuit diagram specifically showing the demodulator in FIG. 5, FIG. 8 is a circuit diagram specifically showing the phase synthesizer in FIG. 5, and FIG. 9 is a circuit diagram specifically showing the phase synthesizer in FIG. A circuit diagram specifically showing the circuit,
FIG. 10 is a circuit diagram specifically showing the Plizzo flop circuit and the ident and killer circuit in FIG. Figures 13(^) and (b) are circuit diagrams showing other embodiments of the Norm matrix circuit, respectively, and Figure 14 is the G-Y axis demodulation of the demodulator and phase synthesizer of Figure 5. Vector diagram 5 Figure 15 shown to explain the operation (
A) is the basic circuit diagram of the phase synthesizer, and Fig. 15(b) (
c) is a diagram showing the equinodal circuit of the circuit in the same figure (15 [g
1(d) is an explanatory diagram shown to explain the phase synthesis operation of the circuit shown in FIG. Figures 16(b) and 16(c) are schematic diagrams of isolateral ports of the circuit shown in the same figure.
Figure (d) is an explanatory diagram for explaining the phase synthesis operation of the circuit in Figure (1), and Figure 17 is an illustration for explaining the operation of the ident and killer circuits shown in Figures 5 and 9. It is an explanatory diagram of the operation shown in FIG. 66... IH delay device, 75... Normatrix circuit, 76-78... Demodulator, 79... System switch circuit, 83... Killer detection circuit, 85...
Ident and killer circuit, 86... flip-flop o,
7' circuit, 87... voltage controlled oscillator, 88... phase synthesizer. Applicant's representative Patent attorney Takehiko Suzue Figure 14 Figure 15 (a) Whistle 15 1! I (b) Figure 15 (C)

Claims (1)

[Scope of Claims] A first complex including a carrier color signal in which the color signal is transmitted by first and second modulation axes orthogonal to each other, and a subcarrier for the second modulation axis is inverted every horizontal period. In a color signal processing circuit that processes a color signal and a second composite color signal without inverting the subcarrier, a burst signal of the first and second composite color signals is supplied to one input terminal, a color killer detection circuit whose other input terminal is supplied with a color killer subcarrier and which performs phase detection of the signal applied to both input terminals; Generates an inversion control signal that inverts the subcarrier for the second modulation axis every horizontal period according to the detection output of the detection circuit, and the phase thereof is in phase with the burst signal in the first composite color signal. a flip-flop circuit whose output state is controlled to be a first voltage and a second voltage depending on the output of the identification circuit; and the first or second composite color. Phase switching means for inverting the phase of the subcarrier with respect to the second modulation axis according to the output of the flip-flop circuit in accordance with the output state of a system switch circuit that generates a voltage at its output that specifies which of the signals is to be processed; , when processing the second composite color signal, the flip-flop circuit can be stopped by lowering the output voltage of the system switch circuit, and the level of both output voltages of the seven flip-flop circuits can be lowered to the level of the first and second flip-flop circuits. and a flip-flop circuit stopping means for setting the voltage level to a third voltage level lower than the voltage level of the phase switching means to stop the operation of the phase switching means, and when processing the second composite color signal, the flip-flop circuit A color signal processing device capable of stopping a circuit and reliably stopping inversion of a subcarrier by the phase switching means.