JPS58213587A - Circuit for demodulating color - Google Patents

Abstract

PURPOSE:To perform a correct color demodulation against chrominance signal of multiple system, by installing a compensation vector generating means to compensate an axis in case the system of a chrominance signal to be demodulated is switched to another system to shifts the demodulating axis. CONSTITUTION:At a PAL matrix circuit 75, matrix processing of an 1H-delayed chrominance signal which is obtained by delaying a chrominance signal by 1-hori zontal period and a direct chrominance signal which is not delayed are performed, when the system processes TV signals of the PAL system. By this matrix processing, components (B-Y) and (R-Y) are separated from each other and inputted into a (B-Y) demodulator 76 and (R-Y) demodulator 77, respectively. On the other hand, when the system processes TV signals of the NTSC system, an operation switch 74 is turned on and the 1H-delayed chroma signal on a delay input line 75a is grounded. Then, only the direct chroma signal is inputted into the PAL matrix circuit 75 and the output condition of a system switching circuit 79 is also switched.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a color demodulation circuit used in a color television receiver or the like that is capable of receiving television signals of different formats in one unit.

[Technical background of the invention]

There are three color television signal systems currently used in the world: NTSC, PAL, and SFCAM. Each of these systems was uniquely adopted by each country or region, but with the progress of color television broadcasting using space satellites and the spread of video Teso recorders, signals of these different systems have been adopted. There is an increasing demand for so-called multi-system color television receivers that can receive images with a single color television receiver.

Conventional multi-scheme color television receivers have been designed to reproduce and process the signals of each system.
has an independent signal processing circuit. For this reason, conventional multi-system color television receivers suffer from an increase in price, power consumption, and
There are problems such as decreased reliability.

In order to solve the above problems, multi-system color television receivers have been developed that reduce the number of parts by increasing the number of circuits that can be used in common with each system when the signal systems are similar. . This multi-system color television receiver is capable of receiving images in the NTSC and PAI systems.

Here, the unique parts of NTSC and PAL color television receivers will be explained with reference to FIGS. 1 and 2.

FIG. 1 shows a color signal processing circuit of an NTSC color television receiver. 11 is a chroma signal input terminal, 12
is a band amplification circuit. The band amplification circuit 12 includes an automatic gain control circuit ACC and a burst dart circuit, and the automatic gain control circuit is a circuit that detects level fluctuations in the input signal and automatically controls the output so that the output is always at a constant level. A burst dart circuit is a circuit for separating a color signal component and a burst signal from an input signal. The chroma signal separated by the band amplification circuit 12 is input to the color control circuit 14 via the transmission line 13, and is amplified according to the user's adjustment. Color control circuit 14
The output chroma signal from the (B-Y) demodulator 15,
(RY) is input to the demodulator 17. On the other hand, the burst signal separated by the band amplification circuit 12 is input to the hue control circuit 19 via the transmission line 18. The hue control circuit 19 has a function of correcting, on the receiver side, a hue error caused by influence of the television signal on the transmission path, and adjustment for the correction is performed by the user. The phase-adjusted signal in the hue control circuit 19 is input to the color synchronization circuit 21 via a transmission line 20. This color synchronization circuit 21 includes a reference subcarrier generator for demodulation for generating subcarriers necessary for demodulating color signals, and a killer detector for identifying color broadcasting, white, or black broadcasting. The output of the killer detector is supplied to a color control circuit 14 or a demodulator,
The circuit function can be stopped to prevent color noise from occurring during black and white broadcasting. The reference subcarrier generator has an automatic phase control function that accurately follows the phase of the input burst signal, generates subcarriers for demodulation based on the phase of the burst signal, and transmits each subcarrier through transmission lines 22 and 23. (B-Y) Demodulator is * (R-y) Supplied to the demodulator 17.

The demodulators 15, 17 each have positive and negative outputs, and depending on the polarity of the picture tube drive circuit that drives the color cathode ray tube for image display in the subsequent stage, for example, the positive polarity output is sent to each output terminal 27.
29, and a negative polarity signal to the transmission line 25.2.
6 to a matrix (G-Y) demodulator 16 to obtain a (G-Y) output at a G-Y output terminal 28.

FIG. 2 shows a color signal processing circuit of a PAL color television receiver. Components having the same functions as those of the circuit shown in FIG. 1 will be described with the same reference numerals. The chroma signal output from the color control circuit 14 is input to the IH delay device 3 and also input to the PAL matrix circuit 33 via the attenuator 32. The output of the IH delay device 31 is also applied to this PAI/IJ wax path 33. PAL matrix circuit 3
3, matrix processing is performed on the IH (one horizontal period) delayed signal of the chroma signal and the non-delayed signal, and the signal is separated into a (B-Y) component and a (R-Y) component.
These are respectively (B-'Y) demodulators 15. (R-Y
) is input to the demodulator 17. On the other hand, in the PAL system, (RY
) component is transmitted with its modulation axis reversed by 180 degrees every horizontal period. This is a feature of the PAL system.
When the matrix circuit 33 performs vector synthesis of the signal one horizontal period before and the direct signal, the influence of subcarrier phase distortion on the demodulated signal is reduced. Since the PAL system is less susceptible to phase distortion in the transmission path, a hue control circuit is not required, and the burst signal separated by the band amplifier circuit 12 is directly input to the color synchronization circuit 21 to generate a reference subcarrier. used for purposes. ~The subcarrier for (B-Y) demodulation obtained by the color synchronization circuit 21 is (
B-Y) is input to the demodulator 15. In addition, the subcarrier for (RY) demodulation is driven by the horizontal retrace/irres and obtains an inverted operation every horizontal period/bus switch circuit 34
The phase-matched subcarrier is input to the (RY) demodulator 17. In addition, the inversion operation of this nozzle switch circuit 340 is as follows:
The color killer detection output information (obtained from the killer detector in the color synchronization circuit) controls the signal to be in phase with the transmission signal. When receiving PAL system,
In the noyal switch circuit 34, the internal flip-flop circuit is inverted or non-inverted by the horizontal retrace z'P pulse, but when a color killer signal is generated, the inversion operation is performed for one horizontal period by a so-called ident signal. The phase of the subcarrier for (RY) demodulation is controlled to have a normal relationship with the transmission signal phase.

In the above-mentioned color signal processing circuit dedicated to the NTSC system and the PAL system, a shared circuit that can perform common functions in both systems is configured as shown in FIG.

In FIG. 3, parts having the same functions as the circuits shown in FIGS. 1 and 2 will be described with the same reference numerals. In the case of this shared circuit, a switching circuit 35 and a system selection means 36 are further provided, and the output of the switching circuit 35 selects the PAL
Matrix circuit 33. The pulse switch circuit 342 is designed to switch the operation of the hue control circuit 19. During PAL reception, the control operation of the hue control circuit 19 is stopped and the band amplification circuit 1
The burst signal separated in 2 is sent directly to the color synchronization circuit 2.
1 will be introduced.

NTSC system receiving system receiving port color control circuit 14
The chroma signal derived from B is passed through a part of the PAL matrix circuit 39 without undergoing matrix processing (B
-Y) demodulator 15 and (RY) demodulator 17. Furthermore, the subcarrier for (R-Y) demodulation derived from the color synchronization circuit 21 is also input to the (R-Y) demodulator 17 without undergoing phase inversion processing via a part of the flat switch circuit 34. be done.

As described above, according to the color signal processing circuit compatible with both PAL and NTSC systems, the signal processing form is switched depending on the system of the received signal. In the above explanation, the PAL matrix circuit 33 determines whether or not IJ wax processing is to be performed for the chroma signal, and the switching circuit 35 determines whether or not to perform IJ wax processing.
Regarding the subcarrier, the f pulse switch circuit 34 determines whether or not to invert the (RY) demodulation axis by 1806 times per horizontal period. That is, in the above system, the phase processing function in the color signal processing circuit is switched depending on whether the PAL system or the NTSC system is being received.

If we further focus on the differences between the signals of the PAL and NTSC systems, the results are shown in Table 1 below.

Table 1 As can be seen from the table above, if the demodulation amplitude ratio of (B-Y)/(R-Y) is calculated and the NTSC system is set to 1, then N
In the TSC and PAL systems, the amplitude ratio of demodulated components is different.

This means that when transmitting color signals of red, green, and blue reference colors,
This is obtained by detecting the amplitude of the demodulated component. The reason why the demodulation amplitude ratio differs between the PAL system and the NTSC system is that the reference white color (color temperature) on the transmitting side differs between the systems. Therefore, in a color signal processing circuit compatible with PAL and NTSC systems, PAL system, NT
In the SC receiving system receiving port, it is necessary to change the circuit gain so that the demodulation amplitude ratio as shown in Table 1 above can be obtained.

Next, each component demodulation axis of the PAL system and the NTSC system will be explained. The (B-Y) component*(R-Y) component is input to the (B-Y) demodulator 751 and (R-Y) demodulator 17, respectively. This (B-Y) demodulator 15. (R-
The (B-Y) demodulation subcarrier 1 (R-Y) demodulation subcarrier generated in the color synchronization circuit 21 is input to the Y) demodulator 17, respectively. When receiving the NTSC method, (B
A phase difference of 105° is set between the -Y) demodulation subcarrier and the (RY) demodulation subcarrier.

Furthermore, during PAL reception, a phase difference of 906 is set and generated between the (B-Y) demodulation subcarrier and the (RY) demodulation subcarrier, and the (RY) demodulation subcarrier is The pulse switch circuit 34 inverts the signal by 180' every horizontal period. In this way, the demodulation axes of the (B-Y) and (R-Y) components are determined by the subcarrier generated by the color synchronization circuit 2. On the other hand, regarding the demodulation of the (G-Y) component,
) demodulator 16 is used.

- Figure 4 (,) shows (B-Y) demodulator 15, (G-
Y) demodulator 76 and (RY) demodulator 17 are shown.

(B-Y) In the demodulator 15, 42 is a phase detector using a double-balanced differential amplifier, and 41 is a constant current source. The phase detector 42 has a (B-Y) demodulation subcarrier (CWB
) and a chroma signal (CRO) are input. An output terminal 42a of this phase detector 42.

42b has detection outputs of opposite polarity, that is, (B″″
A demodulated output (Y) is obtained and is led out from one end of one (B-Y) demodulated output resistor 43 to the output terminal 27. The other (B-Y) demodulated output is input to the (G-Y) demodulator 16. The (RY) demodulator 17 also has the same configuration as the (B-Y) demodulator 15, and has a phase detector 46. It has a constant current source 45. The phase detector 46 receives the (RY) demodulation subcarrier (CWB) and the chroma signal (CRO). Output terminals 46m, 46 of this phase detector 46
Detection outputs with polarities opposite to each other, that is, (R-y) demodulated outputs are obtained at b, and one (R-y)(, l translation output is led out from one end of the resistor 47 to the output terminal 29. , the other (R-Y) demodulated output is input to the (G-Y) demodulator 16. The (G-Y) demodulator 16 has resistors 4B, 49 and a constant A current source 50 is connected in series, and the above (B
-Y) demodulation output is input, and the (RY) demodulation output is input between the resistor 49 and the constant current source 50. And (G
-Y) The demodulated output is led out to the output terminal 28 via the resistor 51.

(G-Y) demodulation output is (B-Y) demodulation output and (R-
Y) Obtained by matrix processing with demodulated output.

This is because in television signal transmission, the ratio between the luminance (Y) signal representing brightness and each signal plane of the three primary colors R, G, and H of light is determined. Y)
If the demodulated output is found, (G-Y) the demodulated output is uniquely determined.

Now, in FIG. 4 (-), if the demodulation conversion conductance of the phase detector 15.17 is shifted from gB r gR, the demodulation output amplitude EBeERt E of the output terminals 27, 29.28
G and DC voltage v, e vRp VG is the input signal el and [7, zn=el −g[I-R,, −・−・−・−・(1
)VB””VCCHI41” R4S°゛l゛°°°
...... (2) En=el ・gH' R47...
・・・・・・・・・・・・ (3) VB=VCC-HI 4
g llR4y −−°11°°…(4) gG=6.
°gB °R4s + elogR(Rn s +R4
s) -... (5) 1 vG0■CC2I41"R2H'2"46
°(R4g+R49)Is o (R4s +R4t
) ...---(6).

The above R48rR47yR4II and tR49 are the values of resistors 43 and 47.48.49, respectively, and I41°I4
5#I60 is the current value flowing through the constant current sources 41, 45.50 In the above circuit, each DC voltage VB, v,
, , If the values of the components are selected so that the VC is equal, there will be no change in the DC level and the brightness on the picture tube surface will not change significantly even when switching from the PAL reception state to the NTSC reception state. do not have.

Now, if the above demodulator is of the PAL system, vB + v, , J yc are set equal, and
EB/EER=1, 8 to satisfy the amplitude ratio in Table 1.
p Ea/En =0.6. As a result, the demodulated component vector is (B-Y)/(R-Y)=1.8, as shown in FIG. 4(b). (G-Y)/(
R-Y) = 0.6, the phase difference between the (R-Y) and (B-Y) axes is 90°, and the phase difference between the (G-Y) and (B-Y) axes is 2
Demodulated at 40°. Next, from the PAL reception state,
When switching to the SC reception state, the vector of TjPA components becomes as shown in FIG. 4(C). Here, since this demodulator is set to be compatible with the PAL system, the amplitude ratio of (B-Y)/(R-Y), (G-Y)/
The amplitude ratio of (RY) will be different from that in Table 1. Furthermore, due to the difference in this amplitude ratio, (
The phase of the GY) axis is shifted from the normal position (vector indicated by a broken line). Therefore, the phase of the (G-Y) component is returned to the normal phase, and at the same time, the amplitude ratio of (B-Y)/(R-Y)e (G-Y)/(R-Y) is shown in Table 1. We need a way to change the value to something like this.

Note that (G-Y) demodulation output is (B-Y) demodulation output and (R-
Y) What is obtained by vector synthesis with the demodulated output is based on the color television signal transmission system. In other words, there is a relationship between the luminance (Y) signal and each of the three primary colors (R, G, B) signals: Y = 0.3OR + 0.59G + 0.11B, and Y and (RY) and (B-Y) (G-Y)=-0,51(RY)-0,19(B-Y
), the (G-Y) demodulated output can be obtained.

[Problems with background technology]

As mentioned above, when Proposition 1 is applied to a multi-system color television receiver, in its color signal processing circuit, (R
-Y), (B-Y) #(G-Y), PAL
, shall be compatible with each NTSC system, and (B-Y)/(R-Y).

Many problems remain, such as setting the amplitude ratio of (G-Y)/(R-Y) to an appropriate value for each system.

A multi-system color television receiver is configured so that its internal signal processing format can be switched to suit each system. However, when switching the signal processing format, it is necessary to avoid large changes in the output signal level due to the switching. Furthermore, the more elements that can be used for processing signals of each type, the more the circuit will be simplified and the cost will be reduced.

[Purpose of the invention]

This invention focuses on the color demodulation means in particular, and when the demodulation axis shifts when the method of the color signal to be demodulated is switched, that is, the P
When transitioning from AL system to NTSC system processing format (
It is an object of the present invention to provide a color demodulation circuit that can correct the deviation of the G-Y axis and perform accurate color demodulation for color signals of multiple systems.

[Summary of the invention]

In order to achieve the above-mentioned object, the present invention, for example, as shown in FIGS. 7 and 8,
861. QB70~QB7,? .

Q876~QB7B, Q764. Q765゜Q767
A correction vector generating means such as ~Q769 is provided. [Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 5 shows the overall configuration of the color signal processing circuit section in the color television receiver of the present invention. 61 is an input terminal for a chroma signal including a burst signal, and the chroma signal input here is input to a variable gain amplifier 62. The chroma signal subjected to gain control in the variable gain amplifier 62 is input to a burst chroma signal separation circuit 63. The burst signal separated by the burst chroma signal separation circuit 63 is processed by the hue control circuit 81t.
The chroma signal is input to the color control circuit 64. Further, the burst signal separated by the burst/chroma signal separation circuit 63 is input to an automatic color control (ACC) detection circuit 71, where the amplitude is detected. A DC voltage obtained by amplitude detecting the burst signal is applied to the gain control terminal of the variable gain amplifier 62. Therefore, variable gain amplifier 62
The chroma signal output from the chroma signal is always controlled to a stable level.・Marst chroma signal separation circuit 63C, in order to separate the burst signal, dart pulse shaping circuit 7
Dart Zorus from 2 is used.

This signal C-) is phase-synchronized with the burst signal period, and, for example, the horizontal synchronizing signal is delayed and adjusted to a constant girth width before being output.

The chroma signal separated by the burst chroma signal separation circuit 63 is amplified by the color control circuit 64.

The gain of the color control circuit 64 is varied by adjusting the iZolium 65 by the user. The output chroma signal from the color control circuit 63 is sent to an IH delay device 66 having a delay time of one horizontal period;
Pulmatrix circuit 75 via coupling capacitor 67
is added to the delay input line 75m of the attenuator 68. It is applied to the direct input line 75b of the pulse matrix circuit 75 via the coupling capacitor 69.

- Regarding the specific operation of the Gurumatrix circuit 75,
This is detailed in FIG. In this chroma matrix circuit 75, when the system is processing a PAL television signal, the chroma signal IH (1
Matrix processing is performed on the IH delayed chroma signal delayed by a horizontal period and the delayed direct chroma signal. By this matrix processing, (B-Y)
The (R-Y) component is separated, and the components are input to a (B-Y) demodulator 76 and a (R-Y) demodulator 77, respectively. On the other hand, when the system is processing an NTSC television signal, the operation switch 74 is turned on and the IH delay chroma signal on the delay input line 75IL is passed to ground. Therefore, only the direct chroma signal is input to the flat matrix circuit 75. When the operation switch 74 is turned on, the internal signal path of the system switch circuit 75 is switched, and the output state of the system switch circuit 79 is also switched accordingly. (The specific configuration of the system switch circuit 79 is explained in detail in FIG. 6.)
When processing TSC television signals,
The pulse matrix circuit 75 separates the direct chroma signal into two transmission paths and inputs them to the (B-Y) demodulator 7 e and the (R-Y) demodulator 77, respectively. ij
A waveform shaping circuit 800 pulses are also added to the pulse matrix circuit 75 for outputting pulses synchronized with the horizontal synchronizing signal period. When this chroma signal is added, the normal matrix circuit 75 cuts off the chroma signal. The waveform shaping circuit 8o is, for example, a flyback/? Using the pv suwo, the dirt
Mother Rus is born. This dart pulse is also used as a timing pulse for a Frizzofrog circuit 86, which will be described later, to obtain a phase inversion operation. The signal output from the noyal matrix circuit 75' is (B-Y)
Demodulation processing is performed in a demodulator 76, a (RY) demodulator 77, and a (GY) demodulator 78. This (B-Y
) Demodulator 76, (R-Y) demodulator 77, and (G-Y) demodulator 78's specific configuration and operation will be described in detail in FIG.

On the other hand, the burst signal whose phase has been adjusted in the hue control circuit 81 is transmitted to a color killer detection circuit 83 (hereinafter referred to as a killer detection circuit) and an automatic phase control detection circuit 84.
(hereinafter referred to as APC detection circuit). When the hue control circuit 81 is adjusted, the adjustment yl?
The IJum 82 is operated by the user. In the killer detection circuit 83, phase detection is performed between the first strike signal and the subcarrier for killer detection, and a voltage corresponding to the phase difference is output as a killer detection voltage. In the APC detection circuit 84, phase detection is performed between the burst signal and the automatic phase control subcarrier, and a voltage corresponding to the phase difference is obtained as an oscillation frequency control voltage. The killer detection circuit 8 J and the APC detection circuit 84 perform a detection operation in synchronization with the burst signal, and the timing thereof is as follows.
zlPrus shaping circuit 72.

The killer voltage from the killer detection circuit 83 is input to the ident and killer circuit 85. This ident and killer circuit 85 is shown in FIG.

This is detailed in FIG. 1O. The ident and killer circuit 85 controls on/off of the chroma signal transmission of the color control circuit 64 and inversion/non-inversion of the flip-flop circuit 86 according to the level of the killer voltage. Furthermore, the ident and killer circuit 83 can also turn on and off the chroma signal transmission path of the norj matrix circuit 2''5 by its output. It is possible to determine whether the color broadcast reception state or the black and white broadcast reception state is received.Furthermore, when receiving a PAL television signal, it is possible to determine whether the inversion/non-inversion operation of the flip-flop circuit 86 is in the correct phase or in the wrong phase. It can be determined whether the free lag frog circuit 860 is inverted,
The non-inversion timing is determined by the dart/gurus output from the waveform shaping circuit 80, and can be inverted or non-inverted every horizontal period. Furthermore, the flip-flop circuit 86 is set to an inactive state or an active state by a switching signal from the system switch circuit 79. When an NTSC television signal is being processed, the operation of the flip-flop circuit 86 is stopped, and when a PAL television signal is being processed, the operation of the flip-frog circuit 86 is started.

The reference oscillation output from the voltage controlled oscillator 87 is introduced into the phase synthesizer 88, and the phase synthesizer M88 outputs, for example, four subcarriers depending on the purpose of use. This phase synthesizer 88 includes a (B-Y) demodulation subcarrier to be added to the (B-Y) demodulator 76 and a (R-Y) demodulation subcarrier to be added to the (R-Y) demodulator 77. t (
c-y) A correction subcarrier to be added to the demodulator 78 and a killer detection subcarrier to be added to the killer detection circuit 83 are generated. The correction subcarrier is used when the (G-) signal of an NTSC TV is being processed.
Y) Utilized in demodulator 78. Phase synthesizer 88
The operating mode is switched by the output of the system switch circuit 79, and can be switched between PAL mode reception and NTS mode.
When receiving the C method, the phase state of the (R-'Y) demodulation subcarrier is switched, and '! & (RY) The carrier wave for demodulation is 1 by the output of the flip-flop circuit 86.
The phase is inverted every horizontal period.

The specific configuration and operation of the phase synthesizer 88 will be described in detail in FIG.
Two reference oscillation outputs are input, and are used to generate various subcarriers. The voltage controlled oscillator 87
The oscillation frequency is controlled by the detection output from the C detection circuit 84, and is controlled so as to always obtain an oscillation output phase-synchronized with the burst signal.

(1) “Explanation No. 6 regarding the matrix circuit 75”
The figure shows 75 Lux matrix circuit. System switch circuit 79. The configuration of the operation switch 74 is specifically shown. The node matrix circuit 75 performs vector addition of a direct chroma signal and a delayed chroma signal during PAL reception.

It functions as a matrix circuit that performs subtraction, and functions as a direct chroma signal separation transmission line when receiving the NTSC system. The operation switch 74 is turned off when receiving the PAL system, and turned on when receiving the NTSC system. A negative horizontal blanking pulse (dart noise) is applied from the waveform shaping circuit 80 to the transistor Q839(7). This horizontal blanking pulse turns off the transistor Q839, and the noggle matrix circuit 75 has the function of blocking input signals during the horizontal blanking period. Even if the transistor Q839 (which means removing the burst signal) is on, if the transistor Q840 is turned on by the color killer signal, the noyral matrix circuit 75 has a function of cutting off the transmission path of the chroma signal.

FALSE (1)-I PAI, operation when receiving the system When receiving the PAL system, the operating switch 74 is turned off, thereby turning on the transistor Q8Z7°Q818. As a result, transistor Q817. The collector potential of Q818 drops.

Vy further than the collector potential of transistor Q818
The reduced voltage (potential drop due to diode connection) is applied to the emitter of transistor Q842, and this voltage is applied to transistor Q889°QII22. Added to Q821's pace. This results in transistor Q8
89. QFJ22°Q821 is turned off. (Transistor Q822゜Q821 is (R-
(Y), (B-Y) A transistor that functions to transmit chroma signals, but is turned off when receiving PAL system)
(1) The vector addition direct chroma signal in the -2 node matrix is added to the pace of transistor Q810, and the direct chroma signal added to the transistor 8100 pace is transmitted from the collector of transistor Q810 → resistor R87s → transistor Q820 → resistor R823. It passes through the path and is guided to the resistor R823. In this case, the direct chroma signal is transmitted through transistor Q820
The phase is inverted.

In addition, the direct chroma signal applied to the Transistoro 8100 pace is the emitter of transistor Q810 → resistor R816 → R817 → transistor Q813 → resistor R876 → transistor Q823 → resistor R882 → R
It also leads to 826.

The delayed chroma signal is then passed through transistor Q818. Q
This will be added to the 8170 pace. After this, the delayed chroma signal is transferred from the emitter of transistor Q817 to resistor 819.
→ R818 → Transistor Q814 → Resistor R877 → Transistor Q824 is led to the collector of this transistor Q824 through the path, and the emitter of transistor Q817 → Resistor R819 → R818 → Transistor Q814 → Resistor R878 → Transistor Q825
→ Guided through the path of resistor R823. As a result, the direct chroma signal and the signal obtained by inverting the delayed chroma signal are added at the connection point between the collector of the transistor Q824 and the resistor R823. That is, vector subtraction between the direct chroma signal and the delayed chroma signal is performed. Further, vector addition of the direct chroma signal and the delayed chroma signal is performed at the connection point between the resistor R826 and the resistor R883 connected to the collector of the transistor Q825.

The (B-Y) component of the result of the vector addition is added to the transistor Q8270 pace and the (B-Y) component of the result of the vector subtraction is added to the transistor Q8270 pace.
The RY) component is applied to the pace of transistor Q826.

(1) -3 Operation when receiving NTSC method When receiving NTSC method, IJ wax path 75 is
Performs amplification and separation processing of direct chroma signals. The operation switch 74 is turned on at this time. Therefore, the transistor Q818 that constitutes the system switch circuit 79
゜Q8170 pace potential becomes low and transistor Q8
18. Q883. Q817 is turned off.

Therefore, among the transistors QB1g and QIJ83+Q884°Q819 constituting the system switch circuit 79, the collector potential of the transistor Q818 becomes high, while the collector potential of the transistor Q819 becomes low.

As the collector potential of transistor Q818 becomes higher, the knee emitter potential of transistor Q842 also becomes higher, and this emitter potential becomes higher than that of transistor Q889. Transistor Q822° is added to the pace of Q821.

This causes transistor Q889. Q822. Q8
21 transitions from the off state to the on state. On the other hand, since the collector potential of transistor Q819 has become low, the emitter potential of transistor Q841 has also become low, and this emitter potential is the same as that of transistors Q823. Q824.
Q825 PACE is applied to transistor Q8200 PACE, turning these transistors off. As a result, during NTSC reception, the transistors Q825 and Q824 forming the transmission path for the delay chroma signal are turned off, and the delay chroma signal is cut off. Therefore, when receiving the NTSC system, the Tran Zosta Q810
Pace collector → resistor R875 → transistor Q8
21→transistor Q82 via the resistor R880 path
6 and also one pace emitter of transistor Q8101 → resistor RIll 16 → resistor R8l
7→transistor Q813→resistor R876→transistor Q822→resistor R881.

The signal applied to the pace of transistor Q827 is transferred from the emitter of transistor Q827 to capacitor C for DC cut.
802→transistor Q-83'20 It is input to the next stage (B-Y) demodulator 76 via the pace emitter path. Further, the signal applied to the pace of the transistor Q826 is input to the (RY) demodulator 77 at the next stage via the emitter of the transistor Q826→DC cut capacitor C801→the pace emitter path of the transistor Q831.

(1) The gain/guru matrix circuit 75 in the -4 nodal matrix circuit is used for PAL reception and for NTS
The gain is automatically switched depending on when receiving the C method. However, the output DC potential does not change in response to system switching. In other words, when receiving the PAL system, the vector addition of the direct chroma signal and the delayed chroma signal is
The vector subtraction is performed on the collector side of transistor Q825 and the vector subtraction is performed on the collector side of transistor Q824. Vector addition extracts the (B-Y) component, but the transistor Q that amplifies the direct chroma signal
For the transistor Q823, the resistor R825 serves as a load, and for the transistor Q825 that amplifies the delayed chroma signal, (resistor R825+R826) serves as a load.

On the other hand, if we look at vector subtraction, vector subtraction is (
Resistor R822 serves as a load for transistor Q820 that inverts the direct chroma signal, and resistors R822 and R824 serve as a load for transistor Q824 that amplifies the delayed chroma signal.
823 becomes the load.

Next, when receiving the NTSC system, transistor Q8
The load on transistor Q821 is resistors R825, R826, and the load on transistor Q821 is resistors R822, RIJ23. R8
It becomes 79.

As mentioned above, in response to PAL and NTSC reception, the (B-Y) component in the noyal matrix circuit,
Load switching for the (RY) component is obtained. By switching this load, the relative amplitude ratio (B-Y)/(R-Y) of the (B-Y) axis t (R-Y) axis component can be changed to PAL without changing the output DC potential. It can be set to 1 when receiving the NTSC method and 056 when receiving the NTSC method. In other words, it is possible to automatically switch and obtain an amplitude ratio appropriate for each method.

(1)-5. In the Gurumatrix circuit 75, P
In terms of AL method processing and NTSC method prescription processing, (
It operates to switch the amplitude ratio of B-Y)/(R-Y), but now it is a direct chroma signal.

The vectors of the delay chromatic language will be explained as α and β.

FIG. 11(a) shows the vector of the direct chroma signal when receiving the PAL system, and FIG. 11(b) shows the vector of the delayed chroma signal. (B-Y) component is the 11th
As shown in Figure (c), it can be derived as 2(B-Y), and the amplitude can be expressed as α(Il?, ?5)+β(tl?, 25). However, R825 is the value of the resistor R825 in FIG. Next, regarding the (RY) component,
It is derived by inverting the phase every horizontal period, and is shown in Fig. 11(d).
) is derived as -2(RY) or 2(RY). At this time, the amplitude is β(R122)−α(R
822) can be done without hail. However, Ft82
2 is the value of resistor R822 in FIG.

Next, when the system is switched to NTSC processing, only the direct chroma signal shown in FIG. 12 (-) is processed. The chroma signal applied to the (B-Y) demodulator consists of 2 (R-Y) components and 2C components, as shown in FIG. 12(b).
B7Y) Combination of components: Derived as a composite vector, and the amplitude in this case can be expressed as α(Ra25+R826). However, R825, R, 826 are resistors R82 in FIG.
5, R826 value. Also, the R4 signal applied to the (R-Y) demodulator is a composite vector of 3.56 (B-Y) and 3.56 (R-Y) components, as shown in Figure 12 (C). The amplitude in this case is −α
It can appear as (R1322+R823-'R879). However, R822゜R823, R87
9 is the value of the resistors R822, R823 and R879 in FIG.

(1) -6・Thirteenth modification of the matrix circuit 75
Diagram (a)? (b) are other embodiments of the knee matrix circuit, respectively.

To explain from the circuit of FIG. 13(-), 91 is a reference ground potential line, 92 is a constant current setting bias line, 9
3 is the pace bias line.

75b is the direct chroma signal input line.

75a is a delay chroma signal input line.

Furthermore, 94 is a switching signal input line from the system switch circuit, and 95 is supplied with a reference voltage.

During NTSC reception, the switching signal input line 94 is at a low level. For this reason, transistor Q, ? 1
, Q 3.5 , Q 36 , Q , ? 4 is off. Therefore, the direct chroma signal is
Custa Qll pace collector → Tran Zosta Q32
is led to the (RY) component output line 96 through the emitter-collector path. Also, the pace emitter of the transistor Qll → the resistor Ftll.

(B-
Y) component output line 97.

Next, when receiving the PAL system, the switching signal input line 94 becomes high level. For this reason, transistor Q35. Q
36. Q34 turns on and transistors Q31. Q33 is turned off. Therefore, the direct chroma signal is led out to the (R-Y) component output line 96 via the transistor Q11, the transistor Q31, and the resistor n3zf. It is led out to the (B-Y) component output line via RJ4. On the other hand, the delay chroma signal is distributed to the transistor Q36 side and Q35 side after passing through the transistor Q21 → resistor R21 → R22 → F run resistor Q22. ,Each(
'RY) component output line 96 and (B-Y) component output line 97 side. This makes it possible to obtain matrix processing during PAL processing.

The signal applied to transistor Q21 is F'(p)n, and the signal applied to transistor Q11 is F(p)n.
+ 1, the signal that appears on the output line () is F(p)n + F(p)n + 1= (α'(B-Y)
±jβ'(R-Y)10(α'(B-Y)gijβ'(R
-Y)1=2α'(B-Y) Similarly, the signal applied to the output line () is F(P)n
−F(+′)n + 1−±j2β(RY).

Next, the pulse matrix circuit shown in FIG. 13(b) will be explained. In FIG. 13(b), parts that are the same as those in FIG. NTS current source Il
It is configured to be turned off or on depending on C system or PAL system processing.

During NTSC processing, the constant current source Il is turned off, so only the direct chroma signal is sent to the transistor Q43.
The collector side of the transistor Q44 is led out to the collector side of the transistor Q44. During PAL processing, constant current source 1 is turned on, so that the delay chroma signal passes through the path from transistor Q41 to Q42, and then to transistor Q.
45. Q46 to enable matrix processing.

(2) (B-Y)p(R-Y), (G-Y) demodulator and phase synthesizer.

7 shows the (B-Y)y (R-Y), (G-Y) demodulators 76, 77, 78, and FIG. 8 shows the phase synthesizer 88.

(2) -1 (B-Y), (R-Y), (G-Y) demodulator (when receiving PAL system) Not derived from the emitter of transistor Q832 (B-
The Y) component is supplied to each pace of transistor QIJ55゜Q861 (D), and the (RY) component derived from the emitter of transistor Q831 is supplied to transistor Q8
Sarel feeds the pace of 56. (B-Y) In demodulator 76, transistor Q854. Q855. Q862゜Q
863. Q864. The QIJ65 constitutes a multiplication circuit, and the (B-Y) demodulation subcarrier (B-YCW) from the phase synthesizer 88 is added to the common pace of the transistors Qstyt and Q863.

The demodulated signal (B-Y) of the (B-Y) component is transmitted by the transistor Q862. It is led out through the common collector of Qlj64 and through the path from the pace emitter of transistor Q874 to resistor R866.

Further, the demodulated signal -(B-Y) of opposite polarity is transmitted to the transistor Q863. A resistor R868 for one matrix is led out from the common collector of Q865. On the other hand, in the (RY) demodulator 78, one transistor Q856. Q857. Q
866° Q867, QB6B, and Q869 also constitute a multiplication circuit, and the (RY) demodulation subcarrier (R-YCW) from the phase synthesis bag @88 is added to the common space of transistors Q867 and QB6B. . The demodulated signal (RY) of the (RY) component is transmitted by transistors Q867 and Q
The common collector of Q869→the emitter of transistor Q875→resistor R870 is led out. Also, the demodulated signal (R-Y) of opposite polarity is transmitted by the transistor Q8.
66, is led out from the common collector of QB6B to the matrix resistor R87. Therefore, the demodulated signal (B-Y)
The demodulated signal (
G-Y) is the base emitter of transistor Q876→
Resistance 87. ? is derived through the path of The demodulated signal obtained at transistor Q869 and the demodulated signal obtained at the collector of transistor Q866 whose load is resistor R868 are 180° different in phase, and
The demodulated signal obtained at the collector resistor R867 of 865,
The phase differs by 1806 from the demodulated signal obtained at the collector of transistor Q862. In other words, the demodulated signal (G-Y)
is obtained by vector synthesis of demodulated signal -(B-Y) and demodulated signal -(RY).

(2)-2 (R-Y), (B-Y), (G-Y) demodulator (when receiving NTSC system) (B-Y) demodulator 7g, (when receiving NTSC system)
(RY) The operation of the demodulator 77 is the same as when receiving the PAL system. However, when receiving the NTSC method,
Due to the operation of the system switch circuit 79, the collector potential of the transistor Q844 decreases, and the collector potential of the transistor Q844 decreases.
The collector potential of No. 3 becomes high. When the collector potential of the transistor Q843 decreases, the transistors Q859 and Q860 forming the (GY) demodulator 78 are turned off. As a result, the transistor Q 861 p Q 85 FJ
turns on, and the chroma signal from matrix circuit 75 is led out to the collector via the pace of transistor Q861. At this time, transistors QB5g, Q861 . Q
II70゜QII71 eQ872, G873 functions as a multiplication circuit, and the transistor Q II73 t
The common collector of Q871 has the multiplication output of the (G-Y) demodulation subcarrier (G-YCW) (actually for G-Y@ vector phase correction) and the (B-Y) component, that is, the correction A demodulated signal (G2-Y) is obtained. therefore,
When receiving the NTSC system, the demodulated signal (B-Y) p (R
-Y)# (G2-Y) IJ wax calculation is performed on the three signals, and the resulting signal is the normal demodulated signal (
G−Y).

(3) Description of the phase synthesizer 88 and demodulation axis FIG. 8 shows the phase synthesizer 88. The relationship between the phase synthesizer 88 and the demodulation axes of the (B-Y)*(m-Y)e(G-Y) demodulator 76, 77, and 78 is shown in FIG.
This will be explained with reference to FIG.

(3) The subcarrier necessary for the A-y axis color demodulation during -1 PAL system reception is generated by the phase synthesizer 88 using the burst signal obtained by the automatic phase control (APC) loop as a reference. The (B'-Y) demodulation subcarrier (B-YCW) for the (B-Y) axis generates the second reference oscillation signal (b) which is applied to the R-s of the transistor Q734 constituting the phase synthesizer 88. made using This second reference oscillation signal (b) is a signal created by delaying the phase of the first reference oscillation signal (-), and the first reference oscillation signal (,) is phase synchronized with the burst signal. This is the signal generated by the APC Luso including the voltage controlled oscillator 87. When the second reference oscillation signal (b) is applied to the pace of the transistor Q734, a signal (b) of the same phase is applied to the collector of the transistor Q735. This signal (b) is passed through transistor Q739 (B −
Y) Transistor Q863 derived from its collector as a demodulating subcarrier (B - YCW ) and shown in FIG.
, added to the common pace of G864.

Next, when we look at the subcarrier (R-YCW) of the (RY) axis, we see that this (RY) subcarrier for demodulation (R-ycw)
) is generated by the first phase synthesis circuit FI8a. The first phase synthesis circuit 81Jh includes a transistor Q,
742. Q743. , G744°G745. G746.
It is composed of G747 and the like. transistor Q7
The pace of transistor Q743 is a first reference oscillation signal (a), and the pace of transistor Q743 is a second reference oscillation signal (b).
) is applied. Transistor Q742. Q743 is
It has a differential amplifier circuit configuration, and the emitters are commonly connected.
Connected to the collector of transistor Q740 that constitutes a constant current source. Therefore, the collector of transistor Q742 has -(a-b)==ba-a,) transistor Q743
Signals (a-b) are applied to the collector of. The signal (ba) can be outputted to the collector side of the transistor Q745, and the signal (ab) can be outputted to the collector side of the transistor Q747 using the resistor 8729 as a load. Here, which of the signals (ba-a) and #signals (a-b) is derived depends on the transistor Q745. It is determined by the output state from flip-flop circuit 86 which is added to the common pace of Q746. That is, when the level of the output (P4) of the inverted and non-inverted outputs (P4) and (P5) of the flip-flop circuit 860 is at a high level, = (a-b) = b-a is generated through the transistor Q745. Resistance R
729 and when the output (P4) is at a low level, a-b is connected to resistor R729 via transistor Q747.
is derived. As explained in FIG. 5, the state of the flip-flop circuit 46 is inverted every horizontal period, so when receiving the PAL system, the signals (b-a), (
a-b) are output alternately every horizontal period. In other words,
The phase of the (RY) demodulation subcarrier (R-YCW) is inverted every horizontal period, and the demodulation of the (RY) component is performed. (RY) Demodulation subcarrier (R-YCW
) are the transistors Q867 and QB6 shown in FIG.
Added to 1J pace.

When receiving the PAL method, regarding the subcarrier (B
-Y) axis and (RY) 111 with a phase difference of 90°.

During PAL reception, the transistor Q818 in the system switch circuit 79 shown in FIG.
The black level is high and the collector potential is low. Then, the emitter potential of transistor Q842 also becomes low, and therefore the collector potential of transistor Q844 becomes high.
The collector potential of transistor Q843 is high.

Transistor Q84 of the above system switch circuit 79
The collector potential of transistors Q751 . It can also be added to the Q7550 pace. Therefore, during PAL reception, transistors Q751 . The base potential of Q7550 is low, and transistors Q751 and Q755 are turned off. Therefore, when transistor Q755 is off, its collector is cut off from resistor R729, so only signals (a-b) and (ba) are derived as subcarriers.

Next, the (G-Y) axis during PAL reception will be explained. During PAL reception, the transistor Q818 that constitutes the system switch circuit 79 shown in FIG.
．． Q819. QFI41.

Q842. Q843. Depending on the state of Q844, the transistor Q861 of the (G-Y) demodulator shown in FIG.
QB5B is off. Therefore, transistor Q
Chroma signal obtained through the emitter of 832 (B-Y
) component is blocked by Q861. As a result,
In the (G-Y) demodulator, the (G-Y) demodulation subcarrier (G-YCW) and the (B-Y) component are not multiplied. However, in this case, transistor Q8
A predetermined DC voltage is applied to the collector of 73. P
At the time of AL system reception, as explained in FIG. ) A demodulated signal is obtained. In the one-way sum synthesizer 88, the signal (
Direct) (+;) are transistors Q764, Q7650
The mixed signal is output as the (G-Y) demodulation subcarrier (G-YCW), but this does not affect the demodulation effect and the capacitance C80 in Fig. 7
Bypassed through 5.

(3) -2 Demodulation axis when receiving the NTSC method When receiving the NTSC method, the Sotrix circuit 75 used when receiving the PAL method is shared, and functions as a chroma signal transmission path as well as a separation path. . NTSC
At the time of system reception, the operation of the free-lag flop circuit 86 is stopped by the system switch circuit 79.

When receiving the NTSC system, the demodulation phase of the demodulation axis is P.
Unlike when receiving AL system, (B-η axis and (R-
The relative phase difference of the Y) axis is set to approximately 105°. Also, regarding the relative field of view ratio of demodulated signals, NTSC and P
This is different from the AL system. This is PAL system and NTSC
This is because the setting of the white color temperature is different between the two. This system is switched to satisfy such conditions. ``During NTSC system reception, the state of each transistor composing the system switch circuit 79 is P.
The state is reversed from the state at the time of AL method reception. For this reason,.

In the phase synthesizer 88, the transistor Q741
, Q751, and Q755 turn on, and transistor Q76
0 turns off. When transistor Q741 is turned on, transistors Q742 and Q743 are turned off. Next, when the transistor Q75 is turned on, the transistor Q75
2°Q753 is turned off. The (B-Y) demodulation subcarrier (B-YCW) during NTSC reception is P
It is extracted in the same way as when receiving the AL system.

On the other hand, transistor Q749. Q750゜Q751
tQ 752, tQ 753, tQ 755, etc. form a second phase synthesis circuit 88b. Since the resistor R733 is connected to the pace of the transistor Q750, the reference oscillation signal (,) is kl・a (0<kl
<1), and the absolute value of the transistor Q7 is varied.
Apply 50 paces.

Also, the resistor R731 is also connected to the transistor 9749.
is connected, the reference oscillation signal (b) is varied in its absolute value to 2·b and is added to the pace of transistor Q749. As a result, the vector signal kg b -kla is applied to the emitter of transistor Q755.

When receiving the NTSC system, the operation of the flip-flop circuit 86 is stopped and the output is output (P4).

(P5) is at a low level, Tran Zosta Q756. Q752. Q746. Q745゜Q754
, Q75,? , Q 747 , Q 74
4 is off. Therefore, on the collector side of transistor Q755, a signal (1a on k2a-) having a phase set to about 105' with respect to the (B-Y) axis is (G-
Y) Derived as a demodulation subcarrier (R-y complex). Since the phase adjustment is based on vector synthesis, it is performed by selecting the values of the resistors R7, 92, and R731. The (G-Y) demodulation subcarrier (G-YCW) extracted in this way is added to the common space of transistors Q867 and Q86B shown in FIG.

In this way, the subcarrier (R-YCW) of the R-η axis is
It is generated with a phase difference of 1056 with respect to the (B-Y) axis. Furthermore, in the (RY) demodulator 77, (R
-Y) component in the pulse matrix circuit 79.
Since the amplitude for the B-Y) component is adjusted and input, demodulation compatible with the NTSC system is performed.

Next, the (G-Y) axis during NTSC reception will be explained. Even when receiving the NTSC method, (G - Y)
The axis needs to have the same phase as when receiving the PAL system.

However, the system changes from PAL processing state to NTSC
In the IJ wax path 75, the gain for the (RY) component is P
It is larger during NTSC system processing than during AL system processing. Therefore, if the demodulated signal (B
Since the vector distribution of -Y)t(RY) is different from that during PAL processing, the CG -y) axis cannot be obtained at the desired phase. Therefore, when receiving the NTSC system, J(G-y
) It is necessary to correct the (G-η axis phase) of the signal.

The (G-Y) axis correction means when receiving the NTSC system will be explained. The (G-Y) demodulated signal is demodulated by performing matrix processing of the (B-Y) demodulated signal and the (R-Y) demodulated signal when receiving the PAL system, but the NT
During SC method processing, (B-Y) demodulated signal, (R-Y)
In addition to the demodulated signal, demodulation processing is performed using the detected output of the (B-Y) component and the (G-Y) demodulation subcarrier (G-YCW). That is, in the phase synthesizer 88, transistors Q 764 p Q 765 t Q 767
tQ 768, tQ769, etc. constitute a third phase synthesis circuit 88c. Since the resistor R737 is connected to the pace of the transistor Q764, the reference oscillation signal (-) is attenuated to llx.''(0<ll<1) and applied to the pace of the transistor Q764.

Also, the resistor R73 is connected to the transistor Q765.
9 is connected, the reference oscillation signal (b) is 12
・b(o<12<1) damping salete, transistor riff 6
Applied to 50 paces. Therefore, transistor Q76
A vector signal of 12・b-lt・a is obtained at the collector of 4, and this signal is used as a (G-Y) demodulation subcarrier (G-YCW) to generate a correction vector. -Y) Transistor Q872 of demodulator 78. Q8
Added to 71 common paces. By this, (G-
In the Y) demodulator 78, the chroma signal added to the transistor Q8610 pace is multiplied by the (G-Y) demodulation subcarrier (G-YCW), and the resulting vector signal is the correction vector. As a signal,
It becomes one of the matrix elements. Through this operation, when receiving the NTSC system, it is possible to have the correct demodulation axis (
GY) demodulated signal is obtained.

That is, since the matrix circuit adapted for PAL processing cannot obtain the correct (G - Y) 111, the phase synthesis circuit 88c uses the correction subcarrier (
G −YCW ) is generated, and as shown in FIG. 14, (
b) - Y) A vector (G-Y) UD is created for correction so that the axis is at the position of the solid line. As a result, a correct (G-Y) axis demodulated output can be obtained.

(3) -3 Phase synthesis stabilization in the second phase synthesis circuit 88b and third phase synthesis circuit 88c.

For the phase synthesis circuit, the reference oscillation signal (,) (b)
Phase synthesis is performed, and the synthesized output is the same as that of the transistor. It is necessary to avoid being influenced by others.

Now transistor Q749. The countermeasures taken for the phase synthesis circuit made up of Q750 will be explained.

Now, if the resistor R733 were not included in this phase synthesis circuit, the following problem would occur.

FIG. 15(a) shows a simplified phase synthesis circuit in which the resistor R731 is removed, but with this configuration, the phase synthesis output is unstable.

In FIG. 15(,), the reference signal (,) is inputted to the pace terminal of the transistor Q750 via the path from the R emitter of the transistor Q to the resistor R732.
) is input to transistor Q749 (7) PACE via the PACE emitter of transistor Q2.

The value of resistor R732 is 1 Ω, and the value of resistor R733 is 5 Ω.
shall be. FIG. 15(b) is an equivalent circuit when viewed from the reference signal (,), and FIG. 15(c) is an equivalent circuit when viewed from the reference signal (b). Using this circuit, transistor Q749. Let's find the pace input voltage of Q750.

T 1 ``bit'''T' s '' O-045K transistor Q
750 pace input vlna ij: transistor Q7
49's base human power vInb bar nb=b. When hfe is changed to 50, 100, and 300, the input vectors are 0.733a, respectively.

0.792a, 0.8182, and the output color subcarrier composite vector C is amplified under the resistance-divided Ka, and its phase error ΔQ changes by about 7°. That is, the composite vector 6 as shown in FIG. 15(d)
, ,C2, will be affected by hf, as in C,. When the subcarrier fluctuates in this way, accurate color demodulation cannot be obtained.

Also, when using the phase synthesis output in a killer detection circuit,
Color killer operation may exceed malfunction.

In order to prevent the above-mentioned phase fluctuation, in the system of the present invention, a resistor R731 is further provided as shown in FIG.
It is designed to be less susceptible to f@ and to obtain a stable phase synthesis output.

That is, the simplified circuit configuration in this case is shown in FIG.
), and its equivalent circuit is shown in Figure 16(b).
It becomes as shown in (,). From this circuit, the pace input voltage of transistors Q749 and Q750 can be found as follows: 〇 Resistor R7, JJ = 1, Ω, resistor R7, V, ? = Ω to 5.

Resistor R7,? Let J=800Ω.

The pace input vlna of transistor Q750 becomes, and the pace input vInb of transistor Q749 becomes. ht
The input vector of 1 combination with e changed to 50, 100, and 300 is 0.744, o, s96+;

Q, 7942, o, c+s3+;, o, sxsλ, 0
．． 981, etc., and the output phase composite vector d is differentially amplified by the resistor-divided Ka and the input, and the phase error thereof is within about 1°. That is, as shown in FIG. 16(d), the phase composite vector e has a stable phase almost unaffected by Kfe.

Therefore, it can be used for accurate color demodulation and phase detection operations.

(4) Color killer detection and color killer operation In the phase synthesizer 88, a subcarrier for color killer detection (K11ler -C%V) is also generated. That is,
This subcarrier for color killer detection (Kth 1er -cw
) is derived from the collector side of the transistor Q762°Q756 and is input to the killer detection circuit 83.

(4) -1 Color killer operation when receiving the NTSC method When receiving the NTSC method, the transistor Q755 in the phase synthesizer 88 is turned on, and the transistor Q
756 *Q 754 is off. Therefore, resistor R734 acts as a load for transistor Q762. The collector of transistor Q762 has a signal (
The vector component b) is sent to the killer detection circuit 83 as a color killer detection subcarrier (K11ler −
CW).

FIG. 9 shows the killer detection circuit 83. The ident and killer circuit 85 is shown. Killer detection subcarrier (K11ler
-cW) is added to the pace of F transistors Q633°Q634. The killer detection subcarrier (K11ler - CW) applied to the transistor Q633 and the burst signal applied to the pace of the transistor Q630 are multiplied by 1 by these transistors, and their output is transferred to the transistor Q634. The potential of resistor R629 is controlled through the path of pace emitter of resistor R627 → pace collector of transistor Q64.

This resistor R629 is connected to the killer filter, and the filter voltage is the same as that of the ident and killer circuit 8.
It is added to the pace of transistor Q663 which constitutes 5.

Now, when the Haas signal is present and the voltage of the killer filter increases, the transistor Q663 forming the ident and killer circuit 85 is turned on. (This is an explanation for NTSC system processing, so the ident operation itself will be explained later.) When the transistor Q663 turns on, the transistor Q659. Q660 current increases,
Since the current in transistors Q65FI and Q661 decreases, transistors Q665. The current in Q666 decreases. In this way, during NTSC processing, when a burst signal is detected, the output of transistor Q665 is
It is added to the transistor Q840 of the pulse matrix circuit 75 explained in the figure to turn it off. When the transistor Q840 is off, the nominal matrix circuit 75 functions as a transmission path and separation path for NTSC chroma signals.

On the contrary, the burst signal is not detected in the killer detection circuit 83, and the resistance R in the killer detection circuit 33
When the terminal voltage of 629 decreases, the terminal voltage of the killer filter also decreases. Therefore, the voltage obtained by subtracting the base-emitter voltage VF of trans-cis pQ 663 from the terminal voltage of the killer filter is the voltage obtained by subtracting the base-emitter voltage VF of transistor Q660. Q65
9, but in this case transistors Q660. Q659 turns off. For this reason, transistor Q661. The collector current of Q658 increases, and accordingly, the collector current of transistor Q666゜Q665 also increases.@When the collector current of transistor 665 increases, the pace potential of transistor Q840 in the pulse matrix circuit 75 increases, This transistor Q840 turns on. This transistor Q
When 840 is turned on, it is NTSC system.

Regardless of the PAL system processing, the transistor Q810. of FIG. Q813. Q814. All Q817 are turned off and a color killer operation is performed.

In this way, all the chroma signal transmission paths of the noggle matrix circuit 75 can be cut off by the collector output of the transistor Q665. It is also supplied to a switch circuit (not shown) that turns the output on and off, and also cuts off the output of the pantono 4-sphere filter itself, thereby inhibiting the color killer operation.
It can be done heavily.

FIG. 1.0 shows the flip-flow 21 circuit 86.

During NTSC reception, the collector potential of the transistor Q844 of the system switch circuit 79 is high, so that the collector potential of the transistor Q1145 in FIG.
．． Q84σ, Q847°Q667 are on. Therefore, the switch composed of transistors Q66B and Q669 is turned on during NTSC reception, and therefore transistor Q670 is turned off. transistor Q67
0 is turned off, no energizing voltage is applied to the flip-flop circuit 86, and the operation stops. Therefore, the outputs (P4) and (P5) of the flip-flop circuit 86 are both at a low level during NTSC processing.

(4) -2 Color killer operation and identification operation during PAL system reception During PAL system processing, the color killer detection subcarrier (K11ler-CW) output from the phase synthesizer 88
) is phase-inverted every horizontal period and input to the killer detection circuit 83. In the PAL system, this is
The burst signal and the phase of the (RY) axis are reflected every horizontal period, and the subcarrier (K
This is to synchronize the iller-CW). PAL
During system processing, the collector potential of transistor Q843 of system switch circuit 79 shown in FIG. 6 is low. Therefore, in the phase synthesis circuit 88 shown in FIG. 8, transistors Q751 and Q755 are turned off. For this reason, transistor Q752. Q753. Q75
4. Q756 can be on, but transistor Q
753°Q754 and a transistor Q752°Q
Which one of the set of 756 is turned on is determined by the state of the output (P4) (P5) of the flip-flop circuit 86. That is, the output of the flip-flop circuit 86 (
P4) is added to the pace of transistor Q 752 t Q 756 and the output (P5) is applied to transistor Q7
53° has been added to the pace of Q754. Now the output (
When P4) is at high level and the output (P5) is at low level, the collector of transistor Q750 → transistor Q
Through the emitter collector of 756, k2 b −kl
The signal of a is the subcarrier for killer detection (K11ler-C
When the output (P5) is at a high level, the signal 2b is transmitted to kla- from the collector of transistor Q749 to the emitter collector of transistor Q754 as a subcarrier for killer detection. (K11ler −CW ). In other words, the output (P4) of the flip-flop circuit 86
(P5), the subcarrier (Killer −
C'w) is (kllL- to 2b) y (kllL
2b) is phase-inverted and derived. Also, P
During AL system reception, the collector potential of transistor Q844 in system switch circuit 79 is high, so transistor Q760 in phase synthesizer 88 is turned on, and transistor Q75B is turned on.

Q759 is off. Therefore, transistor Q7
62 is also off, and resistor R734 is connected to transistor Q
756. It acts as a load on Q752 alternately every horizontal period.

The color killer detection subcarrier (K
i l er −CW ) is the transistor Q 63 , ? of the killer detection circuit 83 shown in FIG. .

Added to Q634 common pace. During PAL reception, the burst signal input to the color killer detection circuit 83 has a phase change of ± for each horizontal period with respect to the -(B-Y) axis.
Take a 40° photo and enter it.

On the other hand, in the flip-flop circuit 86 shown in FIG. 10, the transistor Q84 of the system switch circuit 7g
Since the collector potential of transistors Q845°Q846. Q847. Q667 is turned off, and transistors Q668 . Q669
Also turns off. Therefore, the transistor Q670 is turned on, and an energizing voltage is applied to the flip-flop circuit 86, making it in an operating state. i! Also, is the pace of transistor Q677 of this flip-flop circuit 86 synchronized with the horizontal synchronizing signal? -) pulse is applied, which inverts the state of the outputs (P4) (P5) every horizontal period.

In the killer detection circuit 83 shown in FIG. 9, as described above, the killer detection subcarrier (K111er-C
A multiplication operation is performed by the burst signal whose phase swings every horizontal period. Therefore, the output obtained from the killer detection circuit 83 during PAL processing includes information on whether or not to perform the color killer operation, as well as information on whether the inverted and non-inverted phases of the Furi and Zoff flop circuits 86 are the correct phases. It often includes information as to whether or not it is true.

Now, in the color killer detection circuit 83, transistor Q633. There is a correct relationship between the phase inversion of the killer detection subcarrier (K11ler -CW) added to the Q6340 pace and the swing (±40' swing) of the Nononst signal, that is, the subcarrier (K11l@r -c' W)
and (RY) components are in phase, transistor Q6
34. The current flowing through Q641 increases. When the current of the transistor Q641 increases, the terminal voltage of the resistor R629 increases, and the terminal voltage of the killer filter also increases. As a result, the emitter current of the transistor Q6'''63 of the ident and killer circuit 85 increases, and one transistor Q660 increases. When Q659 is turned on, the transistor Q66 is turned on.
1. Q658 turns off, and along with this, Tran Zosta Q666°Q665 turns off. Therefore, from the collector of transistor Q666, flip-flop circuit 8
No current is supplied to the emitter of transistor Q675 constituting transistor Q6. This means that the flip-flop circuit 8
This means that the fritzno flop circuit 86 continues its current operation without any control over the inverting or non-inverting operation of the circuit 6.

That is, when the subcarrier (K11ler - CW) and the (RY) component of the burst signal are in phase, the state of the flip-flop circuit 86 is not controlled. During PAL reception, the (R-Y) demodulation subcarrier (R-YCW) obtained from the second phase synthesis circuit IJ8b in FIG.
is inverted in phase by the outputs (P5) (P4) of the t flip-flop circuit 86 every horizontal period.

Furthermore, as mentioned above, the flip-flop circuit 86
is operating in the correct phase, transistors Q661 and Q658 are turned off as described above, and therefore transistors Q666 and Q66'5 are turned off.

When transistor Q665 is turned off, transistor Q
The collector output of 665 is the Noyal matrix circuit 75.
transistor Q840 remains off. Therefore, the noyalmatrix circuit 75 also operates normally without being subjected to a killer operation. During PAL reception, the armature matrices circuit 75 performs addition and subtraction processing on the chroma signals to derive the (RY) and (BY) components, as described above.

Next, during PAL reception, the phase inversion situation of the killer detection subcarrier (Kl 11sr -CW) and the phase inversion situation of the (RY) component of the burst signal are in opposite phases, and are different from - I will explain the case.

Killer detection subcarrier (K11ler-CW),
When the phase state with the (RY) component of the burst signal is in an anti-phase relationship, the detected voltage becomes low in the killer detection circuit 83 shown in Figure @9.

That is, the terminal voltage of resistor R629 becomes low, and the terminal voltage of the killer filter becomes low. Therefore, the emitter potential of transistor Q663 of ident and killer circuit 85 becomes low, and transistor Q660. Q659 turns off and transistors Q661. Q658 turns on.

Transistor Q661. When Q658 is turned on, transistors Q66.6. Q665 is also turned on. When transistor Q666 is turned on, its collector current is supplied to the emitter of transistor Q675 of flip-flop circuit 86, that is, to the base side of transistor Q674, thereby inverting the phase of flip-flop circuit 860.

That is, the transistor Q674 in the frizz-frozzo circuit 85 becomes active regardless of whether or not there is a current flowing through the transistor Q675. In this state, Q is lowered by vr4 from the terminal voltage of the killer filter.
This continues until the base voltage of 660 becomes higher than the voltage vL - vr, which is further lowered by vr than the psychic voltage (here, vL) predetermined by the internal bias.

On the other hand, the phase of the killer detection subcarrier (K11ler-CW) supplied to the killer detection circuit 83 is set such that the (R-Y) axis component of the burst signal is large when it is positive and small when it is negative. Y) is set near the axis and connected from the killer detection circuit 83 to the flip-flop circuit 8.
The phase of the killer detection subcarrier (K11ler -CW) when the flip-flop circuit 86 enters the stop mode due to the identification signal added to 6 is (R-Y).
The axis component is set to be in the positive direction.

Therefore, from the moment the flip-flop circuit 86 stops, the killer detection output in the killer detection circuit 83 generates a large positive output and a small negative output, and as a result, the killer filter output voltage Vo increases. . This filter output voltage Vo is compared to the above vL if Vo''> vL
At the moment when ident and killer circuit 85 transistor q660. CJ661 is inverted, thereby
The transistor Q666 is turned off, the pace voltage of the transistor Q674 of the flip-flop circuit 86 is controlled by the transistor Q677, and the flip-flop circuit 86 starts inverting and non-inverting operations from the next horizontal synchronization/mars. At this time, if the (R-Y) component of the input burst signal and the subcarrier for killer detection (Kth 1er - cw) have a correct phase relationship, the killer detection voltage further increases, and the transistor Q659. Q65
8's killer controller and controller are inverted, so transistor Q665 is turned off, the color killer state is released, the color reception mode is entered, and the correct color appears on the screen.

Next, as described above, if we go back to the point in time when vo>vL and the flip-flop circuit 86 starts inverting and non-inverting operations, we find that (RY) of the input burst signal
component and subcarrier for killer detection (K11ler-fr)
It is not always the case that the phase relationship will be correct, and there is a possibility that the phase difference will be 180°. At this time, the killer detection output starts to fall again from vo=■L, and after several horizontal periods, the killer detection output returns to the ident signal and the transistor Q661 as a regulator.
．． Q660 is inverted, thereby causing transistor Q6
66 turns on, forcing the transistor Q6740 of flip-flop circuit 86 to a high level, causing flip-flop circuit 86 to stop operating. As a result,
As before, once again the terminal voltage v of the killer filter
o begins to rise toward vL, and v. ': 2vL, whether vo further rises or falls again is determined depending on the phase relationship between the (RY) component of the burst signal and the subcarrier (K11ler - CW). In reality, when the flip-flop circuit 86 is released from the stopped state, it is difficult to determine whether the phase relationship between the (RY) component of the burst signal and the subcarrier (Killer-CW) is correct or incorrect. , is statistically estimated to be 50, and the probability that the flip-flop circuit 86 is always released in an erroneous state decreases in inverse proportion to the number of repetitions, so that a correct color reception state can be obtained within a finite time.

As mentioned above, if the phase relationship between the (RY) component of the burst signal and the subcarrier (K11ler-CW) is wrong, the identity con/4 rule by the transistors Q661 and Q660 in the identity and killer circuit 85 The flip-flop circuit 86
It is used to temporarily stop and then start again.

Furthermore, in the ident and killer circuit 85, transistor Q659. A killer comparator is also configured by Q658, and a killer voltage can also be output via the collector of transistor Q665.

Here, the state reversal operations of the ident controller and killer circuit 85 shown in FIG. 10 are not performed at the same timing, but are set at different operation levels. That is, the transistor 6640 pace that supplies the pace current of the transistor Q66) is connected to the pace collector of the transistor Q645 that constitutes the bias circuit of the killer detection section. On the other hand, the pace of transistor Q662 that supplies the pace current of transistor Q658 is
Connected to 46 pace collectors.

As a result, when receiving the PAL system, the subcarrier (Kl
11er -CW) and the burst signal (R-'Y
) component is out of phase, the killer detection voltage becomes a low voltage (voltage lower than the set voltage vL), the flip-flop circuit 86 stops (starts operating as the killer detection voltage rises), and the color Get killer action.

Also, when receiving a PAL system, if a burst signal is not detected, color killer operation is obtained first, and
The killer detection voltage V at that time is VL < Vo < Vu
It is. Therefore, in this case, the flip-flop circuit 85
operation will continue. Next, the burst signal (R-Y
) component and the subcarrier (Killer-CW) have a correct phase relationship, a high voltage 7 is used as the killer detection voltage.
8 or more is obtained, and both transistors Q665 and Q666 are off.

That is, as shown in FIG. 17, the detection output is V.

If it is above, the color killer operation and the operation stop of the flip-flop circuit cannot be obtained, and the detection output vo is v)I≧v
If o≧vL, only color killer operation is obtained.

Next, when vo<vL, the color killer operation and flip-flop circuit control are performed.

〔Effect of the invention〕

As mentioned above, the present invention particularly applies to FIG.

As with demodulation of the (G-Y) axis shown in FIG. 8, it is possible to provide a color demodulation circuit that can correct even if the demodulation axis obtained by the matrix shifts due to system switching.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a color signal processing circuit for NTSC system, Figure 2 is a block diagram showing a color signal processing circuit for PAL system, and Figure 3 is a color signal processing circuit for both PAL and NTSC systems. 4(a) is a circuit diagram showing the color demodulation circuit of the circuit in FIG. 3, FIG. 4(b) (C) is a block diagram showing the operation of the circuit in FIG. 5 is a block diagram showing an embodiment of the present invention. FIG. 6 is a circuit diagram specifically showing the node matrix circuit and system switch circuit of FIG. 5. Figure 7 is a circuit diagram specifically showing the demodulator in Figure 5. Figure 8 is a circuit diagram specifically showing the phase synthesizer in Figure 5. Figure 9 is a circuit diagram specifically showing the phase synthesizer in Figure 5. Figure 10 is a circuit diagram specifically showing the killer circuit; Figure 10 is a circuit diagram concretely showing the flip-flop circuit, ID, and killer circuit in Figure 5; Figures 11 and 2 are diagrams of the matrix circuit. A vector diagram shown to explain the operation? Irj13 diagram (,)
(b) is a circuit diagram showing another embodiment of the flat matrix circuit, and FIG. 14 is a circuit diagram (G-
Vector diagram shown to explain Y) axis demodulation operation, Figure 15 (a) is a basic circuit diagram of a phase synthesizer, Figure 15
Figures (b) and (c) are diagrams showing equivalent circuits of the circuit in Figure 15 (,), Figure 15 (d) is an explanatory diagram shown to explain the phase synthesis operation of the circuit in Figure 15 (,), Figure 16 (,) is a basic circuit diagram of the telephonic phase synthesizer used in the device shown in Figure 5. Figures 16 (b) and (c) are equivalent circuit diagrams of the circuit shown in Figure 16 (,). Figure (d) is an explanatory diagram shown to explain the phase synthesis operation of the circuit in the same figure (,), and Figure 17 is an explanatory diagram shown to explain the operation of the ident and killer circuits shown in Figures 5 and 9. FIG. 2 is an explanatory diagram of the operation shown in FIG. 66...IH delay device, 75...Reyall matrix circuit, 76-78...Demodulator, 79...System switch circuit, 83...Killer detection circuit, 85...Ident and killer path , 86...Flip-flop circuit, 87...Voltage controlled oscillator, 88... Phase synthesizer. Applicant's representative Patent attorney Takeshi Suzue No. 11 @ Figure 12 Figure 14 Figure 15 (a) Figure 15 (b) Figure 15 (C)

Claims (1)

[Scope of Claims] A first color demodulator that performs a color demodulation operation between a first color subcarrier having a first phase and a color signal, and a second color subcarrier having a second phase different from the first color subcarrier. a second color demodulator that demodulates the color signal with a second color subcarrier having Color code demodulation characterized by comprising: a matrix circuit section that generates a color demodulation signal for a demodulation axis; and a matrix circuit section that generates an addition vector signal for the output signal of the matrix circuit section, and the third demodulation axis.忰噌.