JPS58213564A - Encoding system of picture having multilevel gradation - Google Patents

Abstract

PURPOSE:To improve the compression ratio against facsimile signal having multilevel gradations as dither pictures have, by encoding an altered block of the address of the starting block with a code indicating the block value and the value of run length. CONSTITUTION:A comparator 32 judges whether the absolute value of the content of a counter 22 is within , for example, ''3'' or not, and outputs ''1'' when the absolute value is within ''3'' or ''0'' when the value is outside the range. When the signal from P3 is ''1'' and that from the comparator 32 is ''1'', the gate 62 is opened and the content of the counter 22 is encoded by a vertical mode encoding circuit 42. On the other hand, a counter 21 is increased one by one from the time when an address controlling circuit 6 sets a0 and stops the countine when it receives an ''1'' signal from P11. A gate 61 is the one which is opened when the output of the comparator 32 is ''0'' or the signal of P5 from a coincidence circuit 8 is ''0''. Block values passed through the gate 61 are inputted into a horizontal mode encoding circuit 41 and encoded.

Description

[Detailed description of the invention] The original F! Ati, relates to an effective encoding method for efficiently transmitting or storing facsimile signals having multiple levels of gradation.

A systematic dithering method is one method for expressing an image having multiple levels of gradation, such as a photograph, in a binary manner so that the human eye can see shading. This method expresses the degree of shading by changing the ratio of the number of black and white pixels, and the principle will be explained with reference to FIG. In the figure, (a) shows the pixel level of each pixel PE of the input image, (b) shows the threshold value for each pixel, and (C) shows the binary display image. According to this method of systematic dithering.

For example, if the input image has 16 levels of gradation, the first
As shown by the thick line in Figure (b), 16 types of threshold values from 0 to 15 are distributed in a 4x4 matrix according to the rules to form a dither matrix DM, and this basic dither matrix is divided vertically and horizontally. are repeatedly arranged to determine a threshold value for all pixels of the input image. If the threshold value is a dog, the pixel is completely black (signal 11"), otherwise it is white (signal "0#").
) is used to display the sini value. For example, in the input image of Fig. 1(a), the pixel IC (Q) in the 2nd row and 1st column is the level cuff of this pixel, and its threshold is 12 in Fig. 1(b), so the pixel is black. In other words, the signal becomes "1#". The binary display image obtained by this method is called a dip image. The arrangement of the threshold values in the dither matrix can be based on various models such as the Bayer model and the spiral model. It is a regular arrangement according to .

On the other hand, as a typical example of a binary facsimile signal encoding system, Modified Read is standardized by the Consultative Committee on International Telegraph and Telephone (CCITT).
d: MR) method. This method uses information changing pixels (
A pixel that changes from white to black or from black to white is hereinafter referred to as a "changed pixel." ), the relative address from the changed pixel on the same scanning line that appeared before the changed pixel to be encoded or the changed pixel on the previous scanning line is encoded. Therefore, this method has a high compression rate for binary facsimile signals that are not expressed in gradations, but when a dithered image is encoded using this method, it is Since there are a considerable number of changing pixels, a high compression rate cannot be expected as is.1 The present invention provides an encoding method that can expect a high compression rate for facsimile signals having multi-rail gradations such as dithered images. It is something.

The present invention will be explained below.

First, the present invention will be explained in detail. When an image having multiple levels of gradation is binarized using, for example, a 4×4 dither matrix, as can be seen from FIG. 1(b), periodicity of the threshold value occurs every four VC pixels.

The present invention focuses on the periodicity of this threshold value, and sequentially collects 4 pixels on each scanning line and creates 2 new pixels for each group.
When considered as one block with a 4-value signal, changes in block values are not as similar to changes in pixel values because there are almost no level changes when looking at the image locally and the threshold has periodicity as described above. shi also decreases considerably. Therefore, if a row of blocks in the scanning line direction is called a block row, and a block that has a block value different from the previous block on the four-block row is called a changed block, the address of the changed block and the block of the changed block. By encoding the values, the compression rate increases as in the case where a binary facsimile signal without gradation representation is encoded using the MR method.

The encoding method of the present invention will be explained in detail with reference to FIGS. 2 to 5. In these figures, each small frame indicates a block newly created by combining binary pixels, and the values within the small frame indicate block values.

Here, it is assumed that each block can take values of 16 levels from 0 to 15. To explain the encoding line and reference line in advance, the encoding line is the line that is being encoded, and the reference line is the line that is already encoded that is useful for encoding the encoding line. This line is selected based on the vertical periodicity of the threshold value in the dither matrix, and is usually the fourth previous line when a 4×4 dither matrix is used.

First, address a0+ al T b of the change block,
Tbl is defined as follows.

ao: Address of the coding line that is the starting point of coding, that is, the starting block on the block sequence being coded.

a61: Address immediately before a6.

a,: Address of the first change block that occurs after the change block at the position an on the encoding line.

bI: Reference line, that is, the address of the first change block that occurs after the block at the aO position on the already encoded block sequence that is used as a reference during encoding.

b, -1: Address immediately before b.

b,: Address of the first change block that occurs after the change block at the position of υ, which is on the reference line.

Further, the values vt(x), vt, (x) of each block and the relative address Y-2 between blocks are defined as follows.

Also, α is the value of the block at the X position on the reference line.

■! The value of the block at the position of X on the α encoding division.

Y-Z: Relative address of Y based on address Z.

However, X, Y and 2 are ao * llo 1 + J
It can take the values +b, , b, -i and bl.

The address and block value of the changed block on the encoding line are encoded according to the following procedure.

a) Find the address &(1+IJ+1)1 and b2 of the changed block.

b) Compare Vt(as) and Vt(ao 1),
■Move the stone to I only if +(ao)=Vt(ao-1). That is, bl is regarded as bl.

(If Vs(bI t)=v*(ao) and -nu≦al-b, 5M2 (Ml 2M! is 0 or a positive integer), the correlation in the vertical direction is strong, so encode in vertical mode. We decide to divide the sign by the value of the relative address, which becomes % &3-b. However, for simplicity, M,
The following description will be made assuming that =M2=M. In addition.

vt(ao) is Vx of the already encoded reference line
Since it is the same as (bI 1), there is no need to encode the block value. For example, in the case of Figure 2, v, (a
o) = 7, Vy(ao 1 ) = 15, so vuao)\V, (a, -1), but V, (b,
-1) = 7, Vt(ao) = 7, and M = 3, since la, -b, 1 = 1<3, it is vertical mode encoding. This encoding 1ti a, -b,
= 1, so for example in Table 1 it is set as ``011''.In the case of Figure 3, Vl(ao) = 15, Vt
(ao 1) = 15 Therefore Vl(ao)
= Vt (an 1) = 25”) bt Kab
t ICfe, resulting in V+ (bI 1 ) =
7, vt(no) = 7 and 1aI-b
, I=1, so vertical mode encoding is performed. Since the encoding is al-b, = -1, according to Table 1, @01
0". In both cases of Fig. 2 and 3, "1 b,
Only the value of the relative address of Vv (
ao ) = V+ (bz-1), so vt(
all) is naturally determined from the block value of the reference line,
There is no need for special encoding. In addition, even if information on whether bl has been moved to b2 is not specially encoded, when decoding, vt(ao) and Vs(ao 1)f: are compared and Vt
When (ao)=Vz(ao-1), it suffices to move from Su to Su and decode.

When the above encoding is completed, a new 1k (
Move 1 &IK.

d) If the conditions of step C) are not satisfied (if it is decided to encode in horizontal mode, the code indicating horizontal mode and Vt
Relative to the value of (aa i) t (ILO
) indicates the value of Pv! (ao-x) (Vt(ao))
and the code DVt(a
o) Divide (IL+io)! I) This chill. For example, in the case of Woaker and Figure 4, v+(io)=ss Vt(ao
1) = 15, so the stone does not change and therefore V+(bs
1) = 5°Vt(io) = 7, L maybe I a, -
Since b, l = 4, condition C) is not satisfied. Therefore, for example, the code indicating the horizontal mode is "001",
From Table 2, the sign indicating the value of Vt(ao) is -11101
”, Table 3, the code indicating the silane length al aQ is “11111”,” 001111011111
1". When this encoding is completed, the new a6 is moved to a for the next encoding. In addition, when encoding the horizontal mode, V weight (ao), = Vt (ao)
In this case, since there is some correlation in the vertical direction, it is assumed to be the second horizontal mode, and the code indicating this mode is, for example, "0001" and V
It is also possible to allocate the code Dv1(a6)(at ao) indicating the second length al-a6 in consideration of t(to). FIG. 5 corresponds to this example, and as shown in Table 3, the code indicating the silane length IILI-ao is "11111", so it is encoded as "000111111".

According to the above encoding procedures a) to d), especially by adding the step b), even if the direction of correlation is from the vertical direction to the left or right, encoding can be performed in the vertical mode with a high compression ratio.
The overall compression ratio is greatly improved. According to a simulation using the test chart tmit of the Institute of Image Electronics Engineers, a dithered image can ideally be compressed to about 7.3 in the range of M=0 to 3.

Although this does not define the essence of the present invention, as a boundary condition, there is a line immediately before the first line in which all block values for four lines are @0#, and immediately before the first block of each line there is a line in which the block values are @0#. Encoding is performed on the assumption that there is a block with a block value of "0" and that there is a virtually changed block after the last block of each line.

Furthermore, in the above explanation, Table 1 is used as the mode code, Table i' is used as the code indicating the block value, and Table 3 is used as the code indicating the run length, but the method of the present invention is limited to these codes. Other codes may also be applied.

Further, as will be explained below, if a code table is used, the compression ratio will be further improved. 4n-3 counting from the first line of the image
The th (n is a natural number) block columns are collectively referred to as L1 column, and similarly, the 4n-2nd, 4n-1st, and 4nth block columns are collectively referred to as L2 column, L3 column, and 54th column, respectively.

The block sequence obtained by binarizing the original image using the dide matrix DM shown in FIG. 1 has the following characteristics (1), (2), and (3) from the arrangement of threshold values.

(1) In the L1 column, the block value @5″ is likely to occur, but “
8” to “15” never occur.

(2) In the L2 column and the 54th column, the block value "10" is likely to occur, but the block value "5" is difficult to occur.

(3) In the L3 column, the block value “5#” is likely to occur, but wlo
l is difficult to occur.

If these characteristics (1), (2), and (3) are used to perform encoding that allocates a small number of pits to those with a high probability of occurrence, the compression ratio will be further improved.

In other words, a different value code table as shown in Table 2 and a block run length code table as shown in FIG. 3 are prepared for columns L1 to L4.

When encoding in horizontal mode, the encoding line is from L1 column to L
It is possible to apply a method of selecting a code table for each encoded line by checking which of the four columns it belongs to.

Furthermore, the reference line may be the line before the encoding line, but in the case of a 4×4 dither matrix, there is a strong correlation with the line 4 or 2 lines before the threshold distribution, so It is desirable to use either 2 inches.

Next, a device implementing the principles of the present invention will be described.

This is an example of a sixth diagram encoding device. In the figure, 2 and 3 are the input terminals for the IL-sampled facsimile signal, memories for storing one line of signals, 2 is the encoding line memory, 3 is the reference line memory, and 4 is the starting point block of the encoding line. 1 block worth of memory to store the value Vt(ao)t'', 4
aij block value Vt (ao i) is stored in one block of memory, 5 is the reference line block value Vl (&
0), 6 is an address control circuit that controls the operation of reading out the contents of the encoding line memory 2 and reference line memory 3 in units of blocks, and 7 is aQ.
a0 address register indicating the location of.

11 is an address a1 detection circuit for detecting the address a% of the changed block of the encoded line, and 12 and 12& are the addresses b, , b of the changed block of the reference line.

The address b1 detection circuit and address b, detection circuit 12b, which detects the address b1, corresponds to the output of the coincidence circuit 71, and b! 12c is the block value vt (
one block of memory storing b+-i), 8 and 7
1 are respectively vt (b, -t) and vt (ao) and ■, (I
Coincidence circuits 21 and 22 detect the coincidence of LO) and Vt (recommendation-1), respectively (at ao) and (at b+
); 32 is a comparator that compares the absolute value 1al-bll of the contents of the counter 22 with the threshold M; 4
1 and 42 are encoding circuits corresponding to horizontal mode and vertical mode, respectively, and 51 is a signal synthesis circuit.

61 and 62 are dirt circuits, 72 and 73 are NOT
81 is an output terminal, 91 is a line buffer, and 92 is a block synthesis buffer.

The line buffer 91 of this embodiment uses the four previous lines that have the strongest correlation with the encoded line as the reference line, so the line buffer 91 uses three
It has a memory capacity for lines.

For simplicity, the I<' pulse circuit for memory shift and the lock circuit for timing, which are not essential to the circuit operation, are omitted.

The detailed configuration and operation of the device shown in FIG. 6 will be explained.

The contents of the encoded line are divided into blocks from the input terminal 1 by the block synthesis buffer 92 and sequentially stored in the encoded line memory 2. At this time, the contents of the encoded previous line are line buffers (1), (2), (3)
+"t= sequentially transferred to the reference line memory 3.

At this time, the recommended address register 7 contains the address a of the starting block. is stored, and also in the address control circuit '6.
. is initially set, so Vt(ao) + Vt(
ao 1 )=-0”.

Vl (Jio) is stored in each memory 4 t 4 & r 5.

The contents of each line memory 2, 3 are simultaneously and sequentially read out from ao in block units by the count-up operation of the address control circuit 6.

At address a, the detection circuit 11 compares the value of the block transferred from the encoded line memory 2 with the value of the immediately preceding block, and outputs "0" if they are equal, and outputs 1' if they are different, to the pH line. Similarly, address b, detection circuit 12 and address b, detection circuit 12 & address b of the changed block on the reference line.

and 11" when detected, P, * + plta
Output to line. - The numerical circuit 71 compares the contents of the Vl (1101) memory 4a and 1ao) memory 5, and outputs 1" if they are equal, and "0" if they are different, to the pH line 7, the gate 12b is p... ==゛If the same, pass the output of the P, ! line, and if p, ,=“l”, the signal of the peta line kP+t
Output to the b line. Vz(bs 1) memory 12c is controlled by the output of this goo) 12b and Vt(b+ 1)
remember. The -number circuit 8 compares the contents of the Vt (bt L) memory 12e and the Vt (io) memory 4, and outputs "1" if they are equal, and outputs "0#" if they are different to the P8 line.

(atb+) counter 22 counts the relative address (at bt) of the change block, and
Counting is started with the earlier input signal of the +tb line signals, and counting is stopped with the later input signal. However, if the signal from P□b is early, it is incremented by 1 in synchronization with the signal from address control circuit 6, and in the opposite case, it is decremented by 1. This gives a relative address with a positive or negative sign. The comparator 32 calculates the absolute value 1al-bIl of the contents of the counter 22.
For example, it is determined whether or not it is within "3", and if it is within the range, 'l' is output, and if it is outside the range, @0' is output.

Gate 62 is opened when the signal from P is 11'' and the signal from comparator 32 is "1", and the contents of counter 22 (a+b+) are encoded (by vertical mode encoding circuit 42).

On the other hand, the s (at as) counter 21 starts from the time when the address control circuit 6 sets the value.
The count is incremented by 1 according to the signal from the Pll, and the counting is stopped when the 1" signal from the Pll is received.

r-) 61 is the hermitage 4? which is opened when the output of the comparator 32 is "0#" or the signal of P8 from the - number circuit 8 is "Os". -), and (al ao) through this dart 61 and V from P4a and P4, (a(, -1) and vt(a
o) is input to the horizontal mode encoding circuit 41 and encoded. The signal synthesis circuit 51 converts the encoded signals received from the encoding circuits 41 and 42 into a signal string and outputs it to an output terminal 81-. Then a. The address register 7 receives the contents of the input counter 21 and adds them to set al to a new a.
Store as O.

At the same time xvt(an) the contents of memory 4 are Vt(ao 1
) 71 Moved to Mori 4a and new again t (a
O) and V, (a,) are stored in each memory 4.5.

Note that in the above explanation, illustrations and explanations of reset conditions for the counters, detection circuits, etc. are omitted for the sake of simplicity, but these are reset each time ao is newly set.

Although the encoding device has been described above, decoding is performed sequentially by the reverse operation. FIG. 7 shows an example of a decoding device. In the same figure.

101 is an input terminal for encoded signals, 102 is an input buffer memory, 103 is a mode code identification circuit, 111 and 112
are reference line memory and decoding line memory, 113 is lLo register, 114 is Vt(aO) memory, 115
is Vy (ao 1) memory, 116 is vt (bt
D memory, 12] is an address control circuit, 122 is a code synthesis circuit, 131 is an address b, detection circuit, 132 is an address b, detection circuit, 133 is a dart, 134 is a coincidence circuit, 141 is a (bl - a.) counter , 151 and 15
2 is a decoding circuit corresponding to vertical mode and horizontal mode; 1
61 is an adder, 171 and 172 are ke''-), 181 is a line buffer, 182 is a block decomposition circuit, and 191 is an output terminal.The same number of line buffers 181 as line buffers in the encoding device are prepared. For the sake of simplicity, the memory shift pulse circuit, timing clock pulse, etc., which are not related to the essence of the single-circuit operation, are not shown.

Next, the detailed configuration and operation of the decoding device will be explained. The 1247 encoded signals from the input terminal 101 are temporarily stored in the input buffer memory 102. At this time, the contents stored in the decoded line memory 112 that have completed decoding are transferred and recorded in the line buffer (1) in the copy 181, and simultaneously converted into a binary signal by the block decomposition circuit 182 and output from the output terminal 191. be done. At this time again.

The contents recorded in the line buffers (1) and (2) in the 181 are transferred to the next line buffers (2) and 181, respectively.
(3), the contents of line buffer (3) are P, 8. At the same time as being transferred from the line to the reference line memory 111 and recorded.

V2 (ao-1) 0# is recorded in the memory 115 1;
The mode code identification circuit 103 is connected to the input buffer memory 102.
A necessary number of signals are read out from the signal structure, and it is determined from the code structure whether the mode is vertical mode or horizontal mode. In the vertical mode, the output of the v-line is set to '1', and in the horizontal mode, the output of the veteran is set to '12'. Address control circuit 12
1 receives “1#” from the V line, reference line memory 1
a received from the P113 line for 11. Shift the memory contents one block at a time from the address.

A / signal is applied to the address b detection circuit 131 and the address bt detection circuit 132 so that they are output in block units. The vt(ao) memory 114 is a memory for one block, and stores (&) from the reference line memory 111 when ao is set in the address control circuit 121. When the value of the block received from the reference line memory 111 and the value of the block immediately before it are equal, the address b1 detection circuit 131 and the address b detection circuit 132
Outputs “1” and “0” when the values are different. Matching circuit 1
34 is Vt(ao) memory 114 and Vt(ao i')
Compare the contents with memory 115, and if they are equal, set "1".
When different, outputs 0#. Dart 133 is matching circuit 1
When the output of 34 is "0", address b, detection circuit 131
When the output of the match circuit is @1#, the output of address b and the detection circuit 132 is passed. vt (bt 1
) The memory 116 stores the value V+(bt 1) 1f before locking from when '1' was output from the dart 133.

(bt ao) Counter 141 is address control circuit 1
From the time when 21 receives "1#" from the V line, the count contents are increased by 1 each time the address control circuit 121 receives the "1#" signal from f-)133, and when it receives "1#" from f-)133, the operation is stopped. The count content "bl-ao" is output to the adder 161. (a, -b,) When the decoding circuit 151 receives "1" from the V line, it calculates the relative address a1-bl from the signal received from the input buffer memory 102 and outputs the result to the adder 161. As a result, adder 1
The output of adder 161 represents run length al-8(1) and is output to gate 171. When this date 171 receives "1" from the V line, it opens and converts the output of adder 161 to al-a(, While outputting to the decoding circuit 153, a
It also outputs to the 0 register 113 and a. is updated to a. The al-a6 decoding circuit 153 receives the pixel signal (block value) vt (bt t) received from the P116 line.
is output to the code synthesis circuit 122 the number of times indicated by the signal from the ff-) 171.

On the other hand, the 81 ao decoding circuit 152 is a veteran
When the input buffer memory 102 receives the received signal and pH! The signal received from the l line, the color run length "!Ll-ao#, and the pixel signal (block value) at ao are determined, and the pixel signal V2 (a (1) is @ , ,
, ag s times to the code synthesis circuit 122, and simultaneously outputs a signal indicating the value of "al-ag" to the r-t 172. This r-t 172 company guest line is opened only when it is 1'', and the contents of the lLo register 113 are updated to a.

The code synthesis circuit 122 includes decoding circuits 152, 153 and a
6 receive each signal from the register 113, ao at
Line memory 11 performs decoding between 7 and decodes the result
Output to 2. At the same time, from the code synthesis circuit 122, V, (a
g-1) A to the memory 115. The block values between 81 and 81 are output and the contents of this memory 115 are updated for the next encoding.

In the decoding device described above, for the sake of simplicity, illustrations and explanations of reset conditions for the counters, detection circuits, etc. are omitted; however, the address bl detection circuit 131. The address b1 detection circuit 132, bl-aQ counter 141, etc. are reset each time aO is set to a new value.

As described above in detail, according to the encoding method of the present invention, an image having multiple levels of gradation can be encoded at a high compression rate.

It should be noted here that the present invention is directed to blocks of binary code sequences obtained by binarizing an original signal having multiple levels of gradation using a dither matrix, etc. The idea can also be applied to the case of encoding an original signal having multiple levels of gradation, that is, a multilevel code sequence itself. For the multilevel code string on each scanning line, a pixel with a different value from the previous pixel is defined as a changed pixel, and the address so of the changed pixel on the encoding line, the address a1 of the changed pixel immediately after this changed pixel, and the encoding a on the already encoded line before the line, ie, the reference line. υ Later, find the address b1 of the first changed pixel and the address b2 of the changed pixel immediately after this changed pixel, and calculate the value Vt(an) of the pixel at address aQ on the reference line and ag on the encoding line. The value of the pixel at the address immediately before V! (no
-1), and if Vs(ao)=V*(as-1), replace b2 with l)tK, and bl on the reference line.
The value Vl (bl-1) of the pixel at the address immediately before is v, (
ao) and al-b, is within a predetermined range, and if this condition is satisfied, the relative address at
The changed pixel of ao is encoded with a code indicating the value of b, and if the above condition is not satisfied, the condition is not satisfied. The pixel that changes in a(, is encoded. According to this kind of encoding, even when encoding the multilevel code sequence itself, it is possible to encode it even if the strength of the correlation is tilted to the right or left from the vertical direction. Since encoding can be performed in an efficient vertical mode, the overall compression rate is greatly improved compared to the case where the MR method is simply extended and applied to a multilevel code sequence.

[Brief explanation of the drawing]

Figure 1 is a diagram for explaining the organized dither imaging method. Figure 1 (a) is a pixel level diagram of the company's input image, Figure 1 (b) is a diagram of the dithering image, and Figure 1 (cl is the dither image). Figures 2 to 51 An explanatory diagram of noodles for detailed explanation of the present invention,
Figure 6 is a circuit diagram of an example of a coding device, and Figure 7 is a circuit diagram of an example of a coding device. In the drawing, ao is the address of the changed block on the encoding line at is the address of the changed block immediately after aQ, bl is the address of the changed block immediately after a6 on the reference line, b2 is the address of the changed block immediately after b1 0 Patent applicant Kokusai Telephone, Shindenwa Co., Ltd. Representative Patent attorney Jube Mitsuishi (1 other person)

Claims (2)

[Claims] (1) A binary code sequence obtained by binarizing an original signal having multiple levels of gradation is divided into a predetermined number n of pixels on each scanning line, and each block is divided into blocks that obtain 2n values. form,
A block that has a different value from the previous block on the block sequence is defined as a changed block, and the address a6 of the changed block on the block sequence to be encoded, that is, the encoding line, the address a1 of the changed block immediately after this changed block, and the already encoded block. Find the address b of the changed block immediately after the address of aO on the reference 2-in, that is, the address b of the changed block immediately after this changed block, and calculate the block value V1 at atrea kC of aO on the reference line. (a6) is compared with the block value Vl (a・-1) at the address of ao-1 on the encoded line, and Vi
(ILo) = Vt (lko 1) (In the case of D, replace ``s'' with -, and the block value V+(b+-1) at the address of ``-1'' on the reference line is the address of a on the encoded line. The block value Vt (
It is determined whether the condition that the relative address at-kl+ is equal to (recommended) and within a predetermined range is satisfied, and if this condition is satisfied, the relative address value l1l-bl is indicated. A change block of &0 is encoded with a sign, and if the above condition is not satisfied, the condition is not satisfied, and a change of a・ is expressed with a sign that indicates the block value of V2(a・) and the value of the gin length of al-ao. A method for encoding an image having multiple levels of gradation, which is characterized by encoding blocks. (2) The encoding method for an image having multi-level gradation as set forth in claim 1, wherein the code sequence used for encoding the changed block is selected for each block sequence.