JPS58213379A - Optical information reader - Google Patents

Abstract

PURPOSE:To attain the use of an image sensor having defective bits, by detecting an error with a prescribed method at each signal of the image sensor to each picture element and correcting the error signal into an intermediate value of the signal detected with plural picture elements relating to the error signal. CONSTITUTION:The image sensor 3 scans an optical image and reads out it as a corresponding electric signal. The sensor 3 is driven with a reading sensor drive circuit 12 and amplified 4 analogically. A peak value of a signal of the output is sampled and held 5 at each picture element of the sensor 3 with a synchronizing signal from a timing generating circuit 13 and passes through a shift register comprising the series connections of the next sample holding circuits B6 and C7. When an error signal is detected 10, a processing circuit 17 has a function to correct the error signal into the intermediate value of electric signals detected at plural picture elements adjacent to the picture signal corresponding to the error signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optical information reading device using an image sensor, which has a function of automatically correcting an error signal in a read signal.

Conventionally, regarding error detection and correction of signals read out from an image sensor, a method has been known in which a series of read out signals is processed by a low-pass filter to cut off wide-band frequencies and shape the waveform. However, a method for detecting and correcting errors for each signal corresponding to one pixel in an image sensor has not yet been proposed.

For example, an image sensor is fabricated by arranging a large number of photodiodes forming one pixel on a single silicon substrate. Therefore, as the number of pixels in an image sensor increases, defects in photodiodes and readout circuits are more likely to occur during the manufacturing process, and the probability that defects in pixels of the image sensor will occur during use increases. If a defect occurs in one pixel of the image sensor, the corresponding detection signal becomes an error signal. The more these defective pixels are scattered, the more erroneous signals will be generated, causing malfunctions in video processing.

To correct this error signal, there is a method of overall waveform shaping using a low-pass filter, but since each bit is not processed, error correction is not reliable.

The present invention has been made with the aim of improving such drawbacks, and is to detect errors using a predetermined method for each signal corresponding to each pixel of an image sensor, and to detect the error signals in a plurality of consecutive pixels. The present invention aims to automatically correct error signals for each pixel by providing a function to correct intermediate values of detected signals, thereby enabling use of image sensors with bit defects.

That is, the present invention provides an image sensor capable of reading out an optical image as an electrical signal corresponding to the optical image using a scanning signal, a driving device for driving the image sensor, and an apparatus for processing the read out electrical signal. and a processing device that obtains a video signal, when the processing device detects an error in each electrical signal detected by each pixel in the image sensor, the processing device responds to the error signal. The optical information reading device is characterized in that it has a function of correcting an error signal in the intermediate value of an electrical signal detected by a plurality of pixels connected to a pixel.

Here, the image sensor may be, for example, a solid-state image device such as a MOS image sensor, a PCD type, an 880 type, or a PCD type image sensor, or an electron tube such as an image pickup tube. In short, any photoelectric conversion element may be used. The signal waveform read out by scanning the image sensor with the scanning signal has a waveform as shown in FIG. 3(b). If there is an error signal, the result will be as shown in FIG. 3(C). error signal A
If there is a signal, the signal is corrected to the intermediate value of the signals on both sides.

The intermediate value may preferably be an arithmetic average value, but depending on the video characteristics, a weighted average of both may be considered. or,
Correction may be performed using a weighted average value of signals of a plurality of bits on one side of a defective bit (erroneous signal bit).

A first method for detecting error signals is to treat signals that do not exist within a predetermined level range as error signals. Second
In this method, if the slope for each pixel of the envelope formed by consecutive peak values of the signal reaches a predetermined value or more, the signal corresponding to this pixel can be determined as an error. can.

As described in the embodiment, the third method focuses on the signal of a specific pixel and calculates the difference between the average value of the signals of pixels on both sides thereof and the signal of the specific pixel for all the pixel signals.

That is, if the peak value of the Nth signal is V(N), then vV (N>= (v(N-1)+V (N+1))
Find /2-V(N). (N) becomes as shown in Fig. 3(d). In this case, the absolute value of the difference is the largest at the Nth point and is between N and 1. N+1st is equal and next largest.

In this way, 1ΔV(N)l becomes maximum at the abnormal bit. In this way, an abnormal signal can be detected from the distribution of ΔV(N). Among these, what is described as the second embodiment is such that when the number of pixels in which 1△V(N)1 reaches a predetermined value or more continues at least twice, for example, 1△
This is a method in which the Nth signal is determined to be an error signal when both V(N-1>1 and 1ΔV(N)l reach predetermined values or higher).

This Lt also 1△V(N-1)l, i△V(N)l, 1△
When all three values of (N+1)l reach a predetermined value or more, the Nth signal may be determined to be an error signal.

When a video signal changes from black to white or vice versa, it generally requires several pixels and the change is clearly one, so the above method is sufficient to detect error signals. In order to obtain a clearer video signal, it is sufficient to use a pixel with a smaller area.

The present invention will be described in detail below based on one embodiment.

FIG. 1 is a block diagram showing the overall configuration of this embodiment. The information card 1 is arranged so as to reflect irradiated light 20a emitted from a light source 20 and image a barcode on a reading sensor 3 via an optical lens 2 as reflected light 20b.

The reading sensor 3 is an MO8 type image sensor in which several hundred to two thousand photodiodes are arranged and formed on a single silicon substrate. The light image of the barcode projected onto the image sensor accumulates charge in a PN junction layer forming a photodiode in the image sensor in proportion to its brightness. That is, an electrical image of the charge distribution corresponding to the optical image can be created. The structure is such that electrical signals can be serially extracted from each photodiode by applying horizontal and vertical scanning pulse signals from the outside and sequentially sweeping them over the image buffer.

Further, the magnification of the optical lens 2 is adjusted so that the pixels of the image sensor represent the width of a white or black barcode using several bits.

The reading sensor drive circuit 12 includes the timing generation circuit 1
This is a drive circuit that receives a synchronizing signal from the sensor 3 and applies a scanning pulse to the reading sensor 3 to read out the electrical signal to the outside. The serial electrical signal read from the reading sensor 3 is input to the analog amplifier 4, amplified, and then input to the peak value detection sample hold circuit A5.

The sample hold circuit A5 is a timing generation circuit 13.
It has a function of obtaining a synchronizing signal from the sensor and sampling and holding the peak value of one signal corresponding to one pixel of the reading sensor 3. Then, the output is shifted to the next sample hold circuit B6 by obtaining a synchronization signal for the next time block from the timing generation circuit 13. Similarly, its output is also shifted to the next sample-and-hold circuit C7 by the next synchronizing signal. That is, a group of three sample-and-hold circuits connected in series constitutes a kind of shift register, and normally holds each peak value of the electrical signal corresponding to Q consecutive pixels in the image sensor. There is. The output of the sample hold circuit C7 is input to the low pass filter 15.

The low-pass filter 15 smooths the stepped waveform output from the sample bold circuit C7, and the binarization circuit 16 converts it into a video signal that conforms to the black and white signal of the information card 1. The data processing circuit 17 recognizes the step-like waveform. It is configured to perform processing and data processing.

On the other hand, the weighted average circuit 8 is a circuit that receives the output (VO) of the peak value detection sample hold circuit A5 and the output (2) of the sample hold circuit C7 and calculates an average value. Its output (a) is Va-(VO+V2)/2. The difference detection circuit 9 receives the output v of the sample hold circuit B6.
1 and the average value output Va are input, and the absolute value Vd of the difference is compared with a predetermined voltage Vk. If the difference is large, a primary error signal VC is sent to the error detection circuit 10. The error detection circuit 10 consists of a two-digit shift register and stores two cycles of the primary error signal. When both of the shift registers are holding the primary error signal, that is, in the three sample and hold circuit groups mentioned above, one specific state and one bit at a time are shifted to the right in the diagram for that state. In the state of the next cycle, the error detection circuit 10 outputs the error detection signal Ver only when the first error signal VC is continuously input through the above processing.

The error detection signal is input to the sample signal switching circuit 11. When the signal is input, the sample signal switching circuit 1
1 functions to input a clock signal from the timing generation circuit 13 and input the above-mentioned average value ■a to the sample hold circuit C7 in synchronization with the clock signal.

That is, when it is detected that the output V1 of the sample and hold circuit B6 is an error hit, the electric signal ■0 corresponding to the pixels on both sides of the pixel on the image sensor corresponding to the v1 signal is detected.
It functions to correct the average value of V2 and V2 to Vl.

The above is the overall configuration of this embodiment.

Hereinafter, the specific structure and operation of this device will be explained based on the circuit diagram shown in FIG. 2 and the timing chart shown in FIG. 4.

The image of the information card 1 generated on the reading sensor 3 is serially read out pixel by pixel using a scanning pulse synchronized with a clock signal from the timing generation circuit 13, and is manually input to the analog amplifier 4 and amplified. FIG. 3 shows the output waveform of the analog amplifier 4. Figure 3 (
a) shows the barcode image on the reading sensor 3. Figures 3(b) and (c) are similar to Figure 3(a).
) is an electrical signal waveform obtained by sweeping the image from right to left in the diagram and extracting it serially along the time axis. In the figure, one cycle of the high frequency waveform corresponds to one pixel of the reading sensor, and its peak value represents brightness. The black portions appear with small signal amplitudes. Figure 3(b) shows the output read by a normal reading sensor, and Figure 3(C)
is the output waveform from the reading sensor that includes the abnormal bit. The portion indicated by the Δ symbol indicates that no signal waveform is output. Information card 1
This is the same as when some black stains are attached to the printed pattern on the image. As another example of an error signal, although not shown, there may be a case where a high level signal is always sent regardless of the brightness of the image.

The device of the present invention corrects such signal errors.

In FIG. 4, S is a scanning synchronization signal clock pulse of the reading sensor 3. TI, T2, etc. represent a read cycle of one pixel. S is a waveform having a negative pulse at time t3 in each time block. Vs
is the output waveform of the analog amplifier 4 of the video signal. S
The video signal Vs is output in synchronization with the rising edge (t4) of Vs.

As shown in the figure, Vs in the T3 block is zero. That is, this means that a failure has occurred in the pixel of the image sensor that corresponds to the signal.

Vs is charged to a capacitor 502 via a diode 501. The charging voltage of the capacitor 502 is the value obtained by subtracting the forward voltage drop of the diode 501 from the peak value of Vs. Even if Vs decreases, the charged voltage is not discharged because the diode 501 is reverse biased, and the voltage remains at Vs.
The value equivalent to the peak value of is held. t of next time block
At 1, a pulse is applied to analog switch 503, turning the switch on and charging capacitor 504 with the charge on capacitor 502.

At this time, since the capacitance of the capacitor 504 is set to be sufficiently smaller than the capacitance of the capacitor 502, the voltage of the capacitor 504 can easily be made almost equal to the initial charging voltage of the capacitor 502. This charging voltage is output as VO from the output terminal of the sample-and-hold circuit A5 via the voltage follower operational amplifier 505. vO is a value obtained by sampling and holding the peak value of Vs input in the previous time block. On the other hand, the analog switch 503 is turned off at 12:00, until the condensation is reached.
maintain. Next, a negative pulse S is applied to the cathode of the diode 501 at t3 of each time block via the series connection of the buffer 507 and the resistor 506. Therefore, during the negative pulse period, the voltage charged in the capacitor 502 is discharged through the above path. Then, the capacitor 502 receives the next V after 14:00 in the same time block.
The battery is charged to the peak value of s.

In this way, vO becomes a voltage waveform that sequentially holds the peak value of VS input in the previous time block at time t1 of each time block.

Next, the operation of the sample and hold circuit B6 will be described.

A negative pulse is input to the analog switch 601 at 17:00, during which time the analog switch 601 is turned on, and the capacitor 602 is charged and discharged to have the same potential as the output voltage VO of the sample hold circuit A5. This potential is maintained even when analog switch 601 is turned off. And that potential is the voltage follower operational amplifier 603
is output from. The output waveform is 1. ■1 is
The potential of 0 at 17:00 in each time block is held.

Next, the operation of the sample and hold circuit C7 will be described.

First, a case where no error signal is detected will be explained.

If no error is detected, sample hold switching circuit 1
A negative pulse is applied to the analog switch 701 from 1:00 to 15:00. On the other hand, the gate of analog switch 702 remains at a high level without changing, so the switch is in an off state. Therefore, analog switch 701 is turned on only during the pulse of t5, making capacitor 703 equal to the output voltage of sample-and-hold circuit B6. Even when the analog switch 701 is turned off, the capacitor 703 maintains the v1 voltage, and the voltage V1 is outputted via the voltage follower operational amplifier 704. This output voltage is V2.

That is, V2 holds the value of ■1 at 15:00. To summarize the above actions, the electrical signal read between timing ℃4 in time block T1 and timing to in time block T2 is
At timing t1 of 2, the peak value of the electrical signal is sampled and held and outputted as a lightning voltage. Next, at timing t7 of the same time block T2, the VO is sampled and held and output as the V1 voltage. Next, at timing t5 in time block T3, the voltage v1 is sampled and held and output as the voltage V2. Due to this action, the peak value of the electrical signal is shifted in synchronization with the clock signal, and the peak value of the electrical signal is shifted in synchronization with the clock signal, and the peak value of the electrical signal is shifted in synchronization with the clock signal.
Serially taken out from the output of 7. In this way, the three sample and hold circuits constitute one type of system register. As a result, VO, Vl, and V2 in the period from tl to 15 of each time block represent the peak values of three adjacent electrical signals, respectively.

For example, the value of vO in time block T4 is the peak value of the electrical signal read in time block T3, the value of Vl is the peak value of the electrical signal read in time block T2, and the value of ■2 is the peak value of the electrical signal read in time block T3. Each represents the peak value of the electrical signal read at T1.

Next, the operation when there is an error signal will be described.

In FIG. 4, the read signal VS in time block T3 has no signal, which is an error signal.

First, the weighted average circuit 8 will be described. Voltage vO is resistor 8
01 to charge the capacitor 804, and the voltage v2 is
The capacitor 804 is charged via a resistor 802. Therefore, when the resistance values of resistor 801 and resistor 802 are equal, capacitor 804 always maintains the average voltage of VO and V2, that is, the voltage of (VO+V2)/2. By changing the ratio of these resistance values, an arbitrary weighted average can be calculated. This voltage is input to a non-inverting voltage follower operational amplifier 803, which outputs an average voltage va of vo and 2. This output Va can be input to the positive input of an operational amplifier 704 via an analog switch 702. In addition, the output (a) is also input to the difference detection circuit 9.

Next, the operation of the difference detection circuit 9 will be described.

Operational amplifiers 906 and 905 constitute a window comparator. Let the forward voltage drop of diodes 902 and 903 be [)V.

The reference input is Va + Dv on the operational amplifier 906 side,
The operational amplifier 905 side is Va-DV.

The comparative manpower of the wind comparator is Vl and Va
When -DV≦■1≦Va+Dv, that is, IVl-Va1≦D■, the output of the window comparator becomes high level.

Further, when l Vl - Va l >Dv, the window comparator output becomes a low level. This low level signal VC is the first error signal and is input to the error detection circuit 10. This circuit 9 compares the signal detected by one pixel among the signals detected from consecutive pixels on the reading fence with the average value of the signals detected from the pixels on both sides, and the difference is determined by a predetermined value. When the value exceeds this value, it acts to output a low level signal. In this case, the predetermined value Vk is given by the forward voltage drop Dv of the diode.

Next, the error detection circuit 1o will be described.

The above output VC is a D-type flip-flop circuit (hereinafter referred to as D
-FF circuit) 101.

Since the D-F, F circuit 101 receives a clock pulse at 13:00, the voltage at the Q output terminal is synchronized with the t3 clock pulse. The synchronized Q terminal output is D-FF
The signal is input to the D terminal of the circuit 102, and the Q terminal output is input to the AND circuit 103. Since the D-FF circuit 102 also receives the t3 clock pulse, its output is synchronized with the t3 clock pulse.

Further, the D-FF circuits 101 and 102 constitute a two-digit shift register, which is shifted by the t3 clock.

The Q terminal outputs of both D-FF circuits 101 and 1o2 are AND
Since it is input to the circuit 103, when both Q outputs are at high level, the AND circuit 103 outputs a high level signal. That is, the error detection circuit 10 outputs a high level error detection signal only when the D inputs of both D-FF circuits are both low level. When a high level signal is issued, 1V1-(V○1V2>
/2 l >Dv. The level signal Ver from this error detection circuit is input to the sample signal switching circuit 11.

Next, the operation of the sample signal switching circuit 11 will be described.

The D-FF circuit 111 receives a clock pulse at time t7 and resets its state. That is, (at 7 o'clock, Q@
The specific output low level and the Q end output are reset to high level. In this state, if no high level signal is input to the CK@ input, that is, if no error signal is detected,
Since the NAND circuit 114 always receives a low level signal, it always outputs a high level signal regardless of the clock gate input at t5, and as a result does not act on the analog switch 702 at all. The NAND circuit 113 inputs a high level signal, converts the t5 clock negative pulse signal into a positive pulse signal by the inverter 112, and inputs the converted signal to the gate. Therefore, the NAND circuit 113 sends out a low level signal only when the t5 clock pulse is input. As a result, the analog switch 701 turns on in synchronization with the t5 clock pulse and charges the capacitor 703 to the value of vl at that time. On the other hand, if an error is detected, the D-FF111
A high level signal is input to the CK terminal at 3 o'clock in a certain time block. The Q terminal output VQ of the D-FF 111 becomes +5V in synchronization with this. Then, VQ remains at a high level until a reset pulse is input at 17:00 in the same time block. The NAND circuit 114 has Vq and [
Because the inverted positive pulse of 5 clocks is manually generated,
Outputs low level signal pulse at 15:00 (Vl)
)do. Therefore, the analog switch 702 is turned on for a period of the pulse width at 15:00, and the capacitor 703 is charged with the output Va of the weighted average circuit 8.

As a result, if there is no error signal (at 5 o'clock, Vl is sampled and held and the output v2 is 1q), but if there is an error signal, the value of vl at that time is an error signal, so 15 At the same time, the average value va is sampled and held and v2 is output.In this way, the error signal of Vl is corrected to the average value.

Next, the overall operation of error detection and correction can be summarized as follows.

Time block 1. At T2, no error signal is read. An error signal is read in time block T3. At the next time block, T4, 0
is the voltage of the error signal.

From t1 to 15:00 in time block T4,
vO holds the voltage of an error signal, and Vl and V2 hold the voltages of normal signals. That is, VO, Vl, and V2 correspond to the peak values of signals detected from three consecutive three pixels. The average value output in this case is Va − (VO + V2)/
2, so now if V2=0.7 and VO=O,
Va=Q, 35.

Next, the absolute value of the difference is l V"lVa l = 11-0
351=0.65, which is larger than the set value Vk=0.14, so the output Vc of the difference detection circuit 9 becomes a low level.

Here, a large difference indicates that any of VO, Vl, and V2° may contain an erroneous rib bit. If the difference becomes large starting from time block T4, it is clear that Vo, which holds the most recently read signal, may be considered to have an error. Detection of this next error is given as a low level signal of VC, and is stored in the D-FFIOI in synchronization with the rising edge of the negative clock pulse at 13:00. For this reason, D-FF101
holds this state until 13:00 of the next time block T5.

Next, the period involved in error detection is time block T5
1. This is the period from t5 to t5. During this period, the sample thread lead circuit shifts, so V2. V
l and VO hold the peak values of Vl, VO, and Vs in the previous time block T4, respectively.

In this example, VO=1. V1=O.

V2=1. Therefore, the average value Va is Va-(O+V
2>/2=1. Also, the difference is 1v1-Va 1=l
o-1l=1, which is greater than the predetermined Vk. Therefore, it can be predicted that there is an error in 0°Vl and V2. Furthermore, if the possibility of such an error is detected twice in a row, it is obvious that it can be considered that there is an error in vl the second time.

In response to the 13:00 clock pulse of time block T5, the state of the D-FF circuit 101 changes to the D-FF circuit 102. The D-FF circuit 101 then stores the state corresponding to the human power signal Vc in synchronization with the 13:00 clock pulse. As a result, this two-digit shift register is T4
The primary error state detected at step 5 is held. That is, it means that the primary error signal was detected in consecutive time blocks. In this case, the above-described function of the sample signal switching circuit 11 applies a negative pulse to the analog switch 702 at 15 o'clock in the time block T5 to set the value of v2 to the value of va.

In this way, when shifting Vl to v2, the average value Va is input in place of the error signal vl for correction.

Next, a second embodiment will be described in which the above processing is implemented using a digital computer.

The output of the sample-and-hold circuit A5 in the first embodiment is input to a high-speed A/D converter, converted into a digital quantity, and then input to a digital computer system. Further, the configuration is such that a clock signal equal to the period of each time block is also input at the same time.

FIG. 5 shows a flowchart of the computer program. Step 102 is initial setting. FLAG is used to determine whether or not a primary error has been continuously detected in two consecutive time blocks. N is used to count the number of pixels corresponding to one scan by the reading lens 3.

Step 104 is a step of updating a counter in order to count which pixel the read signal is a signal from. Step 106 is for determining whether a synchronization signal for J reading has been input, and is for synchronizing one cycle of the computer program with the cycle of data detection from the hardware. That is, it waits until the clock signal is input. When the clock signal is input, the process proceeds to step 108, and the data is output to VO.
Read into. Step 110 is VO, Vl.

This is the initial setting so that 3 data is read into v2. In step 112, the absolute value of the difference between the average value of VC9 and ■2 and ■1 is determined, and in step ``114, this value is compared with a preset value Vk.If the difference is small, that is, there is no error signal. If so, proceed to step 116.
In step 116, since there is no error, h L
Set AG to 0 and proceed to steps 118 and 128.

Therefore, ■Shift 1 to V2 and VO to Vl and step 1
30, V2 is read. In step 132, it is determined whether scanning is complete. If it is not the end, the process returns to step 104 and the following process is repeated.

If it is determined in step 114 that VCmp>vk, that is, if there is an error signal, step 1
Proceed to step 20 to determine whether FLAG is O or not. F.L.A.
If G is O, it means that the first error has been detected, and FLAG is set to 1 to that effect, and step 118
．． Proceed to 1″28,130°132 and change Vl to V21.:;
Shift VO to Vl and update the data. Return to step 104 for the next time block. After determining the average value and the difference, a determination is made in step 114, and if it is determined that the difference is larger than a predetermined value, the process proceeds to step 120. This time, since an error was detected in the previous time block, FLAG is 1, so the process advances to step 124. In other words, error detection was performed continuously in two consecutive time blocks. In this case, since it can be determined that (1) is an error, in step 1.26, the value of vl is corrected to the total average value (VO+V2)/2, and the value of V2 is updated to (VO+V2)/2. In the next step 128, the value of vl is updated to the value of VO, and in step 130, v2 is addressed to a predetermined address.

In this way, in step 130, the data sequentially read into predetermined addresses becomes correct data with the error signal corrected.

The above process involves storing the read data,
After that, a series of processing may be performed.

In summary, the present invention detects an error signal for each bit, and when an error signal is detected, the error signal is corrected using the intermediate value of the signals at both ends. For detection, a method is used in which the average value of the signals on both sides is compared with the signal at the center, and an error signal is detected according to the difference. Therefore, according to this device, errors are detected and corrected bit by bit, so that error signals can be reliably corrected. Therefore,
The image sensor can be used even if it has bit defects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment according to the present invention. FIG. 2 is a detailed electrical wiring diagram of a block related to the gist of the present invention in the block diagram shown in FIG. FIG. 3(a) shows an image pattern on the image sensor. FIG. 3(b) shows a signal waveform read out from the image sensor. Figure 3 (C
) is the detected waveform when there is an abnormal signal, as shown in Figure 3 (
d) shows the distribution of the difference between a specific signal value and the average value of the signal values on both sides of that signal.
FIG. 5, which is a timing chart showing the operation of the embodiment, shows a flowchart of the computer program used in the second embodiment. 3...Reading sensor, 5.6.7...Sample hold circuit, 8...Weighted average circuit, 9...Difference detection circuit, 10...Error detection circuit, 11...Sample signal switching Circuit patent applicant Hikidenso Co., Ltd. Agent Patent attorney Hirodo Okawa Patent attorney Raw material Shudo Patent attorney Akio Maruyama

Claims (3)

[Claims] (1) An image sensor that can read out an optical image as an electrical signal corresponding to the optical image using a scanning signal, a drive device that drives the image sensor, and a drive device that processes the read out electrical signal. and a processing device for obtaining a video signal, when the processing device detects an error in each electrical signal detected by each pixel in the image sensor, the processing device reads the pixel corresponding to the error signal. 1. An optical information reading device having a function of correcting an error signal at an intermediate value of an electrical signal detected by a plurality of pixels connected to each other. (2) In detecting an error in the electrical signal detected by each pixel, the processing device detects an intermediate value between the detection signal of one arbitrarily specified pixel of the image sensor and the electrical signals detected from pixels on both sides thereof. 2. The optical information reading device according to claim 1, further comprising a function of detecting an error signal from a distribution of the difference generated by changing the specific pixel. (3) Detection of the error signal is performed in the distribution of the difference,
Claim 2, wherein an error signal is detected only when the difference values corresponding to at least two consecutive specific pixels both exceed a predetermined value. Optical information reading device.