JPS58212277A - Magnetic recorder and reproducer - Google Patents

Abstract

PURPOSE:To improve the instability of framing discrimination due to temperature change, by processing digitally a composite synchronizing signal. CONSTITUTION:In discriminating an even and an odd number field forming one frame of a video signal, a non-retriggerable monostable multivibrator 23 which is triggered at a tail ridge of a horizontal synchronizing signal and generates an output longer than a 1/2 period and shorter than one period is operated. The even and the odd number field is discriminated by sampling this output with a clock formed with the vertical synchronizing signal. Further, in Figure, 1 is a composite synchronizing signal separating circuit, 21 is a monostable multivibrator having a metastable state time longer than the width of the horizontal synchronizing signal and shorter than the equivalent signal width of the vertical synchronizing signal, 22, 24, 25 are D flip-flops, 26 is a differentiation circuit and 6 is a frequency divider.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic recording/reproducing device, in which a composite video signal (hereinafter referred to as a video signal 2) is generated by heating.

The purpose is to reduce the instability of framing discrimination in (c).

A conventional magnetic recording/reproducing device will be explained with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram of a framing determination section of a conventional magnetic recording/reproducing apparatus, and FIG. 2 is a waveform diagram of input/output signals of various parts of the synchronization system.

In the figure, reference numeral 1 denotes a composite synchronization signal separation circuit, which separates a horizontal synchronization signal and a vertical synchronization signal, that is, a composite synchronization signal, from a video signal. 2 is a vertical synchronization signal separation circuit, 3 is, for example, 40
0 μSEC mono multivibrator (hereinafter referred to as MMV), 4 is 10 pSEC (7) MMV, 5 is A
The ND circuit 6 is a frequency dividing circuit which receives the output signal of the vertical synchronizing signal separation circuit 2 as an input and receives the output signal of the AND circuit 6 as a RESET input.

7 is a rotating cylinder having a magnetic head, 8 is a cylinder 7
PG amplification circuit that amplifies the PG signal from 9, DELA
In the Y circuit, 1o is a frequency dividing circuit, 11 is a phase detection circuit for detecting phases 3 and - of the output of the frequency dividing circuit 1o and the output of the % frequency dividing circuit 6, and 12 is a cylinder drive circuit.

Next, the operation of this device will be explained.

Now, when a video signal as shown in FIG. 2A is input to the composite sync signal separation circuit 1, a composite sync signal as shown in FIG.
A vertical synchronization signal as shown in Figure C is separated. From the rising edge of the vertical synchronizing signal separated by the vertical synchronizing signal separation circuit 2, a pulse of 40011 SEC is outputted by MMV3 of 400 μSEC, and from the falling edge of the pulse of 400 μSEC, a pulse of 10 μSEC is output from the MMV3 of 10 μSEC.
It is output by MV4. This 1oμSEC pulse is a necessary pulse for 7 lemming discrimination,
The signal is input to an AND circuit 6 together with the composite sync signal separated by the composite sync signal separation circuit 1, and the output signal of the AND circuit 6 becomes a framing signal:1'). When the EVEN signal as shown in Fig. 2A is input, nothing is output as shown in Fig. 2F, but the EVEN signal as shown in Fig. 2A is input.
When an ODD signal as shown in Figure G is input, the second
A pulse as shown in the figure is output. This pulse is %
The RESET input of the frequency dividing circuit 6 is used, and a square wave obtained by frequency-dividing the vertical synchronizing signal separated by the vertical synchronizing signal separating circuit 2 is outputted from the % frequency dividing circuit 6. The square wave output from the % frequency dividing circuit 6 and the square wave created from the PG pulse obtained by rotation of the cylinder 7 are input to the phase detection circuit 11, and the phase of the cylinder 7 is determined by the phase error of the two square waves. is under control. However, this method has the disadvantage that the accuracy of framing discrimination decreases because the time constants of the mono-multi-bi-breaks 3 and 40 change due to temperature changes.

The present invention eliminates these drawbacks and provides a magnetic recording/reproducing device with high framing discrimination accuracy.

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4. ,,: FIG. 3 is a block diagram of a framing discriminating section of a magnetic recording/reproducing apparatus according to an embodiment of the present invention, and FIG. 4 is a waveform diagram of input/output signals of each section of the rotation section.

67, 1 in the figure is a composite synchronization signal separation circuit, which separates a horizontal synchronization signal and a vertical synchronization signal, that is, a composite synchronization signal, from a video signal. 21 is a time longer than the width of the horizontal synchronization signal and shorter than the equivalent signal width of the vertical synchronization signal, for example, 10μSEC
MMV, 22 is a D which uses the output signal of MMV21 of 1oμSEC as CLOCK input and the composite synchronization signal as D input.
Type edge trigger flip-flop, 23 is %H
.

A period longer than 1H, for example 718H (=66
．． 6pSEC) MMV, 24 is an AND circuit, 26 is a D type edge trigger flip-flop 22 output signal is used as a CLOCK input, and the output of the AND circuit 24 is connected to a D
26 is a differentiating circuit; 6 is an output signal of the differentiating circuit 26;
This is a % frequency dividing circuit which has a SET input and an output signal of a D-type edge trigger flip-flop 22 as an input.

7 is a cylinder, 8 is a PG amplifier circuit that amplifies the PG multiplied signal from cylinder 7, 9 is a DELAY circuit, 1o is a frequency divider circuit, 11 is the output of frequency divider circuit 10 and %62, -1 the output of frequency divider circuit 6 a phase detection circuit that detects the phase of the
2 is a cylinder drive circuit.

Next, the operation of this device will be explained.

Now, when a video signal as shown in FIG. 4A is input to the composite sync signal separation circuit 1, a composite sync signal as shown in FIG. A pulse of 10μSEC is output from the falling edge. The output signal of MMV21 of 10μSEC is
Type of Edge Trigger Flip Flop 22 CLO
When the CK input is applied and a composite synchronization signal is applied to the D input, a vertical synchronization signal as shown in Figure 4 is output. %H MM
V23 outputs a pulse of %H from the falling edge of the composite synchronization signal, and the output of MMV23 of %H is ANDed with the composite synchronization signal separated by the composite synchronization signal separation circuit 1.
The signal is input to the circuit 24. Furthermore, if the output signal of the D-type edge trigger flip-flop 22 is applied as the CLOCK input to the D-type edge trigger flip-flop 26, and the output signal of the AND circuit 24 is applied as the D input,
A signal as shown in Fig. 4G is output. This signal becomes a framing signal. When an EVEN signal as shown in FIG. 4A is input, an output signal as shown in FIG. 4G is obtained, and when an ODD signal as shown in FIG. 4H is input, an output signal as shown in FIG. 4H is obtained. An output signal as shown in Figure N is obtained. The output signal of the D-type edge trigger flip-flop 25 is input to the differentiating circuit 26, the output signal of the differentiating circuit 26 is used as the RESTE input of the % frequency dividing circuit 6, and the output signal of the D-type edge trigger flip-flop 22 is used as the input. The % frequency divided square wave is output from the % frequency dividing circuit 6. The square wave output from the % frequency divider circuit 6 and the square wave created from the PG pulse obtained by the rotation of the cylinder 7 are input to the phase detection circuit 11, and the error in the phase of the cylinder 7 is caused by the phase error between the two square waves. Controls the phase.

In this way, in this embodiment, one frame A□,
・When determining the even and odd fields that make up j, operate a non-trigger pull mono multivibrator that is triggered at the trailing edge of the horizontal synchronization signal and is longer than the %H period and shorter than the 1H period, and its output is Since even fields and odd fields are discriminated by sampling with a clock generated from a synchronization signal, highly accurate framing discrimination can be performed.

As described above, according to the present invention, the number of equalization pulses located before the vertical synchronization signal in the video signal is different from that of the EVEN signal.
Focusing on the fact that the DD signal is different, we digitally process the composite synchronization signal and improve the instability of framing discrimination due to temperature changes, so we can make stable framing discrimination even with temperature changes. It is possible to perform editing with high precision and high quality.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the main parts of a conventional magnetic recording/reproducing device, Fig. 2 is a waveform diagram of input/output signals of each part of the same device, and Fig. 3 is a magnetic recording/reproducing bag 1, which is an embodiment of the present invention. FIG. 4 is a block diagram of the main parts at a 1° position, and a waveform diagram of input/output signals of each part of the device. 1...Composite synchronization signal separation circuit, 2...Vertical synchronization 9/, - signal separation circuit, 3...400μSEC mono multivibrator, 4...10μSEC mono multivibrator, 6...AND circuit, 6.
...% frequency divider circuit, 7... cylinder, 8.
PG amplification circuit, 9 DELAY circuit, 10 frequency divider circuit, 11 phase detection circuit, 12 cylinder drive circuit, 2
1...1oμSEC mono multivibrator, 22...D type edge trigger flip-flop, 23...%H mono multivibrator, 24...AND Circuit, 26...
D type edge trigger flip-flop, 26...
... Differential circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure (N)

Claims (2)

[Claims] (1) Reproducing means for reproducing a composite video signal that constitutes one frame with two fields, an even field and an odd field, recorded on a magnetic medium, and separation for separating a vertical synchronizing pulse and an equalization pulse from the composite video signal. a counting means for counting the number of the equalization pulses located before the vertical synchronization pulse; and a discrimination means for discriminating the type of field based on the output of the counting means. (2) A patent claim characterized in that the determining means is configured to determine whether the field type is an even field or an odd field by detecting whether the number of equalization pulses is an even number or an odd number. The magnetic recording and reproducing device according to item 1.