JPS58211231A - 情報処理システム - Google Patents

情報処理システム

Info

Publication number
JPS58211231A
JPS58211231A JP57093811A JP9381182A JPS58211231A JP S58211231 A JPS58211231 A JP S58211231A JP 57093811 A JP57093811 A JP 57093811A JP 9381182 A JP9381182 A JP 9381182A JP S58211231 A JPS58211231 A JP S58211231A
Authority
JP
Japan
Prior art keywords
lsi
data
mpu
circuit
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57093811A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6259823B2 (enrdf_load_stackoverflow
Inventor
Kazutoshi Yoshizawa
吉澤　和俊
Yukio Maehashi
幸男 前橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57093811A priority Critical patent/JPS58211231A/ja
Publication of JPS58211231A publication Critical patent/JPS58211231A/ja
Publication of JPS6259823B2 publication Critical patent/JPS6259823B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
JP57093811A 1982-06-01 1982-06-01 情報処理システム Granted JPS58211231A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57093811A JPS58211231A (ja) 1982-06-01 1982-06-01 情報処理システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57093811A JPS58211231A (ja) 1982-06-01 1982-06-01 情報処理システム

Publications (2)

Publication Number Publication Date
JPS58211231A true JPS58211231A (ja) 1983-12-08
JPS6259823B2 JPS6259823B2 (enrdf_load_stackoverflow) 1987-12-12

Family

ID=14092780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57093811A Granted JPS58211231A (ja) 1982-06-01 1982-06-01 情報処理システム

Country Status (1)

Country Link
JP (1) JPS58211231A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6148058A (ja) * 1984-08-14 1986-03-08 Mitsubishi Electric Corp マイクロプロセツサのバスライン制御回路

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519525A (ja) * 1974-07-12 1976-01-26 Matsushita Electric Works Ltd Konpyuutanyushutsuryokusetsuzokuhoshiki

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519525A (ja) * 1974-07-12 1976-01-26 Matsushita Electric Works Ltd Konpyuutanyushutsuryokusetsuzokuhoshiki

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6148058A (ja) * 1984-08-14 1986-03-08 Mitsubishi Electric Corp マイクロプロセツサのバスライン制御回路

Also Published As

Publication number Publication date
JPS6259823B2 (enrdf_load_stackoverflow) 1987-12-12

Similar Documents

Publication Publication Date Title
US4503490A (en) Distributed timing system
US4615017A (en) Memory controller with synchronous or asynchronous interface
US6463488B1 (en) Apparatus and method for testing master logic units within a data processing apparatus
US5119480A (en) Bus master interface circuit with transparent preemption of a data transfer operation
US5416909A (en) Input/output controller circuit using a single transceiver to serve multiple input/output ports and method therefor
EP0062431B1 (en) A one chip microcomputer
JPH07210413A (ja) 集積回路
EP0786726A2 (en) Interrupt sharing technique for PCMCIA cards
US7249209B2 (en) System and method for dynamically allocating inter integrated circuits addresses to multiple slaves
US5201051A (en) Apparatus for interrupt detection and arbitration
KR940000289B1 (ko) 프로그래머블 콘트롤러(programmable controller)
US7054979B2 (en) Method and apparatus for routing configuration accesses from a primary port to a plurality of secondary ports
US4482949A (en) Unit for prioritizing earlier and later arriving input requests
JPS586177B2 (ja) インタ−フエ−ス回路の選択システム
US4594654A (en) Circuit for controlling external bipolar buffers from an MOS peripheral device
US6128691A (en) Apparatus and method for transporting interrupts from secondary PCI busses to a compatibility PCI bus
JPS58211231A (ja) 情報処理システム
US5371863A (en) High speed processor bus extension
US4180855A (en) Direct memory access expander unit for use with a microprocessor
US20040123005A1 (en) Four-phase handshake arbitration
US6934782B2 (en) Process and apparatus for managing use of a peripheral bus among a plurality of controllers
JPS6242306B2 (enrdf_load_stackoverflow)
US5872937A (en) System for optimizing bus arbitration latency and method therefor
JPS648384B2 (enrdf_load_stackoverflow)
US6868457B2 (en) Direct memory access controller, direct memory access device, and request device