JPS58209221A - Analog-digital converter - Google Patents

Analog-digital converter

Info

Publication number
JPS58209221A
JPS58209221A JP9329382A JP9329382A JPS58209221A JP S58209221 A JPS58209221 A JP S58209221A JP 9329382 A JP9329382 A JP 9329382A JP 9329382 A JP9329382 A JP 9329382A JP S58209221 A JPS58209221 A JP S58209221A
Authority
JP
Japan
Prior art keywords
circuit
output
voltage
waveform
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9329382A
Other languages
Japanese (ja)
Inventor
Takenori Akaike
赤池 武則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teraoka Seiko Co Ltd
Original Assignee
Teraoka Seiko Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teraoka Seiko Co Ltd filed Critical Teraoka Seiko Co Ltd
Priority to JP9329382A priority Critical patent/JPS58209221A/en
Publication of JPS58209221A publication Critical patent/JPS58209221A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/50Analogue/digital converters with intermediate conversion to time interval

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To improve the accuracy and the functional, performance, by detecting an average voltage from an output voltage of a bridge circuit by a control circuit in the proportional comparison system. CONSTITUTION:Four sides constituting the bridge circuit A are provided with resistors R1, R2, R3 and R4 being a distortion detecting element respectively. Output terminals (a), (b) are connected to a control circuit B via a switch E and an amplifier 1. When a load is applied to a load cell, the resistors R1, R2 of the circuit A change according to the load, voltages Va, Vb at the output terminals (a), (b) are changed and outputted to a circuit B for output time t1, t2 controlled with the switch E. The circuit B detects an average voltage Vc, of the Va, Vb. A comparison circuit D outputs each period when the Vc crossing with a waveform of one period of the sawtooth waveform based on the said waveform outputted from an oscillating circuit C. The switch E switches the two output terminals alternately with this output.

Description

【発明の詳細な説明】 本発明にブリッジ回路における変動量を検出してデジタ
ル魚に変換するA−D変換装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an A/D converter that detects the amount of variation in a bridge circuit and converts it into a digital fish.

従来のA−Di換装置、例えばロードセルを使用した秤
装置においては、ブリッジ回路の2つの出力端から出力
される差電圧を直接に2i&分方式などを使った積分回
路によりデジタル蓋に変換する方式で8シ、この従来方
式においてはブリッジ回路に加える供給電源、すなわち
A−D変換装置の基準電源の電源変動がA−D変換出力
に影響を及ぼしてしまうので該電源変動を極力小さくし
なければならない。
In conventional A-Di converters, for example weighing devices using load cells, the differential voltage output from the two output terminals of a bridge circuit is directly converted into a digital lid using an integrating circuit using the 2i & minute method. In this conventional method, fluctuations in the power supply applied to the bridge circuit, that is, the reference power supply of the A-D converter, affect the A-D conversion output, so it is necessary to minimize the power fluctuations as much as possible. It won't happen.

又、積分用のコンデンサは誘電吸収又は漏れ電流などが
原因となり出力の直線性を低下させ、さらにカウント用
のクロック発振器の発振周波数の発振N度が要求される
等の欠点がある。
Further, the integrating capacitor has drawbacks such as dielectric absorption or leakage current, which deteriorates the linearity of the output, and furthermore, the oscillation frequency of the counting clock oscillator requires an oscillation frequency of N degrees.

上記の欠点を解消するためには高M度の高価な部品、例
えばオペレーションアンプ、積分コンデンサ、規準電源
などを使用しなければならないとともにアナログ回路の
調整が必要となシ、調整性に劣る不具合を生ずることと
なる。
In order to eliminate the above drawbacks, it is necessary to use expensive components with a high M degree, such as operational amplifiers, integrating capacitors, reference power supplies, etc., and it is also necessary to adjust the analog circuits, which leads to problems with poor adjustability. will occur.

本発明は斯る従来不具合を解消して、精度及び機能性に
優れた安価なA−D変換装置を提供せんとすることを目
的とするもので、歪検出素子を有し荷重等を抵抗値の変
化として検出するブリクジ回路と、前記回路の2つの出
力端にスイッチを介して接続しブリッジ回路の出力電圧
から平均電圧を検出し出力する制御回路と、鋸讃状阪形
を出力する発振回路と、前記制御回路から出力する平均
電圧及び発振回路から出力する鋸歯状波形に基づいて電
圧レベルの時間比率を出力する比較回路と、比較回路の
出力により前記2つの出力端を交互に切換える前記スイ
ッチとよシ々ることを%黴とする。
It is an object of the present invention to eliminate such conventional problems and provide an inexpensive A-D converter with excellent accuracy and functionality. a control circuit connected to two output terminals of the circuit via a switch to detect and output an average voltage from the output voltage of the bridge circuit, and an oscillation circuit that outputs a sawtooth waveform. and a comparison circuit that outputs a time ratio of voltage levels based on the average voltage output from the control circuit and the sawtooth waveform output from the oscillation circuit, and the switch that alternately switches between the two output terminals based on the output of the comparison circuit. Toyoshishi is called % mold.

上記制御回路から出力する平均電圧とは、ブリッジ回路
の2つの出力端から出力する出力電圧の単純平均値をい
うものではなく、積分回路等によシ各出力電圧と出力時
間を乗算した演算値の平均値をいう。
The average voltage output from the above control circuit does not mean the simple average value of the output voltages output from the two output terminals of the bridge circuit, but the calculated value obtained by multiplying each output voltage and output time by an integrating circuit, etc. means the average value of

本発明の実施例を図面によシ説明すれば、第1図は装置
のブロック図を示し、図において(4)はブリッジ回路
、俤)は制御回路、(C)は発振回路、(2)は比較回
路、(6)はスイッチ、CF′)はカウンタである。
To explain an embodiment of the present invention with reference to the drawings, FIG. 1 shows a block diagram of the device, in which (4) is a bridge circuit, (5) is a control circuit, (C) is an oscillation circuit, (2) is a comparison circuit, (6) is a switch, and CF') is a counter.

ブリッジ回路(4)は例えば秤のロードセルであシ、該
回路を構成する4辺の各辺に夫々、歪検出素子である抵
抗(RzXRxXR2XRz)を設けである。
The bridge circuit (4) is, for example, a load cell of a scale, and a resistor (RzXRxXR2XRz), which is a strain detection element, is provided on each of the four sides constituting the circuit.

ブリッジ回路(4)の出力端(a)(b)…1にはスイ
ッチ(匂を介在させ、このスイッチ(ト)をブrして谷
出力端(a)Φ)を制御回路(B)に接続する。
Output ends (a), (b)...1 of the bridge circuit (4) are equipped with a switch (g), and the valley output ends (a) Φ) are connected to the control circuit (B). Connecting.

尚、図の(1)tj増幅器である。Note that this is the (1) tj amplifier in the figure.

ブリッジ回路(4)の接続点(c)(d)には足電圧源
(2)を印加した場合を示し、その印加電圧(7)によ
シ出力端(a)(b)にu I = V/R□+ R2
なる一定の電流カニ流れる。
The case where the foot voltage source (2) is applied to the connection points (c) and (d) of the bridge circuit (4) is shown, and the applied voltage (7) causes the output terminals (a) and (b) to have u I = V/R□+ R2
A constant current will flow through the crab.

ロードセルに荷重が加わるとブリッジ回路(4)はその
抵抗(R1) (R2)が荷重に応じて変化し、これに
よシ出力端(a)(b)の出力電圧(Va )(Vb 
)が変化し、前記スイッチ(6)によ多制御される出力
時間(tlXt2)のあいだ該電圧(Va )(Vb 
)を制御回路(B)へ出力する。
When a load is applied to the load cell, the resistances (R1) (R2) of the bridge circuit (4) change according to the load, and this causes the output voltages (Va) (Vb) of the output terminals (a) and (b) to change.
) changes, and the voltage (Va ) (Vb
) is output to the control circuit (B).

制御回路の)は第2図又は第3図に示す如き積分要素(
3Jを含む回路であって、該要素(3)中の、(4)は
積分用コンデンサ、(5)は抵抗である。
) of the control circuit is an integral element (
3J, in which element (3), (4) is an integrating capacitor, and (5) is a resistor.

又、第2図及び第3図における(7)は微分回路、(8
)は比例回路でろり、(6)は増幅器である。
Also, (7) in Figures 2 and 3 is a differential circuit, and (8
) is a proportional circuit, and (6) is an amplifier.

上記制御回路(B)は前記ブリッジ回!M!(4)の出
力端(a)(b)から出力する出力電圧(Va ) (
Vb )よシその平均電圧(vc)を検出し出力するも
のである。
The control circuit (B) is the bridge circuit! M! (4) Output voltage (Va) output from output terminals (a) and (b) (
Vb) and its average voltage (vc) is detected and output.

すなわち、回路中)の積分要素(3)によう、入力され
た出力電圧(Va XVb )と出力時間(tl)(C
2)の策算値(va−tl、■b−t2)が等しくなっ
たところの電圧(vc)t−検出し、それを平均電圧と
して出力する。
In other words, the input output voltage (Va XVb ) and output time (tl) (C
2) The voltage (vc)t- at which the calculated values (va-tl, b-t2) become equal is detected and outputted as an average voltage.

制御回路(B)中における前記微分要素(7)、比例回
路(8)は前記平均電圧(Vc )の収束を早める機能
を有する。
The differential element (7) and the proportional circuit (8) in the control circuit (B) have a function of accelerating the convergence of the average voltage (Vc).

発振回路(C)は第4図に示す鋸歯状の波形(c)を出
力し比較回路(2)に入力させるもので、その1波形の
周期を(t)(t = t1+tz )とする。
The oscillation circuit (C) outputs a sawtooth waveform (c) shown in FIG. 4 and inputs it to the comparison circuit (2), and the period of one waveform is (t) (t=t1+tz).

比較回路の)は制御回路中)及び発振回路(C) K接
続し、両回路ω)(C)より送信される平均電圧(VC
)と鋸歯状波形(c)とを合成比較しく第4図)、これ
によシ1波形(c)の周期(1)において、波形(c)
の初期点(C1)から平均電圧(Vc )が波形と交差
するレベル時点(C2)までの時間(tl)及び前記晩
点(C2)から終期点、すなわち次の波形の初期点(C
1)までの時間(C2)を検出し時間比幅信号ψ)とし
て出力する。
) of the comparison circuit is connected to the control circuit (in the control circuit) and the oscillation circuit (C), and the average voltage (VC
) and the sawtooth waveform (c) for comparison (Fig. 4), so that at period (1) of waveform (c), waveform (c)
The time (tl) from the initial point (C1) to the level point (C2) where the average voltage (Vc) crosses the waveform, and from the late point (C2) to the final point, that is, the initial point (C2) of the next waveform.
1) is detected and output as a time ratio width signal ψ).

すなわち、比較回路の)はブリッジ回路(4)の抵抗変
化として出力される平均電圧(VC)をそのレベルに応
じた各時間(t1+ tz)としてに挨し出力するもの
でるる。
That is, the comparator circuit (2) outputs the average voltage (VC) outputted as a resistance change of the bridge circuit (4) at each time (t1+tz) corresponding to its level.

スイッチ(6)は前記比較回路(ロ)の時間比幅信号ψ
)の出力する毎に切換動作をし、これによシブリッジ回
路(4)の出力端(a)(b)を順次交互に制御回路0
3)に検出された前記時間(tl)(C2)宛接続して
、その゛間出力電圧(Va )(Vb)を出力させるよ
うにする。
The switch (6) receives the time ratio width signal ψ of the comparison circuit (b).
), the output terminals (a) and (b) of the bridge circuit (4) are sequentially and alternately switched to the control circuit 0.
3) is connected to the time (tl) (C2) detected in step 3), and the output voltage (Va) (Vb) is output during that time.

而して、ロードセルに荷重が加わると上記の出力動作を
繰返すが、電圧変化が平衡状態に達した時には、制御回
路ω)に於いて次式、 (R−ΔR) I−h = (R十ΔR)I・C2の算
式が成立する。尚、R=R1+R2,ΔRは抵抗変化量
である。
When a load is applied to the load cell, the above output operation is repeated, but when the voltage change reaches an equilibrium state, the control circuit ω) calculates the following equation, (R-ΔR) I-h = (R + The formula ΔR)I·C2 is established. Note that R=R1+R2, ΔR is the amount of resistance change.

上式より、ΔR=R弓(tltz)/R−I(tl+t
z)=(L+ −tz >/ t  ・・・・・・・(
A式)すなわち、ロードセルにかかる荷重は比較回路C
D)から出力する時間(tIXtz)の関数として変換
されることと々る。
From the above formula, ΔR=R bow(tltz)/R−I(tl+t
z)=(L+ -tz >/t ・・・・・・・・・(
Formula A) In other words, the load applied to the load cell is determined by the comparator circuit C.
D) as a function of the output time (tIXtz).

上記時間(tl Xt2)の時間比幅信号Φ)はカウン
タC)によシ時間(tlXt2)が夫々計数され、その
後に演算回路(−示せず)VCよシ上記A式に基づいた
演算が行なわれ、その演算値を基に、表示回路に荷重と
して表示される。
The time ratio width signal Φ) of the above time (tl Based on the calculated value, it is displayed as a load on the display circuit.

尚、上記実施例は定電圧源(2)を供給電源とした場合
を示したが、該電源に定電流源を使用する場合も同様に
変換動作管する。
Although the above embodiment has shown the case where the constant voltage source (2) is used as the power supply, the conversion operation is similarly carried out when a constant current source is used as the power source.

本発明は鋲止の如く構成し、制御回路によシブリッジ回
路の出力電圧から平均電圧を比例比較方式によって検出
するようにしたので、電圧又は電流の変動要因が互いに
相殺され、出力精度を高めることができる。
The present invention is configured like a rivet, and the control circuit detects the average voltage from the output voltage of the sibridge circuit using a proportional comparison method, so that fluctuation factors in voltage or current cancel each other out, improving output accuracy. Can be done.

又、比較4回路の出力をブリッジ回路の出力端にフィー
ドバックさせスイッチの切換え動作をさせるようにした
ので、制御回路におけるコンデンサの誘電吸収が補正さ
れ、出力の直線性が保持され、さらにクロックの発振a
度は鋸菌状歯形の1周期以内で安定していれば温度変化
等によって長時間に2ける変化においてはA−D変換精
度には影智しない。
In addition, the outputs of the four comparison circuits are fed back to the output end of the bridge circuit to operate the switch, so the dielectric absorption of the capacitor in the control circuit is corrected, the linearity of the output is maintained, and the clock oscillation is a
As long as the degree is stable within one period of the serrated tooth shape, changes over a long period of time due to temperature changes or the like will not affect the A-D conversion accuracy.

従って、変換装置の精度を高め、高価な補正部品を不要
にして高精度、安価な装置を提供し得る。
Therefore, it is possible to improve the accuracy of the conversion device, eliminate the need for expensive correction components, and provide a highly accurate and inexpensive device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明装置のブロック図、第2図は制御回路図
、箱3図は変形例の制御回路図、taJ4図は比較回路
の動作を示す波形図である。 図中、(4)はブリッジ回路、(ロ))申)は出力端、
(R1)(R2)は抵抗、ω)は制御回路、(C)は発
振回路、[F])は比較回路、[F])はスイッチ、(
VaXVb)は出力電圧、(VC)は平均電圧、(1)
は波形周期、(tx )(t2)は電圧レベルの時間比
率である。 手続補正書 昭和57年 7月?臼 1、事件の表示 昭和57年特許願第93293号 2、発明の名称 A−D変換装置 3、補正をする者 事件との関係     特 許 出 願 人氏名(名称
) 株式会社寺岡精工 4、代理人 住 所  東京都文京区白山5丁目14番7号昭和  
年  月  日 6、補正の対象 明細書全文及び図面企図 7、補正の内容
FIG. 1 is a block diagram of the device of the present invention, FIG. 2 is a control circuit diagram, box 3 is a control circuit diagram of a modified example, and taJ4 is a waveform diagram showing the operation of the comparison circuit. In the figure, (4) is the bridge circuit, (b)) is the output terminal,
(R1) (R2) are resistors, ω) is a control circuit, (C) is an oscillation circuit, [F]) is a comparison circuit, [F]) is a switch, (
VaXVb) is the output voltage, (VC) is the average voltage, (1)
is the waveform period, and (tx)(t2) is the time ratio of the voltage level. Procedural amendment July 1982? Mortar 1, Indication of the case Patent Application No. 93293 filed in 1988 2, Name of the invention A-D converter 3, Person making the amendment Relationship to the case Patent applicant Name (name) Teraoka Seiko Co., Ltd. 4, Agent Address: 5-14-7 Hakusan, Bunkyo-ku, Tokyo Showa
Year Month Day 6, Full text of the specification subject to amendment and drawing plan 7, Contents of amendment

Claims (1)

【特許請求の範囲】[Claims] 歪検出素子を有し荷重を抵抗値の変化として検出するブ
リッジ回路と、前記回路の2つの出力端にスイッチを介
して接続しブリッジ回路の出力電圧から平均電圧を検出
し出力する制御回路と、鋸歯状波形を出力する発振回路
と、前記制御回路から出力する平8電圧及び発振回路か
ら出力する鋸歯状波形に基づいて前記波形1周期におけ
る電圧レベルと波形との又差する間の各時間を出力する
比較回路と、比較回路の出力により前記2つの出力端を
交互に切換える前記スイッチとよりなるA−D変換装置
a bridge circuit having a strain detection element and detecting load as a change in resistance value; a control circuit connected to two output ends of the circuit via a switch to detect and output an average voltage from the output voltage of the bridge circuit; An oscillation circuit that outputs a sawtooth waveform, and each time between the voltage level and the waveform in one cycle of the waveform, based on the Height 8 voltage output from the control circuit and the sawtooth waveform output from the oscillation circuit. An A/D converter comprising a comparison circuit that outputs an output, and the switch that alternately switches the two output terminals according to the output of the comparison circuit.
JP9329382A 1982-05-31 1982-05-31 Analog-digital converter Pending JPS58209221A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9329382A JPS58209221A (en) 1982-05-31 1982-05-31 Analog-digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9329382A JPS58209221A (en) 1982-05-31 1982-05-31 Analog-digital converter

Publications (1)

Publication Number Publication Date
JPS58209221A true JPS58209221A (en) 1983-12-06

Family

ID=14078331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9329382A Pending JPS58209221A (en) 1982-05-31 1982-05-31 Analog-digital converter

Country Status (1)

Country Link
JP (1) JPS58209221A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5255463A (en) * 1975-10-31 1977-05-06 Fairchild Camera Instr Co Single slope detection analoggtoodigital converter
JPS566528A (en) * 1979-06-28 1981-01-23 Nec Corp Signal converter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5255463A (en) * 1975-10-31 1977-05-06 Fairchild Camera Instr Co Single slope detection analoggtoodigital converter
JPS566528A (en) * 1979-06-28 1981-01-23 Nec Corp Signal converter

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