JPS58209178A - Josephson integrated circuit - Google Patents
Josephson integrated circuitInfo
- Publication number
- JPS58209178A JPS58209178A JP57092803A JP9280382A JPS58209178A JP S58209178 A JPS58209178 A JP S58209178A JP 57092803 A JP57092803 A JP 57092803A JP 9280382 A JP9280382 A JP 9280382A JP S58209178 A JPS58209178 A JP S58209178A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- electrode
- josephson junction
- current ratio
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims abstract description 3
- 239000000523 sample Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 abstract description 5
- 238000002347 injection Methods 0.000 abstract description 3
- 239000007924 injection Substances 0.000 abstract description 3
- 206010027146 Melanoderma Diseases 0.000 abstract 3
- 230000004075 alteration Effects 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/12—Josephson-effect devices
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
(1)発明の技術分野
本発明は、ジョセフソン接合論理ゲートに係り、特に共
通の構造を有し、配線接続等の変更のみによυ異なる論
理動作が可能なジョセフソン−理ゲートと、これを用い
る論理回路に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to Josephson junction logic gates, and in particular to Josephson junction logic gates that have a common structure and can perform different logic operations by changing wiring connections, etc. This invention relates to logic gates and logic circuits using them.
(2)従来技術と問題点
従来提案された可変しきい値特性型菫子干渉素子として
は、臨界電流比は共通で、バイアス・1g号・オフセッ
ト−流等の配線接続のみの変更により、論理積・論理和
の製作を選択していた。ところで、論理積と論理和とで
は動作マージンが最大となる臨界電流比が異なるので、
一方の動作マージンが犠牲となっていた。(2) Prior art and problems The conventionally proposed variable threshold characteristic type violet interference elements have a common critical current ratio, and the logic I had chosen to create a product/disjunction. By the way, the critical current ratio at which the operating margin is maximized is different for AND and OR, so
On the other hand, the operating margin was sacrificed.
(3)発明の目的
本発明目的は、インダクタンスや電極等の大部分の構造
が共通であって、1を−〜2)―の変更のみ太
で、臨界11哩比を容易に変更可能とするものである0
(4)発明の構成
本発明は、ジョセフソノ髪合形成のための絶縁層の窓開
は個数を変更するか、あるいは、配線接続の変更により
ジョセフソン接合の接続位置を変更することにより、
臨界電流比を変更し、異なる論理動作を各々に適した臨
界電流比で実現できるようにし、しかも、その変更が1
層〜2層のホトマスク変更のみで容易に行なえるように
したものである。(3) Purpose of the Invention The purpose of the present invention is to have most structures such as inductance and electrodes in common, and to make it possible to easily change the critical 11 ratio by only changing 1 to 2). (4) Structure of the Invention The present invention provides a method for changing the number of openings in the insulating layer for Josephson joint formation, or changing the connection position of the Josephson junction by changing the wiring connection. According to
By changing the critical current ratio, different logic operations can be realized with the critical current ratio suitable for each, and the change is 1
This can be easily done by simply changing the photomask for one to two layers.
(5)発明の実抛例
第1図は、町変しきい値特性型童子干渉素子の等価回路
を示す。2つの接合J+、Jtの臨界電流比が、1:3
である時(第1図(a))動作マージンの大きな論理和
となる。IGはバイアス′に流、IHlとI)itは信
号電流である。一方第1図(b)にボす繊理積は、J8
.J4の臨界′直流比が1.1の場合に動作マージンが
大きい。なお、LIo積は1.4Φ0(Φ0は磁束量子
2.07 X 10−”Wb )程度であって、第1図
(b)のIH,にはΦ、/2Lなるオフセシ)[流を流
す。(5) Practical Example of the Invention FIG. 1 shows an equivalent circuit of a Doji interference element of the Machin threshold characteristic type. The critical current ratio of the two junctions J+ and Jt is 1:3
When (FIG. 1(a)), the operation margin becomes a large logical sum. IG flows through bias', and IHl and I)it are signal currents. On the other hand, the fiber product shown in Figure 1(b) is J8
.. When the critical DC ratio of J4 is 1.1, the operating margin is large. Note that the LIo product is approximately 1.4Φ0 (Φ0 is a magnetic flux quantum of 2.07 x 10-''Wb), and IH in FIG. 1(b) has an offset of Φ, /2L.
第2図は本発明の一実施例を示す図であり、1゜1′は
各々インダクタンスT”、τLを構成する下部電極でち
ゃ、その上に図中省略した絶縁層5iOKより絶縁され
たコントロールm[、Lr配し、各々1.1′と磁界結
合している。#絶縁層Vこは図中黒点2で示す窓開けを
行ない、この部分がジョセフソン接合となるが、第2図
(a)に示すようにその個数を1′側に3個、1111
に1個とすれば、臨が直流比を1:3とすることが出来
る。一方、@2図(b)に示すように2個ずつにする場
合は臨界’ft Mt比は1:1となる。3は下部電極
であって、Si0層に開けた窓4を介して汝地される。FIG. 2 is a diagram showing an embodiment of the present invention, in which 1° and 1' are lower electrodes constituting inductances T'' and τL, respectively, and a control panel insulated by an insulating layer 5iOK (not shown in the figure) on top of the lower electrodes. m[, Lr are arranged, and are magnetically coupled to 1.1' respectively. #The insulating layer V is opened with a window shown by the black dot 2 in the figure, and this part becomes a Josephson junction, but as shown in Figure 2 ( As shown in a), the number is 3 on the 1' side, 1111
If there is one in each case, the direct current ratio can be set to 1:3. On the other hand, when using two pieces at a time as shown in Figure 2 (b), the critical 'ft Mt ratio is 1:1. 3 is a lower electrode, which is applied through a window 4 opened in the Si0 layer.
5はバイアス電流Icを流す端子であり、6,7は信号
電流注入端子である。5 is a terminal through which a bias current Ic flows, and 6 and 7 are signal current injection terminals.
第3図には他の実施例を示す。接合は1′側に2個、1
側に1個作り、さらに下ff:l ’+[、極1,1’
と分離された他の下部電極11上に、さらvc i (
+4の接合10を作っておく。以上を共通構ゴ貨として
、第3図(&)に示すように1′と11を配線12によ
り接続すると、1′側に31固の接合が接続されたこと
になり、臨界直流比1′i3 : 1となる。43図(
b)に示すように1:11を配線13により接続すれば
、臨界′直流比1:1が得られる。FIG. 3 shows another embodiment. There are 2 connections on the 1' side, 1
Make one on the side and further lower ff: l'+[, pole 1, 1'
Further, on the other lower electrode 11 separated from vc i (
Create +4 junction 10. Using the above as a common structure, if 1' and 11 are connected by wiring 12 as shown in Figure 3 (&), a 31-pin junction is connected to the 1' side, and the critical DC ratio is 1' i3: becomes 1. Figure 43 (
If 1:11 is connected by wiring 13 as shown in b), a critical DC ratio of 1:1 can be obtained.
(6)発明の効果
本発明によれば可変しきいl’jjj特性型曾特性型素
子干渉素子クタンスや電極等の構造が共通であって、1
1−〜21−のホトマスクの変更のみで臨界電流比を容
易に変更可能とし、異なる@埋動作に対してもそれぞれ
最大の1作マージンを得ることが出来る0
4.1囲の貨幣なd明
第1図は可変しきい値付性型鍵子干渉素子の等価回路を
示す図、嬉2図は本発明の一夷I・1刈を示す図、第3
し[は本発明の他の実廁例を示す図である。1こ\で1
,1′は童子干渉素子のループインダクタンス、2はジ
ョセフソン朕合、3id上部旺極、4は接地面との接続
部分、5は論理オ1.I動作のだめのバイアス端子、6
.7は論理積動作のための16号KK注入端子、8.9
は論理和動作のための1g号用磁界結合線でありかつ論
理種動作のためのオフセット電流線、10は分離された
下部r1i、惨上に形成されたジョセフソン接合、11
はこの分離された下部電極、12.13は分離された下
部電極をルーズインダクタンス1あるいは1′と接続す
るための配線で、Jll J2− Js、J4はジョセ
フソン接合、各1 3 In I。(6) Effects of the Invention According to the present invention, the variable threshold l'jjj characteristic type great characteristic type element interference element has a common structure such as cotance and electrodes.
The critical current ratio can be easily changed just by changing the photomasks of 1- to 21-, and the maximum one-crop margin can be obtained for different @embedding operations. Fig. 1 is a diagram showing an equivalent circuit of a variable threshold type key interfering element, Fig. 2 is a diagram showing the first part of the present invention, and Fig. 3
[FIG. 7] is a diagram showing another practical example of the present invention. 1 in 1
, 1' is the loop inductance of the Doji interference element, 2 is the Josephson connection, 3id upper pole, 4 is the connection part with the ground plane, and 5 is the logic voltage 1. Bias terminal for I operation, 6
.. 7 is No. 16 KK injection terminal for AND operation, 8.9
is a magnetic field coupling line for No. 1g for logical sum operation and an offset current line for logic type operation; 10 is the separated lower part r1i; Josephson junction formed on the top;
is this separated lower electrode, 12.13 is a wiring for connecting the separated lower electrode to the loose inductance 1 or 1', Jll J2-Js, J4 are Josephson junctions, each 1 3 In I.
々の臨界′直流値はユl IHl 21.2 で
あり、4
Lは計子干渉累子のループインダクタンス+I+;はバ
イアス電流+ IH,l IH,l IAI IBは
侶弓イ匝。The critical DC value of each is 21.2, where L is the loop inductance +I+ of the meter interference resistor;
IH,はオフセット′を流。IH, flows offset'.
Claims (1)
し、ジョセフソン接合の窓開けの変更あるいは、ジョセ
フノン接合電極の接続の変更により、臨界電流比を変更
することを%徴とするジッセフソン東撰回路1・For different logical operations of quantum interference probes with variable threshold characteristics, the Gissefson method is characterized by changing the critical current ratio by changing the opening of the Josephson junction or by changing the connection of the Josephson non-junction electrodes. Tosen circuit 1・
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57092803A JPS58209178A (en) | 1982-05-31 | 1982-05-31 | Josephson integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57092803A JPS58209178A (en) | 1982-05-31 | 1982-05-31 | Josephson integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58209178A true JPS58209178A (en) | 1983-12-06 |
Family
ID=14064567
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57092803A Pending JPS58209178A (en) | 1982-05-31 | 1982-05-31 | Josephson integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58209178A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6188576A (en) * | 1984-10-05 | 1986-05-06 | Yokogawa Hokushin Electric Corp | Thin-film squid |
-
1982
- 1982-05-31 JP JP57092803A patent/JPS58209178A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6188576A (en) * | 1984-10-05 | 1986-05-06 | Yokogawa Hokushin Electric Corp | Thin-film squid |
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