JPS58208994A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain efficient data rewriting, by performing erase and rewrite only to a storage element where the necessity of data rewrite is discriminated by means of the comparison between a written data and a data to be written in. CONSTITUTION:A data written in an ROM cell electrically rewritable of a cell matrix 1 and a data to be written in via an I/O buffer 2 are compared at comparison circuits 4a, 4b-, and when they are dissident, it is discriminated that the data rewrite is required. The data erase/rewrite is done for the corresponding ROM cell of the matrix 1 with a write signal generating circuit 5 and an erase signal generating circuit 6 in response to this discrimination signal. Thus, it is not required to rewrite after lots of ROM cells are erased in byte unit, and the data rewrite is done for a required cell only efficiently and quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention is directed to a place where stored data can be electrically rewritten. !
The present invention relates to a nonvolatile semiconductor memory device whose main body is an EPROM.

[Technical background of the invention and its problems]

Read-only memories, so-called ROMs, are widely used for various data processing. In addition, Kokuchika has developed an E PROM (E
Electrical Erasable Progra
mpbleROM) has been developed and is becoming widely used.

However, conventionally, this type of E2FROM generally has a first
As shown in the figure, a cell matrix, a cell matrix 1, which is a storage device body formed by arranging a plurality of storage cells in a matrix,
This cell matrix, a selection circuit (not shown) that selects the memory cell of the cell matrix 1, an I10 buffer circuit 2 that transmits and receives data between the selected memory cell and the outside, and controls data rewriting of the selected memory cell. The W/E switching circuit 3 includes a W/E switching circuit 3. This W/FJ switching circuit 3 is
For example, the data in the memory cell is changed from 1# to 0'' to write the data, and 1 data is changed from '0'' to 1#.
” to delete it.

When rewriting data in a g2FROM having such a configuration, that is, a nonvolatile semiconductor memory device, first select a memory cell at the target address for data rewriting, write data "1" to that cell, and erase it. 1. A 0" write process is performed according to the new data to be replaced. Such data rewrite process is performed in the same way when performing byte units consisting of several bits of cells. First, all selected cells are After erasing the data, new data is written.

In other words, the conventional device requires a two-step data rewriting process: erasing all bit data and writing desired data. Moreover, since these treatments are usually performed using high voltage, they are quite cumbersome to handle.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and its purpose is to provide a practical method for efficiently rewriting data stored in a storage device body made of a non-volatile semiconductor memory element in a single process. An object of the present invention is to provide a nonvolatile semiconductor memory device with high performance.

[Summary of the invention]

The outline of the present invention is to compare data already written in a memory cell with data to be newly written to the memory cell, and determine whether it is necessary to rewrite the already written data. Data is written according to the judgment result ('J'→″′
0'') or erase data ('0''→''1'') selectively, thereby rewriting the data only in the memory cells that need to be rewritten by the l process. This is what I decided to do.

〔Effect of the invention〕

Therefore, according to the present invention, only the memory cells that require data rewriting are selected and the data 'Om' or 'Om' is written.
By erasing to 1# in a single process, rewriting can be performed, which is very simple. Therefore, it is possible to simplify its handling, which has great practical advantages.

[Actual sister example of invention]

Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 2 is a schematic configuration diagram of an embodiment of the device, in which 1 is a cell matrix, 2Vr I/Q no J, Tufa circuit, and 3 is a W
/E switching circuit. This device is characterized by a circuit that compares the data already written in the selected memory cell of the cell matrix 1 with the data to be newly written given via the 110-4 buffer circuit 2. 4m
, 4b to 4n are compared. In this example, the comparison circuits 4h, 4b to 4n compare each bit data in units of 1/bit. Each of the comparison circuits 4a, 4b to 4n compares the data R that has already been written in the memory cell with the new data D that needs to be written, and performs the logical processing as shown in Table 1. Data W1 indicating whether or not erasing is required, and data El indicating whether erasing is necessary are obtained.

Table 1 The data wt and FEI thus obtained by each of the comparison circuits 4a, 4b to 4n are applied to the write signal generation circuit 5 and the erase signal generation circuit 6, respectively. Upon receiving these signals, each of the signal generating circuits 5.
6 generates a write signal W and an erase signal E, and sends this to W.
/E switching circuit 3. . The W/E switching circuit 3 determines the convolution mode W and the erasure mode e by, for example, logical processing as shown in Table 2, and switches the mode for the cell matrix 1.

Table 2 Note that here, writing and erasing occurrences are detected in units of bytes, and the erasing mode is given priority over the writing mode. In addition, in order to perform such processing in units of 1/I, for example, the data W1. This is performed by performing logical OR processing on Ei in 1-byte units.

Therefore, for a memory cell in which the necessity of writing and erasing data has been detected (determined) in this way, the W/F,
After the switching circuit 3 is designated with the mode, a high voltage is applied to the high voltage generating circuit 7 to perform writing or erasing. In this case, data is erased from the cells that need to be erased among the memory cells that make up one byte, and then data is written to the cells that need to be written among the one-byte storage cells. will be held.

According to the device configured in this way, as shown in the timing chart of FIG. 3, data D to be rewritten is read in period TI and compared with data R that has already been written. Thereafter, in period T2, data is erased (Oj'
→゛°1″) 1- is executed. At this time, if there is no cell that requires erasing, data is written (l#
→゛0#) is executed. Furthermore, if data rewriting is not required, -switching rewriting processing is not performed. Thereafter, in the next period T3, the data is compared in the same manner as in the period T1, and in the period T4, a new write is performed to the cells that were not previously written by the erase operation.

Through the processing during these periods T1 to T4, data is erased or data is added to all cells that require data rewriting, and the data rewriting is completed.

In other words, data rewriting is performed by erasing or writing processing only for memory cells that require data rewriting.

As described above, according to the present invention, data can be rewritten efficiently in a short time without requiring the conventional two-step process of once erasing a memory cell and then writing new data. Moreover, for memory cells that require data rewriting, only 1. Since rewriting processing, that is, writing or erasing processing, is performed, it is very simple, and since a high voltage is used for such processing, restrictions on the number of times data can be rewritten to a memory cell (element) are greatly relaxed. However, the confectionery characteristics deteriorate each time data is changed by applying a high voltage, but since high voltage is applied only to cells that require one change of data, overall the performance of each cell is lower than the number of data changes. The number of data rewrites is reduced. Therefore, as described above, the practical advantage of increasing the number of rewrites is enormous.

Note that the present invention is not limited to the above embodiments and examples.

For example, you could make the embroidery mode take priority over the erase mode. Further, instead of byte unit T, data 1 may be changed in units of 1 bit. In this case, there is no need to give priority to the above mode. In summary, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional device, FIG. 2 is a schematic configuration diagram of an embodiment of the device of the present invention, and FIG. 3 is a timing diagram showing the operation mode of the embodiment device. 1...Cell matrix (storage device body), 2...
Ilo・9277 circuit, 3...W/E switching circuit, 4a
, 4b to 4n... Comparison circuit, 5... Write signal generation circuit, 6... Erase signal generation circuit, 7... High voltage generation circuit,

Claims (1)

[Claims] A storage device main body consisting of a plurality of non-volatile semiconductor storage elements that can electrically rewrite stored data, and data that has already been written to a selected storage element of this storage device main body and 1. a means for comparing the data with data to determine whether it is necessary to rewrite data already written in the memory element, and writing data only to the memory element that requires one change of data according to the result of this determination; or means for erasing data and rewriting data.