JP2000260188A - Control method for semiconductor memory and semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory which is inexpensive and of which the number of rewritable times is large. SOLUTION: A semiconductor memory 10 is provided with a flag bit 19 dividing a memory mat 11 of whole capacity R consisting of non-volatile semiconductor memory cells into plural blocks of size M and discriminating whether each block is rewritten or not, a block decoder 20 selecting a block being not yet rewritten as a block to be rewritten in accordance with a setting state of the flag bit 19, and a rewriting control logic circuit 18 erasing all blocks, that is, the whole memory mat 11 prior to initial rewriting after all blocks are rewritten, when it is assumed that the number of rewritable times is P and the number of division of the memory mat 11 is N, the large number of rewritable times of degree of P×N is realized by an inexpensive memory mat 11 of the number of rewritable times of degree of P.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a control technique thereof, and more particularly, to a semiconductor memory device having a nonvolatile semiconductor memory medium with a limited number of rewrites, and an information processing system incorporating them. Related to effective technology applied to

[0002]

2. Description of the Related Art For example, semiconductor storage devices (memory) include volatile memories (hereinafter referred to as category 1) typified by DRAMs and SRAMs, EPROMs (electrically rewritable, ultraviolet erasable nonvolatile memories), flash memories, and the like. A nonvolatile memory (hereinafter referred to as category 2) having a relatively small number of rewritable times (several hundred to tens of thousands of times) typified by a memory, and a large number of rewritable times (several million or more times)
(Electrically writable and erasable non-volatile memory; hereinafter referred to as category 3).

[0003]

In an application that does not require much storage capacity but requires a large number of rewritable times, a category 3 device is used, but the ratio of the memory to the chip area is considerably low. Nevertheless, the manufacturing process is complicated and requires two transistors per memory cell element (one transistor in the case of category 2), which necessitates the use of a costly EEPROM process. This is a factor that raises the price of the entire system.

An object of the present invention is to use a non-volatile semiconductor memory device having a small number of rewritable times as it is, and to increase the number of rewritable times without the need for a significant and difficult characteristic / process improvement. It is an object of the present invention to provide a semiconductor memory device that can be realized and a control technique thereof.

Another object of the present invention is to provide a semiconductor memory device capable of realizing a larger number of rewritable times at a low cost by using a nonvolatile semiconductor memory medium having a smaller number of rewritable times, and a control technique thereof. To provide.

Another object of the present invention is to provide a semiconductor memory device capable of easily realizing history management of stored information and a control technique thereof.

Another object of the present invention is to provide a semiconductor memory capable of improving availability by diverting an existing nonvolatile semiconductor memory device having a small number of rewritable times to an application requiring a higher number of rewritable times. It is an object of the present invention to provide an apparatus and a control technique thereof.

Another object of the present invention is to provide a semiconductor memory device which can realize a semiconductor memory device having a small storage capacity and a large number of rewritable times at a low cost, and a control technique therefor.

Another object of the present invention is to provide a semiconductor memory capable of realizing a semiconductor memory device having a large number of rewritable times while maintaining high reliability by using a nonvolatile semiconductor memory device having a small number of rewritable times. It is an object of the present invention to provide an apparatus and a control technique thereof.

Another object of the present invention is to reduce the cost of an information processing system incorporating a nonvolatile semiconductor memory device.
It is still another object of the present invention to provide a semiconductor memory device capable of improving reliability and performance, and a control technique thereof.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the present invention, a storage area of a nonvolatile semiconductor storage medium is logically or physically divided into a plurality of blocks, an address space assigned to each block is partially or completely overlapped, and data rewriting is performed. An erased block is selected and executed, and a plurality of blocks are erased prior to the first data rewrite after data rewrite is completed for all blocks.

More specifically, the present invention comprises a memory mat composed of a nonvolatile semiconductor storage medium or the like divided into N blocks, and a flag bit indicating the writing history in block units. The number of divisions N may be fixed or programmable.

In any of the above three categories of memories, the storage capacity and the size of the assigned address are the same in any case. That is, a device having a storage element capacity of 1 KByte has an additional element mounted for the purpose of repairing a defective element, testing, and the like.
The address space of te is allocated. In a flash memory, a memory mat is often divided into several blocks mainly as an erasing unit, but the relationship between a storage capacity and an assigned address is the same.

In the present invention, the assigned address is R / N = M bytes, where the total memory capacity is R bytes. When rewriting data, it is performed in M-byte units.
The flag bit of the block is also written at the same time. In rewriting, conventionally, the memory is once erased and then rewritten, whereas in the present invention, the next block is selected and written there. Use the flag bit to select the next block. That is, the block written immediately before is not erased or overwritten. Erase is performed only when further writing is performed after writing to all blocks.

With this configuration, the apparent memory capacity is reduced from R to M bytes, but the number of rewritable times is increased from P to N times when the number of rewritable times of a single memory cell is P. . It is also possible to provide a counter using the same memory cell in order to manage the number of rewrites of a single memory cell up to P times. Even in that case, the flag bit is used. This is because if there is no flag bit, P × N rewrites will occur when the counter is updated.

As described above, according to the present invention, a large number of rewritable times can be realized by using the device according to the prior art as it is, that is, without greatly improving the difficult characteristics and processes. Further, it is possible to reduce the cost and improve the reliability and performance of an information processing system incorporating the semiconductor memory device of the present invention.

That is, as described above, for an application requiring a small capacity but a large number of rewrites,
In the past, expensive EEPROM had to be selected,
In the present invention, a flash memory (batch erase type EEPROM) is used.
M) or since an EPROM can be used, the system cost can be reduced. It is to be noted that the function corresponding to the present invention cannot be realized by software such as an operating system.
Must be recorded in some way. Temporarily DRAM
If the data is recorded in volatile memory, such as when the power is turned off, it must be re-saved to another storage device, and when power is lost, the value is lost. There is a possibility that it may be damaged. Alternatively, when data is recorded on a magnetic recording device typified by a hard disk, the access time is long, resulting in deterioration of system performance.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a conceptual diagram showing an example of the configuration of a semiconductor memory device that implements a method of controlling a semiconductor memory device according to an embodiment of the present invention, and is shown in FIGS. 2, 3, 4, and 5. ,
6, 7, 8, and 9 are conceptual diagrams illustrating an example of the operation.

The semiconductor memory device 10 of the present embodiment comprises a memory mat 11 and a memory mat 11 which are constituted by a nonvolatile semiconductor memory medium such as a so-called flash memory which is a batch erasable EEPROM, for example. X-decoder 12 and Y-decoder 13 for specifying the positions (bit addresses) of a plurality of memory cells arranged in a memory cell to perform data writing, reading, erasing, etc., and bits read from the memory cells in data reading. Sense amplifier 1 for amplifying electric charge as data and outputting it to the outside
4. An I / O interface 15 connected to an external connection terminal for inputting / outputting a write / read address, write / read data, control command, etc. with the outside, write / read / batch erase A control register 16 for designating an operation mode such as an external operation from the outside, for example, a booster circuit for generating an erasing voltage at the time of electrically erasing the memory mat 11 collectively, and supplying a power for operating each part of the semiconductor memory device 10 The power supply system 17 is provided.

The semiconductor memory device 10 of the present embodiment has a rewrite control logic 1 for managing the number of rewrites of the memory mat 11 and the like.
8. A flag bit 19 for identifying the presence or absence of data writing for each of a plurality of blocks set by dividing the storage area of the memory mat 11 into a plurality of sections as described later, and according to the state of the flag bit 19 , A block decoder 20 for selecting one or a plurality of blocks to be subjected to data writing / reading, and the like.

In the case of the present embodiment, flag bit 19 is formed of, for example, a memory cell having the same configuration as that of memory cell constituting memory mat 11, and is erased simultaneously when memory mat 11 is erased. In the memory mat 11 and the flag bit 19 according to the present embodiment, all bits of the memory cell are set to "1" at the time of erasing.

In the case of this embodiment, as exemplified in FIG. 2, the memory mat 11 having the total capacity R as described above is used.
Is divided into N blocks of size M (R = M × N). Then, as shown in FIG. 3, the same address is assigned to each divided block.

In general, ROM, RA
Although there are M, I / O, etc., when the semiconductor memory device 10 according to the present embodiment is used, the allocated memory size is M. Although the same address is assigned to all blocks, what is actually selected is an active block selected by a mechanism such as a selection logic incorporated in the block decoder 20 described later.

As illustrated in FIG. 4, flag bit 1
9 is set corresponding to each of a plurality of blocks set by dividing the storage area of the memory mat 11.

When the block selected by the block decoder 20 is rewritten, writing is performed in addition to the corresponding bit of the flag bit 19 (in the case of the present embodiment, the operation of setting the bit of the corresponding block to "0"). . The flag bit 19 has two functions. The rewriting history is recorded, and the next selected block (active block) is determined from the history.

As shown in FIG. 5, rewriting is performed in block units. The K-th rewriting is performed for the K% N (% is a modulo operation) block (the 0th block is block 0). That is, the number of divisions (blocks) N of the memory mat 11 =
If 4, K = 10, 10% 4 = the second block (block 2) becomes the active block.

FIG. 6 shows an example of the configuration of the rewrite selection logic 20a of the block decoder 20 as a method of selecting an active block by using the flag bit 19 at the time of rewriting (writing). As an example, the reselection logic 20a
Indicates that the youngest block in the writing order has the flag bit 19
Is used as a determination value (“1”: selected, “0”: non-selected) as to whether or not the corresponding block is selected, and in subsequent blocks, adjacent flag bits are set to one of them (in a lower writing order). Side) and take the logical product (N−
1) The output values of the AND gates 20a-1 are set as the determination values (“1”: selected, “0”: non-selected) of the selection of the corresponding block.

That is, in the case of the present embodiment, immediately after the erasure of the memory mat 11, the flag bits 19 are all "1". Becomes "1" and block 0 is selected. Thereafter, each time rewriting is performed, the bit value of the flag bit 19 of the selected block is updated to "0", so that the position of the selected block thereafter is one. Move to the next block one by one.

In the case of the present embodiment, erasing of the memory mat 11 is not performed every time rewriting, but is performed for all blocks after writing is performed for all blocks. This behavior is
For example, as illustrated in FIG.
In this case, an AND gate 18a that takes the logical product of the inverted values of all the bits of the flag bit 19 can be provided. Alternatively, only the flag bits of the last block may be realized by a plurality of flag bits for the last several blocks.

From the state of the flag bit 19, a signal (mat full signal 18b) is generated which indicates that writing to all blocks has been completed and that the memory mat 11 needs to be erased. When the control software or the like detects this mat full signal 18b at the time of rewriting, the entire memory mat 11 (all blocks) is erased first, and then rewriting is performed.

As shown in FIG. 8, after all blocks are erased, all the flag bits 19 become "1", so that the block to be rewritten is determined by the rewriting selection logic 20a of the block decoder 20. Return to the beginning (0th block 0).

As shown in FIGS. 1 and 9, the memory mat 11 and the flag bit 1
9, a rewrite counter 2 that counts down (counts up) by the mat full signal 18b to count the number of erases.
By providing 1, the number of rewrites of a single semiconductor memory device 10 can be managed.

The erase signal (matt full signal 18b)
May be stored in another register (for example, a part of the control register 16), and the control software may read out the updated register to update a counter provided outside the semiconductor memory device 10.

At the time of data reading, the most recently rewritten block is selected from flag bit 19 and accessed. FIG. 10 shows an example of the configuration of the read-time control logic 20b in the block decoder 20. The read-time control logic 20b of this embodiment is an (N-1) AND gate 20b that takes a logical product of the bit values adjacent to the flag bit 19 from the youngest side of the block order and logically inverts the youngest side. -1 and an inverter 20 for logically inverting and outputting the bit value of the flag bit 19 corresponding to the last block
b-2, etc. As a result, the bit position of the last "0" when each bit of the flag bit 19 is viewed in order from the younger side of the corresponding block, that is, the position of the most recently rewritten block is specified. Can be read.

An example of the operation of the semiconductor memory device 10 of the present embodiment as described above is shown in the flowchart of FIG.

First, in the initial state in which the whole is erased, all bits of the memory mat 11 and the flag bit 19 are set to "1".

In this state, an access request is awaited (step 101), and it is determined whether the access mode is a write request (step 102). If the access mode is a write request, whether or not the mat is full (all blocks have been used for rewriting) Is determined (step 103).

If the mat is not full, the block decoder 20 selects a new active block to be rewritten as shown in FIG. 6 (step 104), and rewrites the write data to the selected active block. Is performed (step 105).

Further, the bit position of the flag bit 19 corresponding to the rewritten active block is updated from "1" to "0" (step 106). Step 105
And step 106 may be performed simultaneously.

When the upper limit of the number of rewrites of the memory mat 11, that is, the rewrite life is managed by providing the rewrite number counter 21, the total number of rewrites of the memory mat 11 is determined by the specifications of the semiconductor memory device 10. It is determined whether or not the upper limit has been exceeded (step 107), and if so, a warning is issued to the outside as necessary (step 112).

If it is determined in step 103 that the mat is full, the entire memory mat 11 is erased (all bits are set to "1" in this embodiment) (step 108), and rewriting is performed. The number counter 21 is counted up (Step 109), and thereafter, the block selection / rewrite processing of Step 104 and thereafter is executed.

In step 102, in the case other than the write request, for example, at the time of a read request, the operation of the read control logic 20b of the block decoder 20 as illustrated in FIG. A block is selected (step 110), data is read and output to the outside (step 111).

As described above, in the case of the present embodiment, for example, the memory mat 1 having a capacity M and a rewritable number of P times.
1 is a block 0 of N size (R / N =) M bytes.
The block is divided into blocks N-1, each block is assigned to a common address, and at the time of rewriting, an unwritten block is selected and executed. When all the blocks have been rewritten, the entire memory mat 11 (all blocks) is collectively collected. By repeating the erasing operation, the apparent memory capacity is reduced from R to M bytes, but the number of rewritable times is P × N when the number of rewritable times of a single memory cell is P times. Increase in times.

For example, when the memory mat 11 having the storage capacity R = 32 KB is divided into N = 1024 blocks each having M = 32 bytes, the memory mat 11 can be substantially rewritten even if the number of rewritable times P = 100. And 100 × 1
024 = 102400 or more rewritable times can be realized.

That is, the memory mat 1 made of inexpensive memory cells whose number of rewritable times is low but whose manufacturing process is easy and inexpensive.
By using No. 1, the non-volatile semiconductor memory device 10 with a large number of rewrites can be realized at low cost without using a more expensive memory cell whose manufacturing process is more difficult but more difficult.

Conventionally, the overhead of the erasing operation occurs every time prior to rewriting, but in the case of this embodiment, the overhead of the erasing operation is such that the next data rewriting is performed when all the blocks have been rewritten. Since this occurs only in the case of the block batch erasure at the time of execution, and other than that, there is no overhead for erasure accompanying the rewriting, so that the performance improvement by shortening the time required for data rewriting can also be realized.

By using the semiconductor memory device 10 of the present embodiment, for example, a device that requires a small amount of data to be stored, but is frequently rewritten, and needs to retain data even after the power is turned off. It can be realized at low cost. For example, in a television receiver, the setting state of a channel is stored even after the power is turned off, or a small amount of data that is frequently rewritten in an IC card or the like where low cost is required is stored in a nonvolatile manner. Becomes effective.

In the example of FIG. 1, the semiconductor memory device 10 is shown as a single unit for the sake of simplicity. However, the configuration of the semiconductor memory device 10 is referred to as a so-called IP (function block), The present invention includes the use of a part incorporated in a system LSI or the like.

In the above description, the flag bit 19
Although the example of determining whether or not each block has been rewritten is shown in the above, the determination can be made using the storage content of each block. That is, as described above, the memory mat 11 in the semiconductor memory device 10 of the present embodiment
At the time of erasing, all bits become "1". Utilizing this, as illustrated in FIG. 12, a specific value (for example, in the present embodiment,
"FF" (HEX)) is used as a pivot, and it is determined that a block in which all bytes of the stored content are "FF" (HEX) is an unrewritten block, and is used to select an active block to be rewritten. be able to. In this case, the flag bit 19 becomes unnecessary, and the semiconductor memory device 1
0 can be further simplified, and further cost reduction can be realized.

In this case, a mechanism for detecting the pivot data by software or the block decoder 20 inside the semiconductor storage device 10 may be provided.

As a modification of the setting and rewriting control of a plurality of blocks in the memory mat 11, for example, as shown in FIG. 13, some of the plurality of blocks divided into N (J1, J3) are used. Can be excluded from the target of the rewrite control as described above. In this case, the removed part can be used as a ROM of the conventional specification with a low number of rewritable times. In other words, there is an advantage that one semiconductor memory device 10 can handle a variety of applications with a required number of rewritable times.

As shown in FIG. 14, M × N
It is also possible to have a configuration having a plurality of block groups and having a different address space for each block group. In this case, one semiconductor memory device 10 can cope with an application requiring a large number of rewrites and having a plurality of memory areas that need to be rewritten separately.

In the above description, as an example, the case where the rewrite operation is performed by selecting one block is described. However, the present invention is not limited to this. For example, as shown in FIG. For each of them, an arbitrary number of plural blocks may be selected at a time and may be rewritten. In this case, it is possible to cope with a special use in which the data size is different every time rewriting is performed.

Further, as exemplified in FIG. 16, when an active block is selected at the time of rewriting, a configuration may be adopted in which blocks are overlapped and designated. In this case, it is possible to effectively use the storage capacity of each block in rewriting small-capacity data smaller than the block size.

In the above description, a case has been described in which the most recently rewritten block is selected and accessed at the time of reading. However, rewriting is performed for one block. May be provided with a function of allocating the block to the address space. That is, since the memory mat 11 is non-volatile, each block rewritten before the current active block stores the rewrite data at that time in a time-series manner. Conversely, a configuration in which rewrite data at an arbitrary point is referred to may be adopted. For example, the management of the update history of data can be easily realized in an application that has been rewritten but requires a reverse access to past data.

In the above description, an example is shown in which the memory mat 11 inside the single semiconductor memory device 10 is divided into blocks and specifications are made. However, a single nonvolatile semiconductor memory chip is used as each block. It is also possible to adopt a configuration in which

That is, as illustrated in FIG. 17, a plurality of nonvolatile semiconductor memory chips 51 each of which is itself composed of a single flash memory or the like, a flag bit 52 for determining whether or not each chip is rewritten; An I / O interface 53 such as input / output wiring, a chip selection logic 54 for selecting the nonvolatile semiconductor memory chip 51 based on the state of the flag bit 52, a rewrite number counter 55 for counting the number of erase operations as a whole, May be provided as the semiconductor memory device 50 including

In the semiconductor memory device 50, these components are sealed in one package so that the address range is as if it were one semiconductor memory device for the capacity of one nonvolatile semiconductor memory chip 51. Is possible.

Then, the chip selection logic 54 sequentially selects each nonvolatile semiconductor memory chip 51 and performs a rewrite operation by using an interface such as a chip select inherent in each nonvolatile semiconductor memory chip 51. ,
The erasing is performed by using an interface that each nonvolatile semiconductor memory chip 51 originally has and receives an external erase instruction.
It is executed by instructing all at once.

The flag bit 52 and the rewrite counter 55 may be stored by allocating a dedicated nonvolatile semiconductor memory chip 51.

In the case of FIG. 17, since most of the components can be realized by using the existing nonvolatile semiconductor memory chip, there is an advantage that the nonvolatile semiconductor memory having a large number of rewritable times can be realized at low cost. is there.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say, there is.

For example, the configuration of the semiconductor memory device is not limited to the one described in the above embodiment.

[0067]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

According to the method for controlling a semiconductor memory device of the present invention, the existing non-volatile semiconductor memory device having a small number of rewritable times can be used as it is, without the need for a significant and difficult characteristic / process improvement. The effect is obtained that a larger number of rewritable times can be realized.

According to the method of controlling a semiconductor memory device of the present invention, a larger number of rewritable times can be realized at low cost by using a nonvolatile semiconductor storage medium having a smaller number of rewritable times. The effect is obtained.

Further, according to the method of controlling a semiconductor memory device of the present invention, an effect is obtained that history management of stored information can be easily realized.

According to the method of controlling a semiconductor memory device of the present invention, an existing nonvolatile semiconductor memory device having a small number of rewritable times is diverted to an application requiring a higher required number of rewritable times to improve availability. Can be obtained.

Further, according to the method for controlling a semiconductor memory device of the present invention, there is obtained an effect that a semiconductor memory device having a small storage capacity and a large number of rewritable times can be realized at low cost.

According to the method of controlling a semiconductor memory device of the present invention, a semiconductor memory device having a large number of rewritable times while maintaining high reliability is realized by using a nonvolatile semiconductor memory device having a small number of rewritable times. Can be obtained.

According to the method of controlling a semiconductor memory device of the present invention, it is possible to reduce the cost of an information processing system in which a nonvolatile semiconductor memory device is incorporated, and to improve the reliability and performance. The effect is obtained.

According to the semiconductor memory device of the present invention, the existing non-volatile semiconductor memory device having a small number of rewritable times can be used as it is, and a large number of difficult characteristics and process improvements are not required. The effect is obtained that the number of times of rewriting can be realized.

According to the semiconductor memory device of the present invention,
By using a non-volatile semiconductor storage medium having a small number of rewritable times, it is possible to obtain a large number of rewritable numbers at low cost.

According to the semiconductor memory device of the present invention,
An effect is obtained that history management of stored information can be easily realized.

According to the semiconductor memory device of the present invention,
The effect is obtained that the existing non-volatile semiconductor memory device having a small number of rewritable times can be diverted to an application requiring a higher number of rewritable times to improve availability.

According to the semiconductor memory device of the present invention,
A semiconductor memory device with a small storage capacity and a large number of rewritable times,
The effect that it can be realized at low cost is obtained.

According to the semiconductor memory device of the present invention,
By using a nonvolatile semiconductor memory device with a small number of rewritable times, it is possible to achieve a semiconductor memory device with a large number of rewritable times while maintaining high reliability.

According to the semiconductor memory device of the present invention,
The effect is obtained that the cost of the information processing system in which the nonvolatile semiconductor memory device is incorporated can be reduced, and the reliability and performance can be improved.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing an example of a configuration of a semiconductor memory device that implements a method of controlling a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram illustrating an example of an operation of a semiconductor memory device that executes a method of controlling a semiconductor memory device according to an embodiment of the present invention;

FIG. 3 is a conceptual diagram illustrating an example of an operation of the semiconductor memory device that performs the method of controlling a semiconductor memory device according to an embodiment of the present invention;

FIG. 4 is a conceptual diagram illustrating an example of an operation of the semiconductor memory device that executes the semiconductor memory device control method according to an embodiment of the present invention;

FIG. 5 is a conceptual diagram showing an example of the operation of the semiconductor memory device that executes the method of controlling the semiconductor memory device according to one embodiment of the present invention;

FIG. 6 is a conceptual diagram showing an example of the operation of the semiconductor memory device that executes the method of controlling a semiconductor memory device according to one embodiment of the present invention;

FIG. 7 is a conceptual diagram illustrating an example of an operation of the semiconductor memory device that performs the semiconductor memory device control method according to an embodiment of the present invention;

FIG. 8 is a conceptual diagram illustrating an example of an operation of the semiconductor memory device that performs the method of controlling the semiconductor memory device according to the embodiment of the present invention;

FIG. 9 is a conceptual diagram illustrating an example of an operation of the semiconductor memory device that performs the method of controlling the semiconductor memory device according to one embodiment of the present invention;

FIG. 10 is a conceptual diagram showing an example of the operation of the semiconductor memory device that executes the method of controlling the semiconductor memory device according to one embodiment of the present invention;

FIG. 11 is a flowchart illustrating an example of an operation of the semiconductor memory device that executes the semiconductor memory device control method according to an embodiment of the present invention;

FIG. 12 is a conceptual diagram showing a modified example of the semiconductor memory device that executes the method of controlling the semiconductor memory device according to one embodiment of the present invention;

FIG. 13 is a conceptual diagram showing a modified example of the semiconductor memory device that executes the method of controlling the semiconductor memory device according to one embodiment of the present invention;

FIG. 14 is a conceptual diagram showing a modified example of the semiconductor memory device that executes the method of controlling the semiconductor memory device according to one embodiment of the present invention;

FIG. 15 is a conceptual diagram showing a modified example of the semiconductor memory device that executes the method of controlling the semiconductor memory device according to one embodiment of the present invention;

FIG. 16 is a conceptual diagram showing a modified example of the semiconductor memory device that executes the method of controlling the semiconductor memory device according to one embodiment of the present invention;

FIG. 17 is a conceptual diagram showing a modified example of the semiconductor memory device that executes the method of controlling the semiconductor memory device according to one embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 10 semiconductor storage device 11 memory mat (semiconductor storage medium) 12 X decoder 13 Y decoder 14 sense amplifier 15 I / O interface 16 control register 17 power supply system 18 rewrite control logic (control logic) 18a AND gate 18b mat full signal 19 flag bit Reference Signs List 20 block decoder (control logic) 20a rewriting selection logic 20a-1 AND gate 20b readout control logic (control logic) 20b-1 AND gate 20b-2 inverter 21 rewriting number counter 50 semiconductor storage device 51 non-volatile semiconductor memory chip 52 Flag bit 53 I / O interface 54 Chip selection logic 55 Rewrite counter

Claims (10)

[Claims] 1. A storage area of a nonvolatile semiconductor storage medium is logically or physically divided into a plurality of blocks, an address space assigned to each block is partially or completely overlapped, and data rewriting is performed. A semiconductor, wherein the erased block is selected and executed, and a plurality of blocks are erased prior to the first data rewrite after the data rewrite is completed for all the blocks. A method for controlling a storage device. 2. A control method for a semiconductor memory device according to claim 1, further comprising a flag bit for identifying whether or not data rewriting is performed for each of said blocks.
A method of controlling a semiconductor memory device, wherein the flag bit is constituted by a memory cell having the same structure as that of the semiconductor memory medium. 3. The method of controlling a semiconductor memory device according to claim 1, further comprising a counter for counting the number of times of execution of the erasure in the semiconductor storage medium, wherein the counter is a memory cell having the same structure as the semiconductor storage medium. A method for controlling a semiconductor memory device, comprising: 4. The method of controlling a semiconductor storage device according to claim 1, wherein said semiconductor storage medium is a batch erasable EEPROM (flash memory) or an EPR.
A method for controlling a semiconductor memory device, which is an OM. 5. The method of controlling a semiconductor memory device according to claim 1, wherein the specific bit data uniformly set in the semiconductor storage medium at the time of the erasing is determined as to whether or not data rewriting is performed for each of the blocks. A method for controlling a semiconductor memory device, wherein the method is used as information for identification. 6. The method of controlling a semiconductor memory device according to claim 1, wherein a part of the plurality of blocks is excluded from a target of the data rewriting and the erasing operation, and is used according to an original specification of the semiconductor storage medium. Operation, an operation of allocating a plurality of the blocks to different address spaces and preparing a plurality of sets, an operation of selecting a plurality of the blocks upon execution of the data rewriting, and executing the data rewriting in units of the individual blocks. And at the time of data reading, an operation of allocating any one of the plurality of blocks to the address space. 7. A nonvolatile semiconductor storage medium in which a storage area is logically or physically divided into a plurality of blocks, and an address space assigned to each of said blocks partially or completely overlaps with a non-volatile semiconductor storage medium. Select the block and execute data rewriting,
A control logic for performing an erase operation on a plurality of blocks prior to the first data rewrite after the data rewrite is completed for all the blocks. 8. The semiconductor memory device according to claim 7, wherein at least one of a flag bit for identifying whether or not data rewriting is performed on each of said blocks and a counter for counting the number of times of erasure performed on said semiconductor storage medium. At least one of an operation of selecting the erased block by referring to and updating the flag bit, and a rewriting life management operation based on the number of erasures of the semiconductor storage medium by referring to and updating the counter. A semiconductor memory device. 9. The semiconductor memory device according to claim 7, wherein the control logic is configured to execute a data rewrite for each of the blocks by using specific bit data uniformly set in the semiconductor storage medium at the time of the erasing. A semiconductor memory device used as information for identifying presence / absence. 10. The semiconductor memory device according to claim 8, wherein said flag bit and said counter are constituted by memory cells having the same structure as said semiconductor storage medium.