CN118098309A

CN118098309A - Method and device for improving data accuracy of NOR FLASH configuration module, storage medium and storage device

Info

Publication number: CN118098309A
Application number: CN202410214635.5A
Authority: CN
Inventors: 王潇潇
Original assignee: Dongxin Semiconductor Co ltd
Current assignee: Dongxin Semiconductor Co ltd
Priority date: 2024-02-27
Filing date: 2024-02-27
Publication date: 2024-05-28

Abstract

The disclosure provides a method, a device, a storage medium and a storage device for improving the accuracy of data of a configuration module of an NOR FLASH memory. By setting a small number of redundant word lines, the problems of word line failure and bit line failure are solved in the configuration module at the same time, redundant bit lines are not required to be set, and one-to-one accurate replacement of the memory cells can be realized. The method comprises the following steps: sequentially performing programming operation on a plurality of word lines in a configuration module; recording a word line address of a memory cell having a program failure, i.e., a failed memory cell, in a first redundant word line as a failed word line address; recording a bit line address of the failed memory cell in the second redundant word line as a failed bit line address; and writing the data which should be written into the failure memory cell into the memory cell which is corresponding to the address of the failure bit line on the third redundant word line as a replacement memory cell of the failure memory cell, and when the data reading is sequentially carried out on the plurality of word lines in the configuration module, replacing the data written into the replacement memory cell on the third redundant word line with the data written into the replacement memory cell on the third redundant word line.

Description

Method and device for improving data accuracy of NOR FLASH configuration module, storage medium and storage device

Technical Field

The present invention relates to the field of memories, and in particular, to a method, an apparatus, a storage medium, and a storage device for improving the data accuracy of a NOR FLASH configuration module.

Background

FLASH memory (FLASH) is a non-volatile memory, and data is not lost even when power is turned off, so it is widely used in electronic devices such as memory cards, solid state disks, and portable multimedia players (Portable Multimedia Players). FLASH memory can be largely classified into NOR-type FLASH memory (NOR FLASH) and NAND-type FLASH memory (NAND FLASH).

The NOR FLASH memory is used as an electrically erasable programmable read-only memory, which can perform erasing and programming operations without removing a memory chip, and has the advantages of non-volatility, solid state property, small volume, light weight, vibration resistance, high performance, low energy consumption and the like, so that the NOR FLASH memory is widely applied to various fields of computer hardware, industrial control, hardware instruments, household appliances, smart phones and the like.

The NOR FLASH memory includes a module (normal array) for a user to perform program, erase, and read operations and a configuration module (config array) located inside the chip in a module structure. The configuration module is responsible for chip power-on configuration, read-write erase algorithm mode selection, mode configuration, analog circuit voltage and current selection and the like, stores a large amount of information of the chip, such as reference voltage/current, internal clock frequency, equipment ID, algorithm related parameters and the like, and is a basic functional module of the NOR FLASH chip.

Before the NOR FLASH chip leaves the factory, the manufacturer needs to program the configuration module and store corresponding data information. After leaving the factory, the data in the chip can be read every time the chip is powered on, but a user cannot read, write and erase the data of the configuration module.

Fig. 1 shows a basic configuration example of a configuration module in a NOR FLASH memory. In fig. 1, a configuration module with a capacity of 64 bytes (byte) is taken as an example. The configuration module is composed of 8 word lines (wl 0 to wl 7) and 64 bit lines (bl 0 to bl 63). The location where each bit line crosses the word line is a memory cell, such as a field effect transistor (not shown). The memory cell has a source terminal connected to the source line, a drain terminal connected to the bit line bl, and a gate terminal connected to the word line wl. By controlling the voltages on the word line wl and the bit line bl, a program operation, an erase operation, and the like are performed on the memory cell.

Once one or more word lines wl and/or bit lines bl fail, the configuration module cannot write the configuration information correctly, resulting in the chip being no longer usable. Therefore, repair of a failed word line or bit line is related to the accuracy of the configuration module data and the yield of the chip.

Patent document 1 discloses a repair method of a NOR flash memory, which solves the problem of word line failure by adding redundant word lines to replace the entire word line of a defective memory cell. In addition, a redundant bit line can be added to replace a certain bit line, so that the problem that a certain bit line on a certain word line fails can be solved. However, if the faulty memory cells are more discretely present on different word lines and bit lines, the resources required for adding redundant word lines and redundant bit lines correspondingly also need to be increased, which leads to an increase in chip area.

Prior patent literature

Patent document 1: CN 111863108A

Disclosure of Invention

The invention aims to solve the technical problems

The invention aims to solve the problems of word line failure and bit line failure in a configuration module at the same time by arranging a small number of redundant word lines without arranging redundant bit lines, and can realize one-to-one accurate replacement of memory cells.

Technical means for solving the technical problems

To solve the above technical problem, according to some exemplary embodiments of the present disclosure, there is provided a method for improving data accuracy of a configuration module of a NOR FLASH memory, the configuration module including:

A memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells respectively disposed at crossing positions of the plurality of word lines and the plurality of bit lines; and

A redundancy word line unit including a plurality of redundancy word lines,

The method comprises the following steps:

sequentially performing programming operation on the plurality of word lines in the configuration module;

Recording a word line address of a failed memory cell, which is the memory cell having programming failure, in a first redundant word line as a failed word line address;

recording the bit line address of the failed memory cell in the second redundant word line as a failed bit line address; and

Writing data that should be written to the failed memory cell to the memory cell on the third redundant word line corresponding to the failed bit line address as a replacement memory cell for the failed memory cell,

And when the plurality of word lines in the configuration module are sequentially subjected to data reading, replacing the data in the failure memory cell with the data written in the replacement memory cell on the third redundant word line.

In some embodiments, the first redundant word line, the second redundant word line, and the third redundant word line are combined in multiple groups.

In some embodiments, the failed word line address on the first redundant word line and the failed bit line address on the second redundant word line are stored in association corresponding to the failed memory cell.

In some embodiments, when sequentially reading data from the plurality of word lines in the configuration module, it is checked whether the failed word line address associated with the word line currently being read is recorded in the first redundant word line.

In some embodiments, when the failed word line address associated with the word line currently being read is recorded on the first redundant word line, the data in the replacement memory cell in the third redundant word line is read to replace the failed memory cell according to the failed word line address and the failed bit line address corresponding to the failed word line address recorded on the second redundant word line.

In some embodiments, the failed word line address on the first redundant word line and the failed bit line address on the second redundant word line are stored in a register in advance when sequentially reading data from the plurality of word lines in the configuration module.

In some embodiments, when sequentially reading data from the plurality of word lines in the configuration module, a check is made in the register as to whether there is a record of the failed word line address associated with the word line currently being read.

The invention also provides a device for improving the data accuracy of the configuration module of the NOR FLASH memory, wherein the configuration module comprises:

A redundancy word line unit including a plurality of redundancy word lines,

The device comprises:

The programming module sequentially performs programming operation on a plurality of word lines in the configuration module;

A first redundant word line recording module that records, in a first redundant word line, a word line address of a memory cell having a program failure, i.e., a failed memory cell, as a failed word line address;

a second redundant word line recording module that records a bit line address of the failed memory cell in a second redundant word line as a failed bit line address;

A replacement memory cell writing module that writes data that should be written to the failed memory cell on a third redundant word line and that corresponds to the failed bit line address as a replacement memory cell for the failed memory cell; and

And a reading module for replacing the data in the failed memory cell with the data written in the replacement memory cell on the third redundant word line when sequentially reading the data from the plurality of word lines in the configuration module.

In some embodiments, the first redundant word line recording module and the second redundant word line recording module store the failed word line address and the failed bit line address corresponding to the failed memory cell in association corresponding to the failed memory cell.

In some embodiments, the configuration module further has a register, and the reading module stores the failed word line address on the first redundant word line and the failed bit line address on the second redundant word line in the register in advance when sequentially reading data from the plurality of word lines in the configuration module.

In some embodiments, the read module checks in the register if there is a record of the failed word line address associated with the word line currently being read while sequentially reading data from the plurality of word lines in the configuration module.

The present invention also provides a storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method of improving the data accuracy of a configuration module of a NOR FLASH memory as described above.

The invention also provides a storage device comprising a storage controller, the storage controller comprising a memory, a processor and a computer program stored on the memory and capable of running on the processor, the processor executing the computer program realizing the steps in the method for improving the data accuracy of the configuration module of the NOR FLASH memory.

Effects of the invention

According to the method, the device, the storage medium and the storage equipment for improving the data accuracy of the configuration module of the NOR FLASH memory, provided by the invention, the problems of word line failure and bit line failure can be solved in the configuration module at the same time by only setting a small amount of redundant word lines and not setting redundant bit lines, one-to-one accurate replacement of storage units can be realized, even if the configuration module of the NOR FLASH memory has a storage unit with programming failure, corresponding data can be written in the replacement storage unit on the redundant word lines, thereby improving the accuracy of power-on data reading of the NOR FLASH memory and not causing the enlargement of a chip.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure, without limitation to the disclosure. In the drawings:

Fig. 1 is a basic configuration example of a configuration module in a NOR FLASH memory.

Fig. 2 is a functional block diagram of the NOR FLASH memory 1 of the present embodiment.

Fig. 3 is a functional block diagram of the redundant word line unit 12 in the NOR FLASH memory 1 of the present embodiment.

Fig. 4 is a flowchart of the programming operation of the configuration module in the NOR FLASH memory 1 of the present embodiment.

Fig. 5 is a flowchart of a read operation of the configuration module in the NOR FLASH memory 1 of the present embodiment.

Fig. 6 is a schematic diagram of the configuration module of embodiment 1.

Fig. 7 is a schematic diagram of the configuration module of embodiment 2.

Fig. 8 is a schematic diagram of the configuration module of embodiment 3.

Detailed Description

In the following, specific embodiments of the present disclosure will be described, and it should be noted that in the course of the detailed description of these embodiments, it is not possible in the present specification to describe all features of an actual embodiment in detail for the sake of brevity. It should be appreciated that in the actual implementation of any of the implementations, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure.

Unless defined otherwise, technical or scientific terms used in the claims and specification should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like in the description and in the claims, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are immediately preceding the word "comprising" or "comprising", are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items. The terms "connected," "coupled," or "connected" are not restricted to physical or mechanical connections, nor to direct or indirect connections.

In the present disclosure, all embodiments and preferred embodiments mentioned herein may be combined with each other to form new technical solutions, if not specifically stated. In the present disclosure, all technical features mentioned herein as well as preferred features may be combined with each other to form new technical solutions, if not specifically stated.

In the description of the embodiments of the present disclosure, the term "and/or" is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

Methods, apparatuses, devices, and storage media for improving data accuracy of a NOR FLASH configuration module provided according to embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

< Configuration Module of NOR FLASH memory >

Fig. 2 is a functional block diagram of the NOR FLASH memory 1 of the present embodiment. The NOR FLASH memory 1 includes a memory cell array 11, a redundant word line unit 12, and a register 13. The memory cell array 11 has a structure shown in fig. 1, for example, and is configured by a 64-byte configuration module including 8 word lines (wl 0 to wl 7) and 64 bit lines (bl 0 to bl 63), and one memory cell is provided at a position where each bit line and each word line intersect and overlap.

The redundant word line unit 12 includes a plurality of redundant word lines, for example, first to third redundant word lines described later, for recording addresses of the failed word line wl, addresses of the failed bit line bl, storing data to be replaced, and the like, which will be described later in detail.

The register 13 is connected to the memory cell array 11 and the redundant word line unit 12, and is used for temporarily storing data, addresses, and the like between the memory cell array 11 and the redundant word line unit 12.

Fig. 3 is a functional block diagram of the redundant word line unit 12 in the NOR FLASH memory 1 of the present embodiment. As shown in fig. 3, the redundant word line unit 12 includes a first redundant word line 121, a second redundant word line 122, and a third redundant word line 123. The first redundant word line 121 is used to record the address of the failed word line (wl_fail), and is also referred to as a redundant word line wl_record hereinafter. For example, for the 64 byte configuration module shown in fig. 1, since there are 8 word lines, on the redundant word line wl_record, 3 bits (bits) can be used to correspond to one word line wl where a failed memory cell exists. For example, when there is a failed memory cell on word line wl3, the redundant word line wl_record may record the address wl_fail of the failed word line wl3 with 3bit "011". When there is a failed memory cell on word line wl4, the redundant word line wl_record may record the address wl_fail of the failed word line wl4 with a 3bit "100". A single failed word line address may be recorded on the first redundant word line 121 (redundant word line wl_record), or a plurality of failed word line addresses may be recorded.

The second redundant word line 122 is used to record the address of the failed bit line (denoted as bl_fail), and is also denoted as the redundant word line bl_record hereinafter. For example, for the 64-byte configuration module shown in fig. 1, since there are 64 bit lines, 8 bits (bits) can be used to correspond to one bit line bl where a failed memory cell exists on the redundant word line bl_record. For example, when there is a failed memory cell on the bit line bl62, the redundant word line bl_record may record the address bl_fail of the failed bit line bl62 with 8bit "11111110". When there is a failed memory cell on bit line bl63, the redundant word line bl_record may record the address bl_fail of the failed bit line bl63 with 8bit "11111111". A single failed bit line address may be recorded on the second redundant word line 122 (redundant word line bl_record) or a plurality of failed bit line addresses may be recorded.

The third redundant word line 123 is used to store data that needs to be replaced, also referred to as a redundant word line wl_ redun below. When the failed word line or bit line occurs, the configuration module in the embodiment does not need to replace the whole word line or bit line, and only needs to store the data to be replaced in the memory cell of the corresponding address of the redundant word line wl_ redun to replace the failed memory cell, so that the problem of word line/bit line failure can be solved at the same time, and the 1-to-1 replacement of the accurate memory cell is achieved.

Next, the programming operation and the reading operation of the configuration block in the NOR FLASH memory 1 of the present embodiment will be described in detail.

< Programming operation of configuration Module >

Fig. 4 is a flowchart of the programming operation of the configuration module in the NOR FLASH memory 1 of the present embodiment. First, in step S41, the configuration modules are programmed sequentially by word line. Here, taking a configuration module having N word lines as an example, for example, in the configuration shown in fig. 1, n=8, the configuration module includes word lines wl0 to wl7.

In step S42, the programming result of step S41 is verified to confirm whether the programming is successful. If the verification is successful (yes in step S42), the process proceeds to step S43, and if the verification is failed (no in step S42), the process proceeds to step S44.

In step S43, the current word line program verify is successful, and thus, the next word line is selected for programming.

In step S44, the current word line program verification fails, which means that there is a failed memory cell in the current word line, and the address wl_fail of the current word line and the address bl_fail of the bit line where the failed memory cell is located are recorded in the register 13.

In step S45, it is confirmed whether the programming of all word lines wl0 to wlN has been completed. If not (yes in step S45), the routine returns to step S41, and steps S42 to S44 are repeated until the programming of the last word line wlN is completed. If all the word lines have completed programming (no in step S45), the process proceeds to step S46.

In step S46, the fail word line address wl_fail recorded in the register 13 is written into the first redundant word line 121, i.e., the redundant word line wl_record. For example, in the case where a defective memory cell exists on the word line wl3, the address wl_fail of the defective word line wl3 is recorded with "011" of 3 bits.

In step S47, the fail bit line address bl_fail recorded in the register 13 is written into the second redundant word line 122, i.e., the redundant word line bl_record. For example, in the case where a defective memory cell exists on the bit line bl62, the address bl_fail of the defective bit line bl62 is recorded with "11111110" of 8 bits.

Since the word line address wl_fail and the bit line address bl_fail at which the failed memory cell is located are recorded in step S46 and step S47, respectively, the failed memory cell, in which writing and storing of data is impossible, can be accurately located. In step S48, the data that should be stored in the failed memory cell is sequentially written into the memory cells corresponding to the bit line address bl_fail on the third redundant word line 123, i.e., the redundant word line wl_ redun. That is, the memory address of the data is changed from the address (wl_fail, bl_fail) of the failed memory cell to the address (wl_ redun, bl_fail) on the redundant word line. Therefore, the data on the invalid storage unit can be properly written into the configuration module of the NOR FLASH memory 1 in the embodiment, and the accuracy of the data can be improved.

< Read/write operation of configuration Module >

Fig. 5 is a flowchart of a read operation of the configuration module in the NOR FLASH memory 1 of the present embodiment. After leaving the factory, the chip of the NOR FLASH memory only automatically reads the data in the configuration module at the power-on stage, and a user cannot program and erase the chip.

In the reading operation, first, in step S51, information recorded on the first redundant word line 121, i.e., the redundant word line wl_record, and the second redundant word line 122, i.e., the redundant word line bl_record, i.e., the fail word line address wl_fail and the fail bit line address bl_fail recorded in steps S46 and S47 of fig. 4, are sequentially read, and the read fail addresses are stored in the register 13. As described above, the address of the failed memory cell in the configuration module can be precisely located, via step S51.

Then, in step S52, the configuration modules are sequentially read data for each word line. Here, a configuration module having N word lines, for example, in the configuration shown in fig. 1, n=8, is also taken as an example, and the configuration module includes word lines wl0 to wl7.

In step S53, it is checked whether there is a record of a memory cell in which the current word line wl is failed in the register 13. If the current word line is the failed word line wl_fail, that is, if there is a failed memory cell on the current word line recorded in the register 13 (yes in step S53), the process proceeds to step S54, and if there is no record in the register 13, that is, if there is no failed memory cell on the current word line (no in step S53), the process proceeds to step S55.

In step S54, since there is a defective memory cell on the current word line, the data in the memory cell corresponding to the defective bit line address bl_fail stored in the register 13 on the third redundant word line 123, i.e., the redundant word line wl_ redun, is read, and the data in the defective memory cell on the current word line is replaced with the data in the corresponding memory cell on the redundant word line wl_ redun.

In step S55, since there is no failed memory cell on the current word line, i.e. the data on the word line is good, the memory cell can be used for the chip without replacement, so the next word line is selected for the read operation.

In step S56, it is confirmed whether or not the reading of all the word lines wl0 to wlN is completed. If not (yes in step S56), the routine returns to step S52, and repeats steps S53 to S55 until the reading of the last word line wlN is completed. If all the word lines have been read (no in step S56), the present flow is ended.

Through the above reading process, the data stored in each memory cell of the configuration module can be accurately read, and even if there is a failed memory cell on the current word line, that is, the failed word line address wl_fail is recorded, the data stored in the corresponding (corresponding to the word line address bl_fail of the failed memory cell) memory cell of the redundant word line wl_ redun can be used to replace the data in the failed memory cell for reading through steps S53 and S54, so that the problem of word line failure and bit line failure can be simultaneously solved in the configuration module only by adding a small amount of redundant word lines, and one-to-one accurate replacement of the memory cells is realized, which is helpful for improving the data accuracy of the configuration module in the NOR FLASH memory.

Next, the configuration modules of embodiments 1 to 3 of the present invention will be described with reference to fig. 6 to 8. The configuration modules of embodiments 1 to 3 each employ the same configuration as that of fig. 1, that is, a 64-byte configuration module composed of 8 word lines (wl 0 to wl 7) and 64 bit lines (bl 0 to bl 63), and one memory cell (not shown) is provided at a position where each bit line and each word line intersect and overlap.

Example 1]

Fig. 6 is a schematic diagram of the configuration module of embodiment 1. In embodiment 1, an example is shown in which one defective memory cell exists in a certain word line, and as shown in the figure, the memory cell in the overlapping position of the word line wl3 and the bit line bl63 is defective.

In this embodiment 1, the address of the failed memory cell is (wl 3, bl 63), as shown by the green fork. According to step S46 in the program operation flow (fig. 4) of the configuration module of the present embodiment, the address wl_fail (=011) of the word line wl3 where the failed memory cell is located is recorded on the redundant word line wl_record, as indicated by the red dot in the figure. In addition, according to step S47 in fig. 4, the address bl_fail (=11111111) of the bit line wl63 where the defective memory cell is located is recorded on the redundant word line bl_record, as shown by the yellow dot in the figure. And according to step S48 in fig. 4, the data originally written into the failed memory cell is written into the memory cell corresponding to the bit line bl63 on the redundant word line wl_ redun, i.e., the memory cell (wl_ redun, bl 63), as indicated by the green dot in the figure.

When the configuration module is powered up to read data, according to steps S53 and S54 in fig. 5, when the data is read to the word line wl3, the data of the failed memory cell (wl 3, bl 63) is replaced by the data of the memory cell (wl_ redun, bl 63) on the redundant word line wl_ redun, and the data is directly read by the memory cells on other word lines or bit lines without failure record, thereby improving the data accuracy in the configuration module.

Therefore, even if a failure memory cell exists in the configuration module, the accurate replacement of the failure memory cell can be realized by adding a small amount of redundant word lines, and the problems of word line failure and bit line failure can be solved at the same time without setting redundant bit lines.

Example 2]

Fig. 7 is a schematic diagram of the configuration module of embodiment 2. In embodiment 2, an example is shown in which a plurality of defective memory cells exist on a certain word line, and as shown in the figure, the memory cells in the positions where the word line wl3 and the bit lines bl62 and bl63 overlap each other are defective.

In this embodiment 2, the addresses of the failed memory cells are (wl 3, bl 63) (shown as a green cross in the figure) and (wl 3, bl 62) (shown as a blue cross in the figure), that is, one more failed memory cell (wl 3, bl 62) is added to the memory cell in fig. 6.

According to step S46 in the program operation flow (fig. 4) of the configuration module of the present embodiment, the address wl_fail (=011) of the word line wl3 where the failed memory cell is located is recorded on the redundant word line wl_record, as indicated by the red dot in the figure. In addition, according to step S47 in fig. 4, the address bl_fail (=11111111) of the bit line wl63 where the defective memory cell (wl 3, bl 63) is located is recorded on the redundant word line bl_record, as shown by the yellow dot in the figure. The address bl_fail (=11111110) of the bit line wl62 where another failed memory cell (wl 3, bl 62) is located is also recorded on the redundant word line bl_record, as shown by the purple dots in the figure. And according to step S48 in fig. 4, the data originally written into the failed memory cell (wl 3, bl 63) is written into the memory cell corresponding to the bit line bl63 on the redundant word line wl_ redun, i.e., the memory cell (wl_ redun, bl 63), as indicated by the green dot in the figure. The data that was originally written to the failed memory cell (wl 3, bl 62) is written to the memory cell corresponding to the bit line bl62 on the redundant word line wl_ redun, i.e., the memory cell (wl_ redun, bl 62), as indicated by the blue dot in the figure.

When the configuration module is powered up to read data, according to steps S53 and S54 in fig. 5, when data is read to the word line wl3, the data of the failed memory cell (wl 3, bl 63) is replaced with the data of the memory cell (wl_ redun, bl 63) on the redundant word line wl_ redun, the data of the failed memory cell (wl_ redun, bl 62) is replaced with the data of the memory cell (wl_ redun, bl 62) on the redundant word line wl_ redun, and the data is directly read from the memory cells without failure record on other word lines or bit lines, thereby improving the data accuracy in the configuration module.

Example 3]

Fig. 8 is a schematic diagram of the configuration module of embodiment 3. In this embodiment 3, an example is shown in which a defective memory cell exists in a different word line, and as shown in the figure, a memory cell in a position where the word line wl3 and the bit line bl63 cross and overlap, and a memory cell in a position where the word line wl4 and the bit line bl62 cross and overlap fail.

In this embodiment 3, the addresses of the failed memory cells are (wl 3, bl 63) (shown as green cross in the figure) and (wl 4, bl 62) (shown as blue cross in the figure), i.e., one more failed memory cell (wl 4, bl 62) is added to the memory cell in fig. 6.

According to step S46 in the program operation flow (fig. 4) of the configuration module of the present embodiment, the address wl_fail (=011) of the word line wl3 where the failed memory cell (wl 3, bl 63) is located, as indicated by red dots in the figure, and the address wl_fail (=100) of the word line wl4 where the failed memory cell (wl 4, bl 62) is located are recorded on the redundant word line wl_record, as indicated by pink dots in the figure. In addition, according to step S47 in fig. 4, the address bl_fail (=11111111) of the bit line wl63 where the defective memory cell (wl 3, bl 63) is located (as indicated by yellow dots in the figure) and the address bl_fail (=11111110) of the bit line wl62 where the defective memory cell (wl 4, bl 62) is located (as indicated by purple dots in the figure) are recorded on the redundant word line bl_record. And according to step S48 in fig. 4, the data originally written into the failed memory cell (wl 3, bl 63) is written into the memory cell corresponding to the bit line bl63 on the redundant word line wl_ redun, i.e., the memory cell (wl_ redun, bl 63), as indicated by the green dot in the figure. The data that was originally written to the failed memory cell (wl 4, bl 62) is written to the memory cell corresponding to the bit line bl62 on the redundant word line wl_ redun, i.e., the memory cell (wl_ redun, bl 62), as indicated by the blue dot in the figure.

When the configuration module is powered up to read data, the data of the failed memory cell (wl 3, bl 63) is replaced with the data of the memory cell (wl_ redun, bl 63) on the redundant word line wl_ redun according to steps S53, S54 in fig. 5 when the data is read to the word line wl 3. When data is read to the word line wl4, the data of the failed memory cell (wl 4, bl 62) is replaced by the data of the memory cell (wl_ redun, bl 62) on the redundant word line wl_ redun, and the data is directly read by the memory cells without failure record on other word lines or bit lines, thereby improving the data accuracy in the configuration module.

Therefore, according to the method for improving the data accuracy of the configuration module of the NOR FLASH memory, no matter the condition that a single failure storage unit exists on a single word line shown in the embodiment 1, a plurality of failure storage units exist on a single word line shown in the embodiment 2 and the failure storage units exist on a plurality of word lines shown in the embodiment 3, when the plurality of word lines are subjected to programming operation in sequence, the word line address of the failure storage unit is stored in the first redundant word line as the failure word line address, the bit line address of the failure storage unit is stored in the second redundant word line as the failure bit line address, the storage unit which is on the third redundant word line and corresponds to the failure bit line address is used as the replacement storage unit of the failure storage unit, and the data which should be written into the failure storage unit is written into the replacement storage unit, so that when the plurality of word lines in the configuration module are subjected to data reading in sequence, the data written into the replacement storage unit is replaced by the replacement storage unit, and when only a small quantity of redundant word lines are arranged and bit lines are arranged, the bit line address is stored in the first redundant word line address, the bit line address is used as the failure bit line address is stored in the second redundant word line address, the storage unit is used as the replacement storage unit is used for the replacement of the replacement storage unit, and the data which should be written into the replacement storage unit is written into the replacement storage unit, and the failure storage unit is written into the bit line in the replacement storage unit when the failure storage unit is not corresponding to the redundancy unit, and the data is written into the redundancy storage unit in the NOR storage unit in sequence, and the bit line.

In some embodiments, the first redundant word line, the second redundant word line, and the third redundant word line may each have a plurality.

In addition, the invention also provides a device for improving the data accuracy of the configuration module of the NOR FLASH memory, which comprises: the programming module sequentially performs programming operation on a plurality of word lines in the configuration module; a first redundant word line recording module that records, in a first redundant word line, a word line address of a memory cell having a program failure, i.e., a failed memory cell, as a failed word line address; a second redundant word line recording module that records a bit line address of a failed memory cell in the second redundant word line as a failed bit line address; a replacement memory cell writing module writing data, which should be written into the failed memory cell, onto the third redundant word line and the memory cell corresponding to the failed bit line address as the replacement memory cell of the failed memory cell; and a reading module that replaces data in the failed memory cell with data written in the replacement memory cell on the third redundant word line when sequentially performing data reading on the plurality of word lines in the configuration module. Therefore, the device can solve the problems of word line failure and bit line failure in the configuration module at the same time only by setting a small number of redundant word lines and without setting redundant bit lines, and can realize one-to-one accurate replacement of the memory cells.

In addition, the invention also provides a storage medium which stores a computer program, and the computer program realizes each step in the method for improving the data accuracy of the configuration module of the NOR FLASH memory when being executed by a processor.

In addition, the invention also provides a storage device, which comprises a storage controller, wherein the storage controller comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor, and the processor realizes each step in the method for improving the data accuracy of the configuration module of the NOR FLASH memory when executing the computer program.

It is to be understood that the above description is intended to be illustrative, and not restrictive. For example, the above-described embodiments (and/or aspects thereof) may be used in combination with one another. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the various embodiments of the disclosure without departing from the scope thereof. While the dimensions and types of materials described herein are used to define the parameters of the various embodiments of the disclosure, the various embodiments are not meant to be limiting and are exemplary embodiments. Many other embodiments will be apparent to those of skill in the art upon reading the above description. The scope of the various embodiments of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A method of improving data accuracy of a configuration module of a NOR FLASH memory, the configuration module comprising:

A redundancy word line unit including a plurality of redundancy word lines,

The method comprises the following steps:

2. The method of claim 1, wherein,

The first redundant word line, the second redundant word line and the third redundant word line are combined to form a plurality of groups.

3. The method of claim 1 or 2, wherein,

The failed word line address on the first redundant word line and the failed bit line address on the second redundant word line are stored in association corresponding to the failed memory cell.

4. The method of claim 1 or 2, wherein,

When the plurality of word lines in the configuration module are sequentially subjected to data reading, whether the failed word line address related to the word line which is currently being read is recorded in the first redundant word line is checked.

5. The method of claim 4, wherein,

And when the failed word line address related to the word line which is currently being read is recorded on the first redundant word line, reading the data in the replacement memory cell in the third redundant word line to replace the failed memory cell according to the failed word line address and the failed bit line address corresponding to the failed word line address recorded on the second redundant word line.

6. The method of claim 1 or 2, wherein,

And when the plurality of word lines in the configuration module are sequentially subjected to data reading, storing the invalid word line address on the first redundant word line and the invalid bit line address on the second redundant word line into a register in advance.

7. The method of claim 6, wherein,

When the plurality of word lines in the configuration module are sequentially data-read, it is checked in the register whether there is a record of the failed word line address related to the word line currently being read.

8. An apparatus for improving data accuracy of a configuration module of a NOR FLASH memory, the configuration module comprising:

A redundancy word line unit including a plurality of redundancy word lines,

The device comprises:

9. The apparatus of claim 8, wherein,

10. The apparatus of claim 8 or 9, wherein,

The first redundant word line recording module and the second redundant word line recording module store the failed word line address and the failed bit line address corresponding to the failed memory cell in association corresponding to the failed memory cell.

11. The apparatus of claim 10, wherein the device comprises a plurality of sensors,

The configuration module is also provided with a register, and the reading module stores the invalid word line address on the first redundant word line and the invalid bit line address on the second redundant word line into the register in advance when sequentially reading data from the plurality of word lines in the configuration module.

12. The apparatus of claim 11, wherein the device comprises a plurality of sensors,

The read module checks in the register whether there is a record of the failed word line address associated with the word line currently being read when sequentially reading data from the plurality of word lines in the configuration module.

13. A storage medium storing a computer program which, when executed by a processor, implements the steps of a method of improving the data accuracy of a configuration module of a NOR FLASH memory as claimed in any one of claims 1 to 9.

14. A memory device comprising a memory controller including a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps in the method of improving the data accuracy of a configuration module of a NOR FLASH memory as claimed in any one of claims 1 to 9 when the computer program is executed.