JPS58206252A - Monitor circuit for circuit quality - Google Patents

Abstract

PURPOSE:To always estimate and detect the circuit quality without inserting a specific signal for inspection of circuit quality, by making use of a bit error correcting circuit of the receiver side. CONSTITUTION:The figure shows the relationship between the S/N during the soft decision and the average increment of the maximum likelihood pass-metric. While the relation between the average increment of the maximum likelihood pass metric and the bit error factor can be quantized by synthesizing the relation between the S/N during the soft decision and the logical bit error factor of the entire system including a coder and decoder. Therefore the maximum likelihood pass metaric delivered from a bit decoding circuit 1 is fed successively to an averaging circuit 5 to extract the average value. Then this average value is fed to an bit error factor converting circuit 6, and therefore the bit error factor of the entire system can be delivered. Thus it is always possible to monitor the circuit quality in real time by monitoring the output of the circuit 6. A pass metric normalizing circuit 4 is provided to suppress the pass metric within a finite capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a line quality monitoring circuit for detecting the line quality status (for example, bit error rate) of a satellite communication channel.

[Technical background of the invention and its problems]

In satellite communication lines, the quality of the communication line fluctuates and deteriorates due to rain, etc., so the line status must be constantly monitored in the receiving state, and in some cases, the monitoring results are conveyed to the transmitting side and the transmitting side magnetic force controls. Conventionally, a specific signal for the line quality status is inserted into the transmitted data and that signal is extracted from the No. 4 data in order to closely monitor the receiving line status where the line unavailability rate is being improved. The reception status was checked depending on the situation, but this often resulted in a decrease in the weekly news information area, and when trying to produce good line quality, the transmission efficiency decreased.

[Purpose of the invention]

The present invention was devised in view of the above-mentioned drawbacks of the prior art, and by utilizing a Viterbi error correction circuit installed on the receiving side, it is possible to improve transmission efficiency without inserting a specific method for line quality inspection. The purpose of this invention is to provide a line quality monitoring circuit that constantly estimates and detects line quality without deteriorating the line quality at all.

[Summary of the invention]

The present invention applies statistical calculation processing to the path metrics that appear during the algorithm processing of the Viterbi decoding method, and estimates the line quality based on the hidden results.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a basic configuration diagram of a line quality monitoring circuit according to the present invention, which is constructed by a Viterbi decoding circuit (1) and an arithmetic circuit (2). The Viterbi decoding circuit 11) performs the normal operation of inputting the received signal and outputting the error-corrected L code data. Path metric 1 word, which is the output of 2, is input to the arithmetic circuit (2), and a line quality signal is output accordingly.

To give a detailed explanation of the non-invention, the present ζ9, proc +d
ingsof the igEE, Vol 61.1
Ho3f'268-27'8.1973 and other Viterbi decoding techniques mentioned by K (I'll summarize some of the main points.

The Piterbi J method is known as a robust error correction method for the 7τ convolution 1f code, but its structure is closely related to the intelligence of the encoder that generates the daughter code. There is.

In other words, ob, if you add the parameters of the target encoder (i.e. coding rate, bundle length), the number of internal states of the encoder is -
, the value is determined, and in this case, the Tavi algorithm is:
It is assumed that >v'f (between the row value signal series and 4) is determined between each time and that time.

Therefore, at each time, a total of as many surviving paths as the number of internal states and the same number of path metrics corresponding to each path are stored, but among them, the surviving path with the minimum path metric ( In other words, the path that is closest to the received data sequence in a 4-rate sense is the most likely transmission data, and is called the maximum likelihood path at that time, and is directly related to the determination of the decoding output.

However, it is also possible to use an arbitrary ratio in selecting the path metric, so that the path closer to the received data has a larger path metric, and in such a case,
The surviving path with the maximum likelihood path metric becomes the maximum likelihood path.

Therefore, in order to unify the two, the maximum likelihood path determined regardless of the definition of the path metric will be considered as a standard, and the path metric of the maximum likelihood path will be referred to here as the maximum likelihood path metric.

It is known that the above-mentioned Viterbi decoding method can significantly improve bit error rate characteristics, especially when used in combination with soft-decision demodulation, and is actually used in this manner.

In this case, the path metric is the symbol metric calculated for the soft decision data at each time, which is monotonous over time, according to the symbol nodrick that defines the distance 4 between the soft decision data and the transmitted symbol. The property of increasing the force a? There will be more.

Returning once again to the detailed description of the present invention.

Let tsuk be used to mean the minimum path metric.

Under these assumptions, when we calculate the relationship between the values of 2 and 3 (representing the power in soft decisions), we get the result shown in 2C, which shows that there is a very specific and quantitative functional relationship as shown in the figure. .

Furthermore, as is clear from the above explanation, the maximum likelihood path metric is a quantity generated in the process of processing the algorithm itself, and therefore is independent of specific transmission data.

Therefore, by using this relationship, communication products and Tavi decoding circuits (1) can be calculated by focusing on a single quantity, the path metric, that appears in the 1st process, without depending on the actual transmitted data.
It consists of an averaging circuit (5) and a conversion circuit (6).
The ratio can be output from the arithmetic circuit tz+. However, in the M3 diagram, (4) is the path 7) IJ rack normalization circuit for keeping the path metric within the finite valley amount.

Now, the maximum likelihood path metric output from the Viterbi decoding circuit (1) is input to the averaging circuit t5), and the output average value is input to the conversion circuit (6), where the bit error rate is output. d! The operating principle of the circuit shown in Figure J3 is explained as follows.

As already shown in Figure 2, the relationship between S/l''J and the corresponding fund 1-ring pit error rate (which can be calculated) at the time of soft decision can be considered to have been established, so we can combine them. Then, the relationship between the average increment of the maximum likelihood path metric and the bit error rate can be quantitatively given as shown in FIG.

Therefore, the maximum likelihood path metrics output from the Viterbi Enoki lp1g:11 are input one after another to the averaging circuit (5) to extract the average straightness, and the bit error rate is calculated as follows: If input to the conversion circuit (6) of >, the bit error 4 of the entire system can be output. Obviously, since all of these operations can be processed in real time, it is clear that by monitoring the output of the conversion circuit (6), the line quality can be constantly monitored in real time.

The averaging circuit can be realized by a digital filter t, and the conversion circuit can be realized by 1N (read-only memory). By the way, in the 4-component shown in Figure 3, the code error rate can be displayed directly, but in some cases, the code error rate itself may not be displayed, but the 8/LN of the received signal or other similar quantities. If so, since they have a quantitative functional relationship with each other, it can be done by appropriately configuring the conversion circuit.
It is also possible to extract these values according to the purpose.

(Effects of the Invention) As described above, according to the present invention, communication is performed independently of transmitted data by utilizing the characteristics of the Piterbi decoding method itself.
, F. 2. I guess. Moreover, since the derivation process effectively utilizes the quantity that appears during the decoding operation, it is possible to provide an effective l-quality monitoring circuit with a small amount of additional calculations.

[Brief explanation of the drawing]

Fig. 1 is a basic configuration diagram of the reversibility quality control +A circuit according to the present invention, Fig. 2 is a relationship between the average increment of the maximum likelihood path metric and the reception name/N, and Fig. 3 is a diagram showing the relationship between fc → FIG. 4 is a circuit configuration diagram in one embodiment of the present invention, and is a characteristic diagram showing the relationship between the bit error rate and the average maximum likelihood path metric. 1... Dotabi decoding circuit 2... Arithmetic circuit 3... Pitabi decoding circuit 4... Path metric normalization circuit 5... Averaging circuit 6... Odor changing circuit agent Patent attorney Norichika City (1 other person) No. 1 No. 2 E b/r'Jo (dB)

Claims (4)

[Claims] (1) A Viterbi decoding circuit that takes the received signal as an input and outputs decoded data that has been subjected to error correction, and a path metric signal that is taken out as a second output from this Viterbi decoding circuit and outputs a line quality signal. 1. A line quality monitoring circuit comprising: an arithmetic circuit that performs the following operations. (2) The path metric signal input to the arithmetic circuit is the maximum likelihood path metric at that time. A line quality monitoring circuit according to claim 1. (3) The Viterbi decoding circuit is equipped with a path metric normalization circuit, and the path metric signal input to the arithmetic circuit is the maximum likelihood path metric obtained by x-normalizing the path metric at each time in the Viterbi decoding circuit. A line quality monitoring circuit according to claim 1 of the fourth patent. (4) The line quality monitoring circuit according to claim 1, wherein the arithmetic circuit includes an averaging circuit. 15) The line quality monitoring circuit according to claim 1, wherein the arithmetic circuit is constituted by an averaging circuit and a conversion circuit.