JPS58206161A - Process control system - Google Patents

Abstract

PURPOSE:To reduce the quantity of variation of the electric characteristic to be generated at the manufacturing process of a semiconductor element by a method wherein the channel doping quantity under a gate is adjusted conforming to impurity density of a substrate and the deviation value of the shape of the gate from the aiming value. CONSTITUTION:At the manufacturing process of the semiconductor element having gate structure of an MOSFET, etc., the sheet resistance value is measured at first to be inputted to a CPU, and the impurity density of p type Si substrate 101 is calculated. Then after an oxide film to isolate between the FET's is formed, channel width (w) is measured. Then an oxide film is formed on the whole surface of the substrate, and film thickness (d) of the gate oxide film 102 is measured. Then channel doping is performed according to ion implantation to form a p type surface inversion layer in the whole region of the surface of the substrate. At this time, the channel doping quantity is calculated according to operation from impurity density of the substrate and the measured values (w), (d). After then, diffusion layers 103, 104 and electrodes 106, 107, 108 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for controlling the process of channel doping/doping under the gate of a semiconductor device having a gate structure of MQSPET8, and particularly to a method for controlling an LSI manufacturing process in which individual devices are miniaturized. 1ill Regarding the secondary blade type.

In the conventional MQSPET "IJ, f% process, the word of mouth of each process and the operation items are fixed to a pre-designed candy, and the target value of the subsequent) process is fixed due to the fluctuations that occurred in the previous process. Since there was no practice of shaking the operating cylinder or the operating cylinder, there was a drawback in that fluctuations that occurred during the process directly affected the fluctuations in the characteristics of the element.

An object of the present invention is to provide a process control method that reduces the amount of variation in the electrical characteristics of semiconductors such as MQSPET.

Although the electrical characteristics of MQSPET vary depending on the substrate impurity concentration and the gate shape, we conducted a simulation to demonstrate that the variation in electrical characteristics can be reduced by adjusting the channel doping amount according to each change. ,
Confirmed by experiment.

The present invention focuses on these points, and the substrate impurity concentration,
The motivation lies in the fact that the dead body A1 is detected from the target value of the gate shape, and the channel doping amount f under the gate is adjusted based on that saliva.

An embodiment of the present invention will be described below with reference to the drawings.

The first is the first generation of the structure of the FET in the NtO8FET]
shows. The substrate 101 is p-type silicon, and therein is a 01 type source diffusion layer 103 and a drain/diffusion k t
04, a p-type surface diffusion Iso (channel portion) 105 is formed. On the channel 105 is a cateacetate film 10.
2 is the drain expansion on the source diffusion layer 103? +1)ll on layer 104 and gate oxide 19102, respectively.
06.107. l 08 has been formed. Ke =
1. Oxidation) The shape of 1ψ102 is a rectangular parallelepiped, and its size is determined by the thickness d1, length z, and IIMW. FE
It is separated by a phosphorized membrane between V1 and T.

Impurities for forming the p-type surface diffusion rm 105 in the form h7 are implanted into the substrate surface by channel doping.

Next, a control equation for determining the amount of impurity in channel doping so as to keep threshold 1 constant and pressure constant will be shown. The threshold voltage (hereinafter referred to as Vih) is 1'vlO8I''
19. This is the basis of ET and is generally a surface inversion between the source and drain.・The number of carriers inside is the key sr IJ of the board
It is defined as the state where the number is equal to the number of In actual measurements, the drain pressure is often fixed at 71411 in some ten steps, 4)
1. The 1-point also changes depending on the fixed law. In this example -
The drain η of the current is treated as a gate voltage with care. First, regarding Vsh, the following one-body difference equation (1) is used.

However, vtho = target 1st straight N of the 1st straight stop' pressure:
Impurity density of silicon substrate (side lid 11 white) N. : Impurity density of silicon substrate (direction of 14 tanks) d : Gate oxidation) thickness (measurement (16)) do : Gate oxide film thickness (measurement) t : Channel length (measured value) to : Channel length (measured value) (Direct) W:: Channel width (measurement end) Wo: Channel width (target (direct)) NDII: Channel doping interval (operation (!#) ND
IIO: Channel doping amount 1 quasi-1 straight) a, ~a,:
According to the coefficient equation (1), after obtaining N, d, L, and W, the sub-side equation for determining the operation of the channel doping amount so as to eliminate the deviation from the target value of Vo is (2 ) formula is obtained.

The entire root of equation (1), which is the basis of equation (2), is shown below.

According to the one-dimensional model in the substrate depth direction, vtb is calculated using formula (3)%
Formula% Tatashi, VF! l :Flat pad/de'fill FF
φr: Fermibodenon Yar Q of the board! l: t-load in channel depletion layer CoX: Gate oxide bomb Nng: Channel doping - First, N, sulfurization is expressed as a change in Q- in the third term of equation (3), and d and ( Since the relationship between `` and .

However, regarding the electrical coefficient t of C@dioxide film, 1-11. Due to the increase or decrease of t, Dreno'ton1
-V because t changes the ringing of the map on the channel
s h changes. This phenomenon is usually called knowledge channel effect.

That's naive. Regarding W, if the impression force is 0'lIl pressure bundle column is equal, the drain ゛i,''1 will also increase or decrease according to the increase of W 7Aυ.
V th changes because of one stone.

The change in N o s (7) mainly affects V th as a change in the fourth term of equation (3).

Coefficients a, -, -a, i, j: Calculated as follows. N
Aim for 1゜d+Z+w (in the nearest child, change NDlI to (dust Y(straight hair f′;
” E Ti is created and Vtb is determined by four rivers.Using this result, multiple regression analysis is performed to calculate !7 coefficients a, ~aS
Establish.

The device configuration of the embodiment of the present invention is shown in FIG. 2, and the processing flow of the CPU is shown in FIG. Fig. 3 also shows the order relationship between the processes related to this embodiment during the )'E'I' manufacturing process and the processing of the CPU. 111i1ffl will be explained.

At the same time, the coefficient a of equation (1), ~a, is applied to CP11201.
+ do + ZOI WO% Channel Dobi 7g Ha no Sho...Pal value NO! 10 (step 40)
1). Yoshitsu, repeat the 1ζ-■rie 1ri until the 1-1 ri is completed.

In the board inspection process 301, the resistor 4-phase regulator 202 determines that the board's 7-tt''> anti-1 f 1i11i '+i'
-r (step 402). CPt1201i1T1 1st part is input 7, and 1st bud 11r N of the board is output (step 403).

Next, in a first oxidation process 302, acid and vinegar are added to separate the FETs, and the channel width W is determined using a dimension measuring device 203. CP[J201haso(
1) (Enter IS (step 404). Next,
In a second oxidation process 303, an oxide film is formed on the entire substrate,
Membrane j! ν昘15? The thickness d of the Kate oxide film is 4 using the container 204.
(11) Enter the f target in CP [-1201 (step 405).Next, ion implantation process 3
04, a p-type surface inversion layer is formed over the entire surface of the substrate without channel doping. In this case, N.

w and d have already been determined, but since t is the next office, c p tl201 is calculated by removing the term t from equation (2) (
5) Cut out the channel-doped MNosi, transfer it to the ion implantation device controller 205, and apply it to the ion implanter controller 205 (step 406).

Remove the oxide film on the drain and check the size. Then, the length t of the gate oxide film 102 is determined by the III regulator 206.
reactor.

CP tJ 201 enters its Inn, 7E, (
Step 407).

In addition, there are many processes! l] Then, form n+ expansion 11 layers 103, 104 and electrodes 106, 107, 108 [
7 to create a PET (ρ, Nity test process 3f)
At step 6, Vth is set to 6 using the C tester 207.

CP LJ 201 ('j Vth khuman power, -(
(Step 1408) In addition to formula (1), numbers a1 to a are corrected (step 409).

An example of how to correct θS for faa+ to q in equation (1) is shown below. Itt of i-1, i, i+1 in chronological order
It is assumed that processing is performed in r+ order. For the i-fold element (
1) The 71+11 constant of each variable in the formula is ~'tb(1)
+ N, (i), d(i).

t(i), w(i), doy+sakushu'< No8(i
), the coefficient Pl of equation (1) is a, (i ) ~ a , (i)
It is expressed as The coefficient a for the i+1th element, (i4-1)
The method for determining ~a, (i+1) is as follows. First, solve the simultaneous equations (6) obtained from the 11th fixed candy and the 1st operation from the i-4th to the i@th to obtain ar to az.

= 0 ...... (6) Here, k = i -4, i -3, ......, ia
, / ~a, / as is aI (I+1) ~a,
(i+1), the noise generated in the process and l'
There is a possibility that it may be affected by Ijl constant noise.

Therefore, in order to stably control the process, filtering techniques are used to determine a, (i+11 to aa(!+13). For example, it is determined by equation (7).

a, (4-1)=ajfil-t-β('dr at
(i) l-=-17) J-1, ......, 5 where β Gebu
Find the optimal value within lIn. .

As described above, according to the present invention, it is possible to reduce the amount of variation in the electrical characteristics of a semiconductor element caused by contamination of the substrate and variation in the shape of the gate. the result,
Uniformity of device characteristics is improved.

[Brief explanation of drawings]

FIG. 1 shows the structure of an example of the FET in Mo5LSI according to the present invention, FIG. 2 shows an example of the device configuration according to the present invention, and FIG. 3 shows the processing in the CPU of FIG. FIG. 201...CPU, 202...Resistance measuring device, 203
...Dimension measuring instrument, 204...Pancreatic thickness illumination device, 2o
5... Ion implantation device controller, 2o6... Dimension measuring device, 207... IC tester, 301... Board inspection process, 302... First oxidation process, 3o3
...Second oxidation process, 304...Ion implantation process, 305...Etching process, 306...
Characteristics Test F O (!, x. Agent: Patent Attorney Toshiyuki Usuda No. 2 Figure No. 3 / Inside the development laboratory

Claims (1)

[Claims] In the manufacturing process of semiconductor devices with gate structures,
Process feeding 1 characterized by detecting the deviation value of the substrate impurity density and gate shape from the target pattern, and aligning the channel doping needle under the gate once based on the detection (directly based on the detection)
method.