JPS58205911A - Data slicing circuit - Google Patents

Abstract

PURPOSE:To obtain a stable slicing level at all times, by switching a slice control loop of a signal in response to a transmission speed of an input signal. CONSTITUTION:In selecting a changeover switch 14 to the terminal (2), the control of the slicing level is exercised at a maximum pulse width detector 10. When an input signal source comes from a medium such as disc, the maximum pulse width detector 10 is inoperative when the medium is started from stop or at a very low speed. Thus, the fixed slicing level should be taken in this case. In selecting the changeover switch 14 to the terminal (1), a reference voltage 6 is inputted to an input B of a comparator 1 fixedly. An operating state discriminator 12 discriminates that the disc is rotated and a pulse signal is obtained, and the changeover switch 14 is selected to the terminal (2). Then, the stable slicing level is obtained at all times in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform shaping circuit in a digital data transmission system, and particularly to a data slicing circuit that converts a signal reproduced from a recording medium into a digital signal.

Characteristics of digital data transmission paths, especially when reproducing signals from a digitally recorded disk or tape recording medium, due to distortion during recording to the recording medium and distortion during reproduction.
This causes asymmetric distortion of the positive and negative levels of the signal. When a signal having this asymmetrical distortion is converted into a digital signal through a data slicing circuit, the signal is divided into fluctuations in pulse width, causing data identification errors. As a means to improve this shortcoming,
The slice level control method is shown in FIG. 1 of the earlier application.

The method of controlling the slice level will be explained with reference to FIG.

In Fig. 1, 1 is a comparator, 2 is a signal input terminal, 3 is an output of the comparator, 4 is a positive/negative pulse width detector, 5 is its output, 6 is a base pressure, 7 is an adder, and 8 is a It is a digital signal processing circuit, and the B input of the comparator 1 becomes the slice level of the 20 input signals. An input signal detected from a recording medium is sliced by a comparator 1, and its output 6 is input to a digital signal processing circuit 8. Positive/negative pulse width detector 4
detects the positive and negative pulse widths of a specific pattern (synchronization signal, etc.) whose pulse widths are divided in advance, and outputs a voltage according to the difference.The slice level of comparator 1 is set to the reference voltage 6 This becomes a signal added to the output of the pulse width detector 4, and is added to the input of the comparator 10B.

Next, the operation of the circuit shown in FIG. 1 will be explained using the waveforms shown in FIG. 2.

The human input signal 2-1 (thick solid line) shows an example of a synchronization signal pattern. In this example, the synchronization signal is a pulse signal with a basic cycle unit of "1°" and a negative pulse width of 11T and a positive pulse width of 111. It is a signal with a duty of 50% with exactly 22T as one cycle. Now, assuming that the input signal 2-1 is in a normal form without distortion, the base r! ! - It is sliced at the slice level 9-1 determined by the voltage source 6, and the output M5-1 of the comparator 1 obtains a pulse signal having a pulse width of 11T-111. This means that the signal that was originally intended to be transmitted was correctly reproduced.

By the way, in the case of the distorted signal shown in the input signal 2-2 (broken line), if sliced at the slice level 9-1, the output signal 6 will not have a correct pulse width as shown in the signal 3-2. (6-2 shows an example when the signal becomes qr-137''.) In this case, the positive/negative pulse width detector 4 calculates the difference between 9T and 13T, and calculates the difference signal 4T.
The input pressure of the converter 10B is controlled via the adder 7, and the slice level is changed.

By slicing the input signal 2-2 at the slice level 9-2 controlled in this manner, the output signal can obtain a pulse width of 117, 11T, such as -3-3.

Now, in the above method, the synchronization signal 11 no = 11 T-
The condition is that a 5% constant pattern exists. In other words, control is possible only within the operating range in which the synchronization signal is received. However, a synchronizing signal cannot be obtained until the signal source reaches a steady running speed or when the signal medium, such as a disk record or tape, stops feeding, and the above method cannot control the slice level.

There is a maximum pulse width detection method that can be used without a specific parameter such as a synchronization signal. Normally, the maximum and minimum values of the pulse width of a human signal are predetermined, so the maximum value of the positive pulse width and the maximum value of the negative pulse width are extracted, and the difference between the respective pulse widths is calculated using the data as in the previous method. This is calculated as a tee difference and attempts to control the slice level.

However, there is a risk that scratches on the recording medium or noise may be detected as the maximum pulse width signal.

An object of the present invention is to provide a data slicing circuit that always performs optimal data slicing by switching a signal slicing control loop according to the transmission speed of an input signal.

For this reason, the present invention is applicable to states in which the waveform of the input signal changes, that is, the transmission speed of the C signal, which corresponds to the feeding speed of the signal recording medium, is stopped or slow; (i) the transmission speed is accelerated; 0) transmission speed; The problem is solved by dividing the signal waveform into a stable state and a 0) state in which the signal waveform is incorrect, and switching to a signal slicing circuit suitable for each state.

Embodiments of the present invention will be described below using a PC'M disk signal reproducing circuit. The signal transmission speed corresponds to the rotation speed of the disk, and the disk can go from a stopped state to an accelerated state to steady rotation.

The explanation will be divided into special rotation states such as and random access.

FIG. 3 shows a first embodiment of the invention. The additions from Figure 1 are: 10 is a positive/negative maximum pulse width detector, 11 is the same output signal, 12 is the operating state discriminator, 13 is the same output signal, 14 is the changeover switch, and 15 is the same output signal. .

A PCM signal reproduced from the disc is applied to the input terminal 2. The PCM signal is a modulated wave having a fundamental period T and a pulse width of 6T to 11T for both the positive pulse and the negative pulse.

A signal for comparing the stop pulse width and the negative pulse width must be extracted from the randomly input PCM signals. When the slice level is not appropriate, the problem is which pulse signal to compare.

Therefore, the maximum positive pulse width input within a certain time,
When the maximum negative pulse widths are compared, it follows from the nature of the PCM signal that signals corresponding to pulse widths of positive 111' and negative 111' are compared.

The positive and negative maximum pulse width detector shown in FIG. 6 and 10 has this function. When the selector switch 14 is turned to terminal (2),
With this maximum pulse width detector, the slice level explained in FIG. 1 can be controlled.

By the way, if the input signal source comes from a medium such as a disk, the signal is not detected yet when starting from stop. Also, the input pulse width at extremely low speeds is considered to be very long. , no matter how many digits the counter for pulse width detection has, there are not enough digits.Then, the maximum pulse width detector becomes disabled.Therefore, when starting from this stop, the slice level should not be set to the automatic open side 1. , it is necessary to set the slice level to a fixed level.
) terminal is IL to create the slice level of measurement.

When the changeover switch 14 is turned to (1), the changeover switch 14
The output 15 of is "O" level addition j1. Vessel 7v Koha Iro]
The voltage of the reference voltage 6 is fixed to the B input of the comparator 1.

Operation status 79 'I' (The I distinguisher 12 determines that the disk is rotating and a pulse signal is obtained and starts, and switches the selector switch 14) from l(1+ to (2). As a result,
At the start of the disc, it becomes a skill to smoothly control the slice level of No. 46.

As described above, the slice level control by the positive/negative maximum pulse width detector 10 operates regardless of the signal transmission speed, but the maximum pulse width may be erroneously detected due to scratches or disturbances on the disk. Next, we will discuss the control of the optimal slice level when the V-disc is in steady rotation.
A random signal is always input to the data part of the PC'M signal, but the synchronization signal has a specific pattern and is fixed. And since it always exists periodically,
By detecting the positive and negative pulse widths of the synchronization signal and using it as a slice-level control signal, reliability can be improved compared to the maximum pulse width detection method described above.

FIG. 4 shows an example thereof. 16 is a synchronizing signal positive/negative pulse width detector, 17 is the same output signal, and 1B is a synchronizing signal amount force. The synchronizing signal positive/negative pulse width detector 16 is connected to the terminal (3) of the changeover switch 14 in parallel with the positive/negative maximum pulse width detector 1o. The synchronization signal 18 detected by the digital processing circuit 8 is input to the operating state discriminator 12 and the synchronization signal positive/negative pulse width detector 16 . A synchronizing signal positive/negative pulse width detector 16 generates an analog signal at an output 17 corresponding to the positive pulse width 11T and the negative pulse width 11 of the synchronizing signal. The detection rate of the synchronization signal 18 becomes high as the rotation of the disk becomes steady rotation, and the detection rate becomes nearly 100% when the disk rotation becomes steady rotation.

The operating state discriminator 12 monitors the number of inputs of the synchronization signal 18 (-detection rate) and determines whether the disk is rotating normally. For example, when the changeover switch 14 is turned to the (3) terminal with a synchronization signal detection rate of 50, the output signal 15 of the changeover switch 14 will be the difference between the positive and negative pulse widths obtained from the synchronization signal positive and negative pulse width detector 16. A corresponding voltage is sent to an adder 7 to control the slice level.

To summarize the flow of the above operation, the selector switch 14 is set to (1) until the width of the pulse can be detected from the stop state of the disk, which is the signal source, and the slice level is fixed at the constant voltage of the reference pressure source 6. Ru. Then the disc rotates and
When the pulse width can be detected reliably, the selector switch 14 is turned to (2), and the positive/negative maximum pulse width detector 1
The slice level is controlled by the output signal 11 of 0. Next, the disk becomes steady rotation, and the synchronization signal 1
When 8 is obtained, the selector switch 14 changes to (3),
By the output signal 17 of the synchronization signal pulse width detector 16,
Slice level is controlled.

Next, a hold circuit will be added to the circuit of the previous embodiment and a circuit will be explained. The purpose of the hold circuit is to prevent abnormal changes in pulse width due to disturbances in signals during steady rotation of the disk, thereby preventing slice level control from being disrupted.

For example, this may occur when the reliability level is significantly degraded due to a large scratch on the disk, or when a signal track is jumped to randomly access information on the disk.

FIG. 5 shows an embodiment of the hold circuit.

19 is a switch, 20 is a capacitor, 21. is a hold controller, and 22 is its output signal.

Switch 19 is normally in the 01V state. capacitor 20
The voltage of the slice level control that comes from the changeover switch 14 is charged with a single charge. When the signal level at the input terminal 2 becomes small, the hold controller 21 switches the switch 1
Turn 9 off. Then, the capacitor 20 holds the voltage immediately before the switch 19 opp' and keeps the slice level constant. This makes it possible to prevent deflection at the slice level. Also, if it is known in advance that the input signal 2 will be disturbed due to random access, etc., a signal is sent to the hold controller 21 before operation, and the above and four-way switch 19 are activated.
It is also possible to hold the slice level by setting it to op"p'.

Although the above-described hold circuit holds the analog value using the capacitor 20, the hold circuit can also be implemented by cutting off the latch clock signal at the digital output in the pulse width detection circuit.

In the embodiment shown in FIG. 6, the "f reference voltage 6 and adder 7 shown in the previous examples are omitted. A voltage corresponding to the reference voltage 6 is stored inside each pulse width detector (10° 16). The operation for controlling the slice level is the same.

The voltage source 21 connected to the terminal (11) of the switch 14 is
This is a fixed voltage corresponding to the reference voltage 6.

The basic operation of the present invention has been explained above using block diagrams. Next, the circuits in each block will be specifically explained.

FIG. 7 shows an example of the synchronizing signal pulse width detector 16. 2
6 is a clock signal, 24 is a counter, 25 is a control circuit, 26.27 is a nip signal, 28° 29.34
is a latch, 30.51 is an output terminal of the latch, 32 is a subtracter, 33 is its output data, and 65 is a clear signal.

The operation will be explained with reference to FIG. 7 and the time chart FIG. 8. 11T~1 so as to overlap input signal 2 in Figure 7.
Let us take as an example the case where a 1T synchronization signal is input.

In FIG. 7, 18 is a counter 1 that measures the pulse width.
9 clock, and has a period of 1/8 of the basic period T. 25 is a control circuit, and output signals 26 and 27 are negative etch and positive etch signals of input signal 2. Also, -
Reference numeral 65 is a shifted edge signal of the above two glazes, and is a clear signal for clearing the counter 24. Latch 28 latches a positive pulse width on edge signal 26. The data α corresponds to a count number of 88 if input number 2 is accurate. Latch 29 latches the negative pulse width in edge signal 27. Similarly, the data b corresponds to a count number of 88 if the input signal 2 is accurate. Reference numeral 18 designates a synchronization signal output of the digital signal processing circuit 8, which includes a synchronization signal detection circuit. When the output of the subtracter 62 which inputs data α and data b is latched using the synchronizing signal output 8 as a clock, the latch 64 obtains a differential signal, ρ(α−b).

The output data (difference signal α-b) is time information, and must be converted into an analog signal in order to control the slice level of the comparator 1.

Therefore, the digital information in the latch 64 is once converted into a PWM signal, and this is smoothed by C'R to become an analog signal.

Next, a specific circuit of the maximum pulse and width detection circuit will be explained with reference to FIGS. 9 and 10. Figure 9 is an application of Figure 7, and the new additions are 56 latches, 36 comparators, 3
7 is its output, 68@bugame), 39,40.4
2 a clock signal, 41 a data selector, and 41 an etch signal. The counter 24 counts the clock 26, and the count value is latched into the latch 56 using the edge signal 46 of the input signal 2 as the clock. After latching, the counter is cleared by a clear signal 65. The data in latch 56 corresponds to the pulse width of input signal 2. U1. The output of the /chi 56 is compared with the B input signal of the comparator 36 as the A input signal. The B input signal is the data selector 41
The output signal of the positive pulse width latch 28 or the data of the negative pulse width latch 29 is selected.

Now, when the pulse width latched by the latch 56 is C shown in FIG. 9, C is a positive pulse, so the data selector 69 selects B. When "A>B", the output 37 is set to a high level voltage.

Now, the content of C data of input signal 2 is count number 96,
If the output data of the latch 28 is 90, then 96) 6
0, the output 37 becomes a no-y level, and as a product of the clock signal 44, the latch 2 is output through the gate 38.
Clock signal 40 is input at 8, and the contents of latch 28 are converted from 90 to 96.

That is, when the previous data is greater than the latch.

Contents are converted. It has a function to hold the maximum value.

Similarly, the maximum value of the negative pulse is held in the latch 29. The outputs of latches 28, 29 are input to subtracter 32, whose output 66 is connected to the input of latch 64. latch 6
The clock signal 42 of No. 4 is a clock generated at a certain constant period, and when the clock signal 42 is generated, the output 33 of the subtracter 32 is latched into the latch 34. At the same time, latch 2
8.29 is cleared and latch 28.29 restarts as maximum pulse width detection.

That is, the difference between the maximum value of the positive pulse width and the maximum value of the negative pulse width is stored in the latch 34 every 420 cycles of the clock signal. In the time chart of Fig. 10, latch 6 is finally
4 stores data "12" of "96-84".

The above is the specific circuit of the positive/negative maximum pulse width detector. Note that the output data is converted into analog as described above.

Next, an embodiment of the present invention will be described in which the synchronizing signal positive/negative pulse width detector 16 described above and the positive/negative maximum pulse width detector 1o are shared. A diagram of its principle is shown in FIG. 66 is a comparator, 37 is its output, 46.54 is a latch, 55,
51 and 52 are clocks, 47 are control lines, 48 are ORKATE, 49 are ANDKATE, 53 are clock selectors, and 54 are pulse width data.

The latch 46 latches the maximum value of the pulse width data 54. The input and output signals of the latch are connected to a comparator 66 in order to latch up to 11L as shown above. The output 37 of the comparator 36 is passed through an OR gate 4B and an AND gate 49, and its output becomes a clock input for driving the latch 46.

Further, the latch 34 is provided to latch the data of the latch 46 at a predetermined cycle. The latch 64 is driven by the clock 51 or the clock 5 via the clock selector 56.
Do it in 2. Control line 4 that is currently operating state discriminator 12
7 is at a low level, the OR gate 48 is conductive and the clock selector 53 selects the periodic clock 51 for maximum pulse width detection. In this state, the maximum value of pulse width data 54 is latched into latch 46 at clock 56 in response to comparator 660 output 57. Thereafter, it is latched by the latch 64 at the clock 51. Next, when the control line 47 goes high, the output of the OR gate 48 always goes high, and the latch 46 is latched by the clock 56 regardless of the pulse width. At the same time, the output of the clock selector 53 is switched to the clock 52, and the latch 64 is switched to the latch 4 by the clock 52.
6 output data is latched. The clock 52 is the PC'
If it is the same as the synchronization signal 18 of the M signal, the data launched into the latch 31 will be transferred to the latch 4 from the pulse width data 54.
Only the pulse width data of the synchronizing signal is passed through 6.

As mentioned above, when the control line 47 is at a low level, the maximum pulse width is latched in the latch 61, and when the control line 47 is at a high level, the synchronizing signal pulse width is latched in the latch 31.

FIG. 12 embodies the principle block shown in FIG. 11, and is an example in which the circuit shown in FIG. 7 and the circuit shown in FIG. 9 are used in common. Basically, it has two systems of positive and negative pulses with the addition of latches and subtracters, so I won't go into too much detail. be.

As described above, according to the present invention, the state of the transmission speed of input 4q, that is, stop or constant acceleration speed, is accurately determined, and the first optimal control method is selected based on the determined signal. Therefore, a stable slice level can be obtained under any signal input condition. Furthermore, the slice level can be held to further stabilize the input signal against temporary disturbances. Furthermore, by sharing the pulse width detection circuit, the circuit can be simplified.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of the data slicing circuit of the earlier application;
The figure shows slice levels and output signal waveforms, FIG. 6 is a circuit diagram of one embodiment of the present invention, FIG. 4 is another circuit diagram of the present invention, FIG. 5 is still another circuit diagram, and FIG. Another circuit diagram, Fig. 7 is a synchronization signal Hals width detector circuit diagram, Fig. 8 is a time chart diagram, Fig. 9 is a maximum pulse width detector circuit diagram, Fig. 10 is a time chart diagram, and Fig. 11 is a circuit diagram of the maximum pulse width detector. FIG. 12 is a common circuit diagram of a synchronizing signal pulse width detector and a maximum pulse width detector, and is a practical circuit diagram thereof. 1...Comparator 2...Input terminal 6...Reference voltage 7... -Adder 8...Digital signal processing circuit 14
......Selector switch 10...Positive/negative maximum pulse width detector 16...
... Synchronization signal positive/negative pulse width detector 12 ...
・・・・Operation state discriminator collar 1 Figure 2 Figure 3 Figure 7 Figure 8 Figure 34, - m' Procedural amendment (spontaneous) t 57929 Showa year, month, day, Showa 57 Patent application No. 87929 Invention Name Person who corrects data slice circuit 4/5fl/Tweeter Hitachi Ltd.-a 6 3 1
) Katsu Shigeyo Osamu Personal Notice jJ1-〒1t)O Tokyo, Chiyoda-ku, Marunouchi-5-1 The following sentence is added between page 21, line 16 and line 14 of the amended statement of contents. Next, a specific example of the operating state discriminator 12 shown in FIGS. 3 to 6 will be explained. FIG. 13 shows a circuit that counts the synchronization signal 180 manual strokes and determines whether or not the disk has started rotating normally. 61 is a counter 61 that counts the synchronization signal 1S, 65 is a counter that divides the frequency of the clock 64, and 65 is a latch. 66 Haratsuchi output. The counter 61 receives the synchronization signal 18
When the count exceeds a specified number, an output signal is sent to the data input of the latch 65. The predetermined number may be any value that corresponds to a synchronization detection rate of 50%, for example. counter 63 beam atsuk 6
4 is divided (counted) to create a reference time for synchronous signal counting. The output of the counter 63 sends a latch signal to the rack 65 to latch the latch data manually. The output 66 of the latch 65 is passed through the OR gate 74 as the output 16 of the °C operating state discriminator 12, and becomes an output signal indicating whether or not the disk is rotating normally. Further, 73 in FIG. 13 is a mieto signal of the reproduction signal, and when mieto is released, it is determined via the OR gate 74 that the disk is rotating normally, and a signal is output. FIG. 14 shows a specific example of the operating state discriminator 12 that determines whether the disk has started to rotate. counters 62, 67
is a counter that measures the pulse width of the comparator output 8. The counter 62 measures the positive pulse width of the comparator output 8;
Counter 7 measures the negative pulse width by inverting comparator output 8 with inverter 9 . counter 62,
67 is the counter value corresponding to the specified pulse width. The output is sent to AND gate 70. and gate 70
determines that both the positive pulse width and the negative pulse width have become specified pulse widths, and sends the output to the data terminal of the latch 71. The counter 65 and clock 64 are used to create a reference time as in FIG. 13, and their outputs are used to latch the latch data input signal. The latch output signal 72 becomes the output of the operating state discriminator 12, that is, the output indicating that the disk has started to rotate. Note that the clock 75 is a signal for measuring the pulse width. FIG. 15 shows the operating state discriminator 12 and the hold controller 21.
This is a concrete example. Here, we will explain the operation when random access is performed by -5ff in the disk operation. The output signal of the pulse 1 quotient horizontal output device 76 is sent to the output part 86 via the launch 77. The latch 77 outputs the latch signal 79.
is controlled via an AND gate 78. 82 is a keyboard for operation and a manual part for random access for selecting one song. The output signal of the keyboard 82 is sent to the operating state discriminator 80 via the microcomputer circuit 81. The working state discriminator 80 uses the signal to detect disturbances in the disk detection signal due to random access, etc., and outputs a hold signal 86. At this time, the hold signal 83 becomes Low level, and the AND gate 78 cuts off the latch signal 79. Therefore, latch 17
The output 83 of holds the previous data. As a result, stable operation can be maintained without disturbing the reference voltage of the comparator even when the disc reproduction signal is disturbed due to random access or the like. 2. The ``deru.'' on page 22, line 14 of the detailed description is written as a picture of the first bell of the ``hihold fffii goki''. ” is corrected. '5. Figures 13 to 15 are added as shown in the attached sheet. More than 14 years old

Claims (1)

[Scope of Claims] 1. A signal reproducing device comprising a comparator that compares an input signal with a predetermined reference voltage, and reproducing the original signal with a signal processing circuit that inputs the output signal of the comparator as an input signal, wherein a device, a plurality of references 1 connected to the switching device comprising a pressure generator and an operating state discriminator for determining the operating state of the signal reproducing device, the switching device output being a predetermined reference voltage of the comparator; . A data slicing circuit, characterized in that the switching device is controlled by the output of the operating state discriminator to switch a predetermined reference voltage of the comparator. 2. The data slice circuit according to claim 1, further comprising a voltage holding circuit for holding the reference voltage of the comparator by the operating state discriminator. 3. At least one of the plurality of reference voltage generators generates a voltage according to the pulse start-stop negative asymmetry in the pulse signal output of the comparator, and the data slice circuit according to claim 1, wherein: . 4. The voltage generator is configured so that the input No. 4g of the comparator is the predetermined base I! a positive pulse width detector that detects a pulse width in a positive region larger than 4 voltage; a negative pulse width detector that detects a pulse width in a negative region where the input signal is smaller than the predetermined reference voltage; and the positive pulse width detector. 19. The data slicing circuit according to claim 19, wherein the data slicing circuit comprises an arithmetic unit that calculates the difference between the output of the detector and the output of the negative pulse width detector. 5. The positive pulse width detector and the negative pulse width detector are
%el to detect the maximum or minimum value within a predetermined time
The data slicing circuit according to the first item in the scope of F. Zhao Qiu. 6. AiJ Kiki 4! Of the voltage generators, there are a few
2. The data slice circuit according to claim 1, which uses a specific pattern such as a synchronization signal that periodically exists in the input signal 4B, and generates a voltage according to the asymmetry of the positive and negative pulse widths of the specific pattern. 7. At least one of the standard military pressure generators listed in M'll
The data slice circuit according to claim 1, which generates a fixed voltage. 8. The data slice circuit according to claim 1, wherein the operating state discriminator discriminates whether the maximum pulse width or the minimum pulse width within a predetermined time is greater than or equal to a predetermined value. 9. The data slice circuit according to claim 1, wherein the operating state discriminator discriminates whether or not a specific pattern such as a synchronization signal is present in the input signal. '10 The data slice circuit according to item 1, wherein the voltage holding circuit is controlled by the output signal of the input signal magnitude adjustment circuit. 11 The reference voltage generator and the switching device
a latch, an input signal of the first latch, a comparator that receives the output signal of the first latch, and a first clock line that is controlled by the comparator and connected to the first latch. a second latch that receives the first latch output signal as an input, and a selection switch that selectively selects the second and sixth latch clock lines and leads them to the second latch; A data slice circuit according to claim 1, which simultaneously controls said selection switch and conducts and cuts off said comparator output.