JPS58205281A - Fast fourier transformation device - Google Patents

Abstract

PURPOSE:To read and write data in and out of two alternate RAMs and to speed up arithmetic operations, by using two of three program counters for reading data and the remaining one counter for writing data. CONSTITUTION:An arithmetic device performs fast Fourier transformation (FFT) at a high speed by butterfly arithmetic and its butterfly arithmetic processing part 1 employs the pipeline structure where latch circuis 7, 8, and 9 are provided between two sum of products arithmetic circuits 5 and 6 parallel to an adding and subtracting circuit 4 between input and output data buses 2 and 3; and two of three program counters 18, 19, and 20, i.e. 18 and 19 are used for reading data and the remaining one counter 20 is used for writing data to write and read in and out of RAMs 13 and 14 without any latency time. Therefore, the arithmetic time of FET is shortened.

Description

[Detailed description of the invention] The present invention relates to an arithmetic device intended to increase the speed of processing.

Basically, butterfly lS. The calculation time varies depending on the configuration of the arithmetic processing device and the program used when executing this method.

Although it is generally desired that the calculation time be short, F F T
It is well known that when applied to audio signal processing h4, real-time processing is often required, and that shortening the calculation time requires special implementation.

However, the conventional OFF '11'' arithmetic device generally has to perform random access memory (hereinafter referred to as T'HAM) and memory while the RAM is reading data. In this case, there is a problem in writing the calculation result that has already been obtained, which impedes the speeding up of the calculation, which is characteristic of the data read end 1.

The present invention was made in order to solve all the problems of the conventional FFT nose performer as described above and completely improve the calculation level.
A launch circuit is provided between several J-number performance instrument circuits to create a pipeline structure, and as an address sequencer, there are 31-direction program counters, two of the circles and another one for data reading. An object of the present invention is to provide a fast Fourier transform device which is used for writing all data and allows two RAMs to read and write data alternately. will be explained in detail with reference to drawings showing one embodiment.

FIG. 1 is a diagram illustrating the butterfly calculation method of P F T.

That is, FFT samples a signal and performs discrete Fourier transform (hereinafter referred to as DFT) on a large number of sample values by dividing it into a small number of samples.
For I', all the necessary multiplications and insertions such as addition and subtraction and multiplication by constants (trigonometric functions) as shown in the diagram are carried out on each set of divided samples, and the results are further processed. Similar movements are repeated a predetermined number of times.

Conventional arithmetic device 1-J that performs such butterfly calculations
It is equipped with only one RAM and one address sequencer such as a block counter, and even if a specific operation has already been completed, writing to the 114AM cannot be done while the RAM is reading another Cheetara, so it must wait. As mentioned above, it took a lot of time to get used to it.

Furthermore, since the conventional processor has only one repeat counter in the microprogram sequencer that controls the performance procedure, the budget for repeated nesting is extremely inefficient. This also has the drawback that if no software measures are taken to avoid this problem, it is necessary to increase the capacity of the microprogram ROM.

In order to solve the problems of the conventional FFT processor as described above, the present invention adopts a configuration as shown in FIG.

That is, 1 is butterfly'fp! In the compilation department, the input and output data buses are arranged between circuits 2 and 3, one circuit 4 and one circuit! Arrange the two-blooded Iwabuchi Hayabusa circuits 5 and 6, and latch circuits 7, 8, and 6 in each darkness. and 9, and multi-flexors 10, 11, and 12. A pipeline structure is constructed in which the output from the adder/subtracter circuit 4 is sent to the chichi circuit 8 and is connected to the multibrader power data bus 3.

The two H, AM13 and 14 are connected to the output data buses 2 and 3, and are connected to the two address buses 15 and 16, and the data bus 1
5 and 16 from the address controller 17? Give instructions. At this time, the address bus 15 and ]6
Three program counters 8.19 and 20 are provided between the address controller 17 and the address controller 17, two of which are used for reading data, 18 and 20, and the other one, 20, is dedicated for writing all data. By doing so, data can be written to and read from the R, AM 13 and 14 without waiting time.

All the constants stored in the ROM 21 according to the commands from the address controller 7 are stored in the dance record circuit 5 as appropriate.
and 6 to execute predetermined calculations.

It goes without saying that the above-described calculation processing device is included in the interface 22' provided on the data bus 3, and is controlled in a predetermined procedure by the microfloclum O sequencer 23 at J6.

In the uninvented arithmetic processing device that is integrated as described above, It operates as explained below.

1) 1 Now, the data χ1. sampled through the interface 22. When I2...... is input, this data is once stored in the R, AM 13 or 14, and then sequentially read out according to the instructions 1111 of the microprogram sequencer 23 and transferred to the data bus 2. The data is sent to the butterfly calculation processing section 1 through.

At this time, the data χ1. χ2.・・・・Anki R
Writing to AM13 and AM14 is via the program counter 20, and reading is via the program counters 18 and 19, respectively.
This is done by specifying all of the predetermined addresses of AM2S and ]4.

Now, the data Z input to the Erasing Butterfly Processing Unit 1
1+χ2. ......and U y + y 2...
...('/ 1 + y2 +... VC at the start of the acid nose, is generated as a result of calculation when repeating V) is first generated by the multiplexer 10 with a predetermined silk. None, the above-mentioned p subtraction j calculation circuit 4 performs addition and subtraction for each predetermined state, and the result l7181zl+z2 is -H the latch 9
, and further stores the multi-flexure 12 in zl z2.
A predetermined constant V (triangular interval L') is inputted from (, 0N21) to the Gonwahama arithmetic circuit 5 or 6 through the Gonwahama calculation circuit 5 or 6, and the result is input to the latch 9. The stored data zI+r2 is stored in the memory 4 (in AM13).

Calculate the above here: Ayuka r1+ 12""rl, z2'c
O5θky 2' sinθ to -χ2'I, , 1
1,000y2""/1' and Z2 S] [101<10y2'
If ω(θ is −y2″, then these data?+' +
yl', z2'', and y2'' are stored in the RAM 13 or 1 again.
4 and repeats the same addition and subtraction and sum calculation a predetermined number of times to obtain the Fourier transform of sample Z1+χ2, . . . .

The detailed explanation will be further explained with reference to FIG. 3, which is schematically illustrated in relation to the butterfly operation circuit of FIG.

In Figure 3, for vibe 1, sample data 'l+
The above H, AMI 3 and 1"I in V1 and z, z+y2
.

14 and temporarily stored in the latch circuit 7.

These data are subjected to addition/subtraction operations in pipe 2.
1' + 3'1' and χ2', yz' are obtained.

Next, these are multiplied by a constant from the RAM 21 in the pipe 3 to obtain the total weight χ2 and y2, and are sent to the RAM 13 or the RAM 13 via the vibrator 4 together with χj' and r stored in the latch 9. Accumulates to 14. That is,
By repeating the operation of sequentially latching the Cheetah key in each vibe, then performing the operation, and latching the #j result, addition/subtraction operations, multiplication, and As a result, the overall calculation efficiency is improved.

As is clear from the above explanation, since there are always two types of data to be read from L, AM]3 and 14, the program counters 18 and 19 are used as respective dedicated address sequencers. The other counter 20 used is designed to shorten the data read time by dedicating it only to the glutes. In addition, the two R,
If one of the AMs 13 and 14 is storing data, it is only necessary to read data from the other one, which also contributes to shortening the retrieval time.

It will be understood that the latches 7, 8 and 9 provided at each stage of the butterfly arithmetic processing section 1 are intended to absorb the difference in FiT time required for each vibe.

There is no need to do this, and as shown in Figure 4, it may be even longer, and the number of repeat Kalantara kernels built into the microprogram sequencer 23 should be processed in the butterfly operation. It is also effective to shorten the length.

For example, by taking the above-mentioned Hinakin, 256 points FFT
When using a conventional processing device, the calculation speed of 2.4 ms is reduced to about 0.5 ms.

Furthermore, d-i, as shown. ...Note 21. Total of 4 product-sum calculation circuits
Multiplying circuits 24, 25, 26, and 27 may be multiplied in parallel, and an addition/subtraction calculation circuit 28 may be added at the subsequent stage.

By doing so, it becomes possible to increase the speed of attack even further, and the time can be reduced to about half of the 0.5 ms described above.

Since the butterfly settlement processing apparatus of the present invention is constructed as described above, the FFT calculation time can be reduced to a large extent, and real-time processing is no longer required.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the butterfly settlement method, and a circuit diagram showing an example in which 2mK was used. 2.3... Input/output take bus 4.28... Addition/subtraction calculation circuit 5.6... Addition/subtraction calculation circuit 7.8. and 9... Latch circuit 13.14... Random access memory 18
．． 19 and 20... Program counter:)3
・・・・・・ Micro program sequencer 24
+ 23, 26 and 27...The numbers are arithmetic circuit patent applicant: Toyo Tsushinki Co., Ltd.

Claims (1)

[Claims] - A latch circuit between the bus, the adder circuit, and the plurality of serial circuits? [318 10 crumbs] and the random access memory of 2 (! High-speed Two-Lier Conversion 1 and 1 10 patented for being able to execute search, write, addition, subtraction, and multiplication simultaneously and continuously. (2) Microflodarum sequencer that controls the arithmetic processing unit. By having a plurality of repeat counters in the sequencer, it is possible to reduce the time required for repeated nested calculations to be processed in addition to the butterfly calculation, and also to reduce the time required for the repeated nested calculations that need to be processed by the butterfly calculation.
The fast Fourier transform device according to claim 1, characterized in that the entire capacity of the only memory is saved. (3) Yusuke fake's total sum arithmetic circuit all parallel regrets 4
Is the multiplication of the numbers an arithmetic circuit and an addition/subtraction calculation route to these steps? The fast Fourier conversion device according to claim 1 or 2, characterized in that the self-nose time is further shortened by arranging the fast Fourier conversion device.