JPS58205202A - Fault detector - Google Patents

Abstract

PURPOSE:To prevent a system down when a fault occurs during dual system operation by monitoring changes of state of two signals a specific timer after dissidence between two signals is detected in a dual system control protective device. CONSTITUTION:For example, when a system B is normal and a system A is troubled on the side of an output pulse 1, a dissidence signal generated by dissidence detecting gate 14 is delayed by a specific time through a timer 16 and a one-shot circuit 16 and an AND gate 18 and an OR gate 20 output 1 in accordance with the AND condition with the output pluse 1 of the system A. Once the output pulse of the system B changes from 1 to 0, an FF21 is set and an inverted signal is outputted from an inverter 23 after being delayed by a specific time through a timer 22; and an AND gate 24 outputs a pulse 1 in accordance with the AND condition with the output pulse of the OR gate 20, and the trouble of the system A on the side of the pulse 1 is detected. The trouble of the system A on the side of a pulse 0 is the same.

Description

[Detailed description of the invention] [Night surgery field of the invention] The present invention is directed to a dual-layered helmet protection device, Gurus 101.
The present invention relates to a highly reliable failure detection device that is capable of detecting both a failure on the side of the mother bus 111 and a failure on the side of the mother bus 111, and is capable of determining which control protection device is at fault.

[Technical background of the invention]

FIG. 1 is a block diagram showing an example of a failure detection device in a conventional multiplexed control and protection device.

In Figure 1, 1.2 is duplicated with a control and protection device, and each ? ! +IJlIl] The protection device is equipped with a failure detection device 3.4, and each failure detection device 3.4 detects a discrepancy? - consists of 5.6.

Hereinafter, the system side protective equipment #1.2 will be referred to as A system and B system, respectively.

In such a configuration, the output pulse of system A is now pulse “1”@, and H/4 pulse is 10”11J K therefore N
However, if the output pulse of the B system is normal, the output pulse of the A system is normal, and the output pulse of the B system is on the 4 pulse 111 side, □ or 1,000 pulses"oMm". if you did this,
Both of the discrepancy detection darts 5 and 6 detect discrepancies, and each fault is detected by the fault detection devices 3 and 4.

[Problems with background technology]

However, in the conventional fault detection H4, it cannot be determined whether the detected fault is due to a fault in system A or system B. In such a fault detection device,
If a fault occurs during two-system tally operation, the system in which the fault has occurred cannot be immediately isolated and dealt with in order to continue operation, resulting in a system shutdown.

However, in recent years? 1fIIli [0 With the increasing standardization of protection devices, there has also been a need for highly reliable changes in failure detection devices. Therefore, the above drawbacks can be eliminated and the limited warranty
! Even if the device is operated in two systems, it is possible to determine which system is at fault.
There is a need for a fault detection device that can detect even if there is a tli voice disorder or a fault on the pulse 11@ side.

[Object of the present invention]

Therefore, it is an object of the present invention to eliminate the disadvantages of moe-rou and to satisfy the above-mentioned needs. The purpose of this invention is to provide a new fault detection system that improves reliability in integrated circuits.

[Summary of the invention]

The present invention is characterized in that the object is achieved by detecting a mismatch between two signals and, when the mismatch is detected, monitoring changes in the state of the two signals immediately after the mismatch is detected. .

[Embodiments of the invention]

Figure 2 is a block diagram of a failure detection device showing an embodiment of the present invention. 10.11 is a trench protection device, hereinafter referred to as A system and B system, respectively. 12 and 13 are fault detection Ha for the A system and B system, respectively, and the fault detection device 12 is a mismatch detection f-t1 that detects a fault by detecting mismatch with the t4 pulse of other systems.
4. Timer 16, one-shot circuit 16, inverter J7, which detects a failure by delaying the pulse for a certain period of time and comparing it with the output/4' pulse of each system after a certain period of time;
It is composed of AND gates 1B and 19, a circuit 25 (hereinafter referred to as the A1il path) that has a function of locking a failure in another system, an AND gate 24 that is satisfied by the AND condition of the OR gate 2o, and the A[qJ path. For example, the circuit is nest 2
As shown in the figure, the fritz defrotz f21, timer 22,
It is composed of an inverter 23.

Here, the timer 15 has a function of outputting a pulse after delaying the output pulse of the flip-flop 2) by a time T8, which is longer than the normal output of the image stabilization device 1. When changing from 111 to 101, the output pulse changes from 111 to 101 at the same time as the change, and the output pulse of the flip-flop 21 changes to 101.
When changing from ``I'V!-'', the output pulse has the function of changing from 101 to 11@ with a delay of time T.6 Time T1 and time T have a relationship of T:>T.

Next, the operation of the present invention will be explained.

＠2 series of swords consisting of A series and B series as shown in Figure 2
In the failure detection device 12 of the arsenic protection device, the function of detecting a mismatch between the output signals of the A system and the B system by the mismatch detection gate 14 is hereinafter referred to as the first means. -15. The function of generating an output after a predetermined time via the one-shot circuit I6 is as follows:
The output signal of the second means and the input signal from the specified A system are AND-dated 18, or the output signal of the second means and the input signal from the B system are combined via the inverter 17. The function of detecting a failure in the A system at the AND gate 19 based on the AND condition with the inverted signal is hereinafter referred to as third means. Similarly, the failure detection device 13
@1 means for detecting a mismatch between the signals of the system and the B system; a second means for generating an output after a predetermined time after the output signal of the first means is generated; It has third means for detecting a failure in the B system based on the input signal from the A system and the input signal from the B system.

Now, if the B system is normal and the A system fails to the output pulse 11@ side, the discrepancy is detected by the discrepancy detection gate 14 by the first means, and the timer is activated by the second means. 15. One shot (b) The output is delayed for a certain period in path 16, and the output i4 of the A system is output by the third means.
Under the AND condition with Ruth 111, the output of And Dart 18 is 11', so the output of Or Date 20 is @
It becomes 1. On the other hand, the output/Grus of the B system is "11 to 10
When the signal changes to ', the flip-flop 21 is set and the timer 22 outputs the signal after the time T. The output pulse of the timer 22 is inverted by the inverter 23, and according to the AND condition with the output of the OR gate 20/4 pulses, a pulse 111 is output to the AND gate 24, and A
The failure of the system pulse °1 ° II] i1 is detected by the failure detection device 12.
It can be detected by

In addition, if the B system is normal and the A system deviates to the output pulse "0" side, the mismatch is detected by the mismatch detection gate 14 by the first means, and the mismatch is detected by the first means. The output is delayed for a certain period of time by the timer 15 and the one-shot circuit 16, and the output pulse of the B system is ANDed with the pulse inverted via the inverter 17, and the AND gate 19
Since the output curve of the signal is 111, the output of the OR gate 20 is 111. - 10,000, B-type cuckolds are 11
When the value changes from 1 to 101, the flip-flop 21 is set and output via the timer 22 at time Tt<&. The output pulse of the timer 22 is transferred to the inverter 23.
A? The pulse 111 is output, and the failure detection device 12 detects a failure on the pulse Mol side of the A system.

zrc, A system is normal and B system is output/4 rusl 1111
．． 1, as shown in Figure 3, the mismatch is detected by the mismatch detection gate 14 by the first means, and the second means (from the timer 15 and the one-shot circuit 16 delay the output for a certain period of time, By means of step 3, the AND condition with the output pulse of system A and the output/4 pulses of system B are applied to inverter 1.
Under the AND condition with the pulse inverted through 7, the output pulse of AND gate 18.19 remains 101, so the output of OR date 20 becomes 101, and AND gate 24
The output pulse is IQI, and the B system pulse '1' 1flU
This failure is not detected by the failure detection device 12.

Also, because the A system is the correct one and the B system is on the output pulse Mol side,
4, the output pulse of the inverter 17 remains 111 as shown in Figure 3 (■), so the output pulse of the inverter 23) remains 101, and the output pulse of the AND e -) 24 is 101, which is the pulse of the B system. The failure of I01x1j is not detected by the failure detection device 12.

FIG. 3 shows a time chart for each of the above cases. Similarly, only B-type rhinoceroses are detected in the rhinoceros excavator 13.

Next, other embodiments of the present invention will be described.

In Figure 4, the arrangement of the flip-flop 21, timer 22, and inverter 23 of the circuit shown in Figure 2 is changed. The circuit has the function of locking the functions of other systems.
! As long as it is a circuit and has the function, the type and arrangement of the cape component are not limited. Therefore, in addition to the circuit A in FIG. 4, which has the same function as the circuit A in FIG.

Furthermore, Figure 5 shows AL! of Figure 2! The output of the circuit is an-f
-) Entered in 19. In the failure detection device having the configuration shown in FIG. 5, the AND gate 24 in FIG. 2 is unnecessary, and failures are detected by the output of the ORDATE 20. The function as a failure detection device is the same as that shown in FIG. 2, and it detects only the failure of the pulse 1s9i1 of the system A. In FIG. 82, the failure detection device A system.

Although the B system and the failure detection device are configured independently, it is possible to incorporate the failure detection device into the device to be detected, and the mismatch detection circuit 14, timer 15, and one-shot circuit 16 may be used in common. You can also do it. That is, the first means of the fault detection device 120 and therefore the first means of the detection arrangement 13 and the second means of the fault detection device 12.13 can each be shared.

〔Effect of the invention〕

As explained above, according to the present invention, in the control protection device that is frequently damaged, each system of the control protection device is equipped with a failure detection device, and the write failure detection HrtL is detected by the output of each system. A? The output pulse of the other system is different from the output pulse of -4m, and the mother pulse "O"ii! j.

The circuit A, which has the function of detecting a failure on the ``11 side'' and locking failures in other systems, is redone, and the circuit A, which has the function of detecting a failure on the ``11'' side of the pulse 10'' side of the separate protection device, and By detecting only failures in the system, even if a system with multiplexed control and protection devices is stopped and two systems are operating, the failed system can be quickly disconnected and disposed of. It has the remarkable effect that it continues to operate in one line and does not cause the system to stop.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional multiplexed fault detection device with four control systems, and Fig. 2 shows an embodiment of the present invention. l
! 3 are time charts for explaining the operation of the pigeon 2, and FIGS. 4 and 5 are configuration diagrams showing other different embodiments of the present invention. 1.2, 3.11...Control protection device, 4.5゜6.1
2.13...Failure detection device, 7.84-4...Failure
Scatter detection date, 9.1B, 19.24...Andr-
15, 2:2...Timer, 16...One-shot circuit, 17.23...Inverter, 20...Orff-to, 21...Flip-flop, 25...
A circuit (artificial circuit) that has the function of locking out failures in other systems. Patent attorney Suzue Takehiko□

Claims (1)

[Scope of Claims] ・1) In a failure detection device that detects a failure in a duplicated control and protection device, the signals of each system of the duplicated control and protection device are −1 to detect a mismatch between the signals. A first means for detecting the output signal of the means of Part 1, a second means that generates the output signal after a fixed time, and an output signal of this second means and an input signal of the two systems. A failure detection device characterized in that each system is equipped with @3 means for detecting a failure in the system (2> The first means and the means @2 are 2'!1). 2. The failure detection device according to claim 1, wherein the failure detection device is shared by the system.