JPS58203553A - Method for discriminating allowable storage data in data area - Google Patents

Method for discriminating allowable storage data in data area

Info

Publication number
JPS58203553A
JPS58203553A JP5277282A JP5277282A JPS58203553A JP S58203553 A JPS58203553 A JP S58203553A JP 5277282 A JP5277282 A JP 5277282A JP 5277282 A JP5277282 A JP 5277282A JP S58203553 A JPS58203553 A JP S58203553A
Authority
JP
Japan
Prior art keywords
register
input data
data
bits
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5277282A
Other languages
Japanese (ja)
Inventor
Megumi Suyama
巣山 めぐみ
Etsuko Negishi
根岸 悦子
Eiichi Aoki
栄一 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5277282A priority Critical patent/JPS58203553A/en
Publication of JPS58203553A publication Critical patent/JPS58203553A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To check simply the tolerance of a storage area, by inputting an input data value to a shift register, shifting the value to the lower-order and discriminating whether storing is available or not by the existence of ''1'' in the register after shifting the value. CONSTITUTION:Data inputted to a register 1 are transferred to a shift register 2 and a register 5. A setting part 4 connected to the register 2 sets up the number (n) of bits in a data area register 7, shifts the contents of the register 2 by n bits in the lower-order bit direction and turns the empty bits in the upper-order bits which are generated in accordance with the shifting operation to ''0''. A discrimination circuit part 3 discriminates whether the register 2 includes ''1'' after shifting or not, and when there is no ''1'', opens a gate circuit 6 and stores the input data value stored in the register 5 into the register 7. When the circuit part 3 discriminates the existence of ''1'' once at least, the input data value is returned to the input data side regarding that the storage of the value in the register 7 is impossible.

Description

【発明の詳細な説明】 (a)  発明の技術分野 この発明は、入力されるデータ数値が所要のビット構成
のデータ領域に収納されるやを判定するデータ領域の許
容収納データ判定方法に関するものである。
Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a method for determining allowable storage data in a data area, which determines whether an input data value is stored in a data area with a required bit configuration. be.

(至)従来技術と問題点 従来数値で入力される入力データがビット構成からなる
データ領域に入力されつるや否やを判定する場合ビット
に対する数値を表に表わした表を用いて数値をビット数
、或はビット数を数値に変viの演算を行ひ演算結果と
入力数uLtl−比較してデータ領域に対する入力デー
タ即ち数字の入力可否を判定する方法を用いてい友。曲
者は表を作成し内蔵せねばならず従って内蔵用のメモリ
も必要であ)、後者は演算を行わねばならず何れにして
もこれら処理は単純でないといった問題があつ念。
(To) Prior art and problems Conventionally, when input data input as numerical values is input into a data area consisting of bits, a table showing numerical values for bits is used to convert the numerical value into the number of bits or A method is used in which the number of bits is converted into a numerical value, the operation vi is performed, and the result of the operation is compared with the input number uLtl to determine whether input data, that is, a number, can be input to the data area. The composer has to create and store tables (therefore also requires built-in memory), and the latter has to perform calculations, so in any case, there is a problem that these processes are not simple.

(C)  発明の目的 この発明は、以−トのような従来の状況から格納領域の
許容チェックが簡単に行えるデータ領域の許容収納デー
タ判定方法を提供することを目的とするものである。。
(C) Object of the Invention It is an object of the present invention to provide a method for determining the permissible data stored in a data area, which can easily check the permissibility of the storage area from the conventional situation as described below. .

1) 発明の構成 簡単に述べるとこの発明は、入カテ°−夕数iiiiシ
フトレジスタに人力し、データ領域を構成するビット数
、オ覇しジスタ内の数ijIを下位方向にシフトきしめ
、空ビットを10′とし、シフト後のレジスタの内容内
のゞビの有無により収納可否を判定することを特徴とす
るものである。
1) Structure of the Invention Briefly stated, this invention manually inputs the number of bits constituting the data area into the input category iii shift register, shifts the number ijI in the register in the lower direction, and sets the number of bits constituting the data area in the lower direction. It is characterized in that the bit is set to 10', and whether or not it can be stored is determined based on the presence or absence of ``2'' in the contents of the register after shifting.

(e)  発明の実施例 図はこの発明を適用したデータ領域の許容収納データ判
定方法の一実施例を示すブロック図であって、■と6t
iレジスタ、2はシフトレジスタ、3は判定回路部、4
は設定部、6はデー1回路部、7はデータ領域レジスタ
をそれぞれ示す。入力されるデータ数値はレジスタlに
入力される。図における右側が下位、左側が上位ビラト
ラ示す。レジスタ1に格納された入力デ−タ数値がT1
ビット構成からなるデータ領域レジスタ7に格納し得る
かを判定する場合に、レジスタlの内容t−シフトレジ
スタ2とレジスタ5に転送する。シフトレジスタ2には
設定部4が付設されており、この設定部4はデータ領域
レジスタ7のビット数nが設定され、設定都令はこの設
定値nビワ1分シフトレジスタ2の内容を下位ビット方
向に7フトさせる動作を行うとともに、シフトに応じて
生じるシフトレジスタ2の上位ビットの空ビットをlO
′と−rる動作を行う。判定回路部3はシフトされた後
のシフ)レジスタ2の中に11が存在するや否やを判定
し、1ビが無ければその旨をゲート回路6に連絡しゲー
ト回路部6を1通′となしてレジスタbに格納された入
力データ数値をデータ領域レジスタ7に格納する。判定
回路部8が少くとも1個の11の存在を判定すると入力
データ数値はデーリー 一タ領植レジスタ7には格納不可能であると入力データ
側に送り戻す。
(e) Embodiment of the Invention The figure is a block diagram showing an embodiment of a method for determining permissible storage data in a data area to which the present invention is applied.
i register, 2 is a shift register, 3 is a judgment circuit section, 4
6 indicates a setting section, 6 indicates a data 1 circuit section, and 7 indicates a data area register. The input data value is input into register l. The right side of the figure shows the lower rank, and the left side shows the higher rank. The input data value stored in register 1 is T1
When determining whether data can be stored in the data area register 7 consisting of a bit configuration, the contents of the register l are transferred to the t-shift register 2 and the register 5. A setting section 4 is attached to the shift register 2, and this setting section 4 is set with the number of bits n of the data area register 7, and the setting ordinance is used to convert the contents of the shift register 2 into lower bits. At the same time, the empty bit of the upper bit of shift register 2 that occurs in response to the shift is moved to lO
' and -r operation. The determination circuit unit 3 determines whether or not 11 exists in the shift register 2 after being shifted, and if there is no 1 bit, it notifies the gate circuit 6 to that effect and sends the gate circuit unit 6 a 1' message. Then, the input data value stored in register b is stored in data area register 7. When the determination circuit section 8 determines the presence of at least one 11, it sends back to the input data side, indicating that the input data value cannot be stored in the Daly data entry register 7.

(1つ 発明の効果 ト述のごときこの発明によれば表とか演算とかを行わず
に格納領域に許容される入力データの判定が簡単に行え
、入力データを処理する上で利点の大きいものとなる。
(1. Effects of the Invention) According to this invention, it is possible to easily determine the input data that is allowed in the storage area without using tables or calculations, which is a great advantage in processing input data. Become.

【図面の簡単な説明】[Brief explanation of the drawing]

図はこの発明1に適用したデータ領域の許容収納データ
判定方法の一実施例を示すブロック図である。 図において、lと5はレジスタ、2はシフトレジスタ、
8は判定回路部、7はデータ領域レジメタをそれぞれ示
す。 へカテゝり
The figure is a block diagram showing an embodiment of a method for determining permissible storage data in a data area applied to the first invention. In the figure, l and 5 are registers, 2 is a shift register,
Reference numeral 8 indicates a determination circuit section, and reference numeral 7 indicates a data area register. Hecate

Claims (1)

【特許請求の範囲】[Claims] 設定されたnビット構成からなるデータ領域に入力デー
タ数値が入力される際に該データ領域に前記人力データ
数値が収納される許容可否を判定する方法であって、該
入力データ数値をシフトレジスタに入力L l1il 
記nビット分ビット下位方向にシフトするとともに該シ
フトによる空きビットを10′とし、前記ジフト後の前
記シフトレジスタ内の11の有無を判定して当該入力デ
ータの収納可否を判定するようにしたことを特徴とする
データ領域の許容収納データ判定方法。
A method for determining whether or not the input data value is allowed to be stored in the data area when the input data value is input into a data area having a set n-bit configuration, the method comprising: inputting the input data value into a shift register. Input L l1il
The input data is shifted in the lower bit direction by n bits, and the vacant bit resulting from the shift is set to 10', and the presence or absence of 11 in the shift register after the shift is determined to determine whether or not the input data can be stored. A method for determining permissible storage data in a data area, characterized by:
JP5277282A 1982-03-30 1982-03-30 Method for discriminating allowable storage data in data area Pending JPS58203553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5277282A JPS58203553A (en) 1982-03-30 1982-03-30 Method for discriminating allowable storage data in data area

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5277282A JPS58203553A (en) 1982-03-30 1982-03-30 Method for discriminating allowable storage data in data area

Publications (1)

Publication Number Publication Date
JPS58203553A true JPS58203553A (en) 1983-11-28

Family

ID=12924153

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5277282A Pending JPS58203553A (en) 1982-03-30 1982-03-30 Method for discriminating allowable storage data in data area

Country Status (1)

Country Link
JP (1) JPS58203553A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991146A (en) * 1972-12-29 1974-08-30
JPS51129134A (en) * 1975-05-02 1976-11-10 Toshiba Corp Overflow detector device for the memory registers of electronic calcul tors

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991146A (en) * 1972-12-29 1974-08-30
JPS51129134A (en) * 1975-05-02 1976-11-10 Toshiba Corp Overflow detector device for the memory registers of electronic calcul tors

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