JPS58201123A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To speed up the operation of a semiconductor integrated circuit by incorporating a circuit which generates a reference clock of double frequency on the basis of an external clock input in the integrated circuit. CONSTITUTION:The clock 10 is divided into two; one is differentiated directly by a differentiating circuit 11, whose output (a) is inputted to an NOR circuit 16 after waveform shaping 14. The other one is inverted in phase by an inverter 12, and then inputted to the NOR circuit after differentiation 13 and waveform shaping 15. The output of the NOR circuit 16 is inverted by an inverter 17 into the reference clock to be outputted. Thus, the clock of frequency twice as high as that of the clock input is generated to increase the limited frequency of the input clock equivalently, speeding up the circuit operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit incorporating, for example, a microcomputer circuit.

[Technical background of the invention]

Conventionally, in semiconductor integrated circuits for microcomputer circuits, the maximum frequency of the clock signals used inside the integrated circuit is prepared as a reference clock signal outside the integrated circuit, and this is input into the integrated circuit and used as needed. Accordingly, the input clock frequency is divided and used within the integrated circuit.

[Problems with background technology]

However, when increasing the frequency of the reference clock in order to speed up the operation of an integrated circuit, it is difficult to increase the input clock of the integrated circuit to four times higher than the required reference frequency as in the past due to the technical limitations of the input clock oscillator circuit. There were limitations due to its characteristics.

In other words, the limit frequency of the input clock limits the speed of integrated circuit operation.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to increase the speed of integrated circuit operation by using a reference clock with a higher frequency than that of the input clock, and to extend the limit frequency of the input clock with equal constraints. The present invention provides semiconductor integrated circuits.

[Summary of the invention]

That is, the semiconductor integrated circuit of the present invention has internally formed a reference clock generation circuit that generates a reference clock by doubling the frequency of an input clock. Therefore, the reference clock frequency is higher than the input clock frequency, making it possible to increase the speed of integrated circuit operation.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. Figure 1 shows a reference clock generation circuit formed inside a single-channel type (for example, N-channel type) MOS-LSI (insulated dart type transistor large-scale integrated circuit). In other words, 10 is an input terminal to which an input clock signal supplied from outside the integrated circuit through an input pin is guided. This input terminal 10 is connected to a first differentiating circuit 1 and also to a second differentiating circuit 13 via an inverter circuit 12 .

These differentiating circuits 11.13 consist of a capacitor C, a diode D, and a resistor R using, for example, a depletion type transistor.

14 and 15 are waveform shaping circuits for shaping the outputs of the differentiating circuits 11 and 13, each of which is made up of nine, for example, two inverter circuits connected in series. Each output of the waveform shaping circuits 14 and 15 is led to a two-man NOR circuit 16, and the output of this NOR circuit 16 is inverted by an inverter circuit 17 to become a reference clock output.

Next, the operation shown in FIG. 1 will be explained with reference to FIG. In the initial state, the input clock is at the 0” logic level (OIy
), the voltages at the output terminals a and b of the differentiating circuit 1113 are both at the '0# level. Then the input clock is “
When the voltage shifts from 0- to 1#1# (level D power supply potential), the output terminal a of the first differentiating circuit 11 is pulled up to the 1# level by the capacitor C, and this capacitor C
The capacitor C is charged with voltage by the time constant of the resistor R, and the output terminal a shifts to the 0'' level.On the other hand, in the second differentiating circuit 13, the voltage of the inverter circuit 12 in the initial state is Since the capacitor CKt pressure is charged by the l# output, the change in the output of the inverter circuit 12 due to the change in the input voltage ('0''→''1') K ('1''→''01) causes The voltage at the output terminal S attempts to shift to the -vDD potential, but is pulled back to the 0'' level by the diode D in a short time. Next, when the input clock changes from “1#” to “01”,
In accordance with the above-mentioned operation, the output terminal a of the first differentiating circuit 11 attempts to shift to the -VDD potential, but is pulled back to the "0" level in a short time, and the output terminal of the second differentiating circuit 13 becomes vDD.
After shifting to the potential, the time constant of the capacitor C and the resistor R causes the voltage to shift to ``0 level'' and progress to 5-.

Differential outputs a, b of the differentiating circuits 11 and 13 as described above, waveform shaping circuits 14 e 15, and XpApy waveforms e, d
After being shaped into a clock, it passes through a NOR circuit 16 to become a clock with twice the frequency of the input clock, and then passes through an inverter circuit 17 to become a reference clock output and then to other circuits (not shown) inside the integrated circuit. Supplied.

By setting the capacitor C and resistor R of the differentiating circuits 11 and 13 to appropriate values, the differential output a of the ideal linear analog waveform can be obtained.

The duty of the output clock of the NOR circuit 16 can be set to 50% by generating the clock signal b and shaping it into a signal with a coherency of 25q6 by setting the threshold voltage of the logic circuit at the subsequent stage.

Note that the present invention is not limited to the above-mentioned embodiment, and for example, the waveform shaping circuits 14 and 15 are each made into one inverter circuit, and the NOR circuit 16 and the inverter circuit 11 are made into one inverter circuit.
Even if a two-man NAND circuit is used instead, it is possible to generate a standard clock output similar to the above example.

〔Effect of the invention〕

As described above, the semiconductor integrated circuit of the present invention has a built-in reference clock generation circuit that generates a reference clock by doubling the frequency of the input clock. It is also possible to use a reference clock with twice the frequency of the reference clock, and the limit frequency of the input clock can be expanded isometrically. Therefore, if the present invention is applied to, for example, an integrated circuit for a microcomputer, the speed of circuit operation can be increased, which is preferable.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a reference clock generation circuit in a semiconductor integrated circuit according to the present invention, and FIG. 2 is a timing diagram shown for explaining the operation of FIG. 1. 11.13... Differential circuit, 14*15... Waveform shaping circuit, 16... NOR circuit. Applicant's agent Patent attorney Takehiko Suzue 7- Figure 1 11 Satoku 0-/7

Claims (3)

[Claims] (1) A semiconductor integrated circuit comprising a built-in reference clock generation circuit that generates a reference clock having twice the frequency of an external clock input. (2) The reference clock generation circuit includes two differentiating circuits that respectively differentiate the clock input signal and a clock signal obtained by inverting the clock input signal, and a waveform shaping circuit that shapes the outputs of the respective differentiating circuits. 2. The semiconductor integrated circuit according to claim 1, comprising: a circuit; and a logic circuit for calculating the logical sum of the respective outputs of these waveform shaping circuits. (3) The semiconductor integrated circuit according to claim 1, characterized in that it is formed as a single channel type MOS-LSI and incorporates an n1 microcomputer circuit.