JPS5820066B2 - Hardware virtualizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical field to which the invention pertains The present invention generally relates to a computer system, and specifically relates to virtual resources simulated on a general-purpose host computer and virtual resources executed on the host computer. The present invention relates to a method and a hardware virtualization device (partualizer) for establishing correspondence with a real process.

(B) Description of the Prior Art The advent of input/output ('10) processing units in the early 1960s and the use of multiprogram methods to improve resource utilization and overall processing efficiency made main memory This encouraged the development of multiprocessor and multiprogram processing systems in which dissimilar processing units are shared and a single processing unit is shared by several processes competing for a common resource.

A two-state architecture was adopted to slow system integrity issues.

Basically, system operation can be broadly divided into two modes: privileged mode and non-privileged mode.

Special: Unprivileged operating mode (also called master/slave operating mode, system/user operating mode).

), the execution of critical operations is limited to privileged mode, and most non-critical operations are performed in non-privileged mode.

(B-1) Ordinary two-state system and its problems Figure 1a shows a part of an ordinary two-state system.

A bare (undecorated, sober) machine 101 (indicated as "base machine" in the drawing) is a %-rights software core 102
It has a base (basic) machine interface 103 that supports (can handle).

This base machine interface is a software-visible interface directly supported by a particular system's hardware and firmware.
le) means a group of objects and instructions.

This bare machine 101, privileged software core 102, and base machine interface 103 are combined into several extended machines (extended machines) 1
04, 105, etc. (only two are shown in FIG. 1a for simplicity).

This expansion machine 106 and 101 may support several user programs as shown.

However, since conventional systems of this type have only one base machine interface 103, there is only one privileged software core 103 at any given time.
Only 02 can be executed.

Therefore, since the privileged software core is the only software that can completely access the hardware and control all functions and capabilities of the hardware, several problems arise.

An important problem is that the program is actually created for an extended machine consisting of an unprivileged program or a privileged software core and unprivileged functions of the hardware.
It exists in the field of transportability (program portability).

While bare hardware machines (machines with bare hardware) can be standardized relatively easily, extended machines require that the system's primitives (original functions or directives) are partially embodied in software. Therefore, since it is relatively easy to change or modify a system that includes a privileged software core, standardization is extremely difficult.

Therefore, there are a wide variety of extended machines (systems) that can be executed on a standard bare machine.

Therefore, a user who wants to run a program written for one extended machine that is disparate from the user's extended machine must either abandon his own extended machine to run a "foreign" software kernel, or run a program on a dissimilar extended machine. It is necessary to modify the program written for the user's own expansion machine.

This option is not preferred by most users.

Another problem arises from the fact that since only one privileged software kernel is provided, it is not possible to have two privileged software kernels running at the same time.

Continuously evolving, changing and modifying the software kernel is therefore very difficult to implement since it requires system programmers to have the associated machines at their disposal for very long periods of time.

Furthermore, when system programmers freely use related systems for debugging (examination of calculation execution) or changes/modifications, the utilization efficiency is extremely low and resources are
The efficiency of use of will be extremely poor.

Finally, tests can be performed without interfering with the normal computational planning, since the diagnostic software must access and control all functions and capabilities of the hardware and therefore cannot run concurrently with the privileged software core.・The amount of diagnostic processing is limited.

(B-2) Description of a virtual machine In order to eliminate such problems, it is necessary to create a virtual machine (which can support several similar base machine interfaces 124 (FIG. 1b) instead of an extended machine interface). It is necessary to create a virtual) machine monitor VMM 122 (Figure 1b).

In this way, different privileged software kernels, ie operating systems 112, 113 (FIG. 1b), could be executed on each additional base machine interface 124 and the problems described above would be eliminated.

Although not directly supported on bare machines, extended machines
The base machine interfaces supported in the same way as the interfaces are called virtual machines and are numbered rllo, 1 in Figure 1b.
It is indicated by 11J.

Figure 1b shows the same bare machine 101 as in Figure 1a.
is shown, but the base machine ink face 10
Privileged software running in 3 is a virtual
A machine monitor (VMM) 122.

The virtual machine monitor 122 supports several base machine interfaces 124 in this illustration.

Therefore, different privileged software kernels 112, 113
is executable at each additional base machine interface 124.

Each privileged software kernel 112-113 may support its own set of extended machine interfaces 125 and 126 and therefore its own user programs 118-119 or 120,121.

The base machine interface supported by the Virtual Machine Monitor (VMM) is
l) Functionally identical to the machine's base machine interface, any privileged software kernel that can run on the base machine will be able to run on the virtual machine as well.

Furthermore, a privileged software kernel has no means of determining whether it is running on a bare machine or a virtual machine.

Fundamentally, therefore, a virtual machine is equivalent to its actual replica, with no discernible functional differences.

Virtual Machine Monitors (VMMs) do not interpret and execute these programs instruction by instruction, but allow the programs to run directly on a bare machine most of the time.

However, sometimes the Virtual Machine Monitor (V
MM) traps certain instructions and executes them interpretively to ensure the overall integrity of the system's contents; after this interpretive execution is finished, control is transferred to the returned to the program.

Executing a program in a virtual machine is therefore very similar to executing a program in an extended machine, with most instructions being executed directly without software intervention, and control to perform the necessary interpretive operations. Interventions are sometimes performed by software for

As can be seen, the virtual machine monitor (VMM) 122 of FIG. 1b is run directly on the bare machine.

This type of system is called an rIJ virtual machine.

However, there may also be virtual machine monitors running on extended machines.

This second type of virtual machine is shown schematically in FIG. 1C and is referred to as an rllJ type virtual machine.

In FIG. 1c, a bare machine 101 is shown comprising a base machine interface 103 with a privileged software kernel 151. In FIG.

Privileged software core 151 is connected to expansion machine 15 having expansion machine interfaces 157a and 157b, respectively.
It supports 3,154.

The extension machine 153 supports the user program 155, the other extension machine 154 supports the virtual machine 158, and the other virtual machine 158 can support the extension machine 161. may support user programs 162.

(B-3) Specific examples of virtual machines Here, a relatively small number of virtual machines in the conventional technology will be described.

The following things are intangible.

(b) I 8M44=r I J type FV (family parturizing, family virtual computer) I 8M44 (Highly modified and modified second generation IB
M7044) is problem/supervision/operation mode/location.

It has been expanded to include multiple operating modes such as John/Non-location testing, mapping/non-mapping operating modes, and paging functionality.

An operating system called MOS (Module Operating System).

The use of stems creates a family of virtual machines called "44X."

However, since they are slightly different from the actual r7044J, these r44XJs are not virtual machines in the strict sense.

The r44XJ operating system runs on each r44XJ and is capable of conventional services found in many operating systems.

(0) IBM Cambridge Science Center CP-40="
I” type Fv (cognate partializing, cognate virtual computer CP-40 (control program-40) is CP
-67, and was created in response to the IBM 360/40, which was specifically modified and modified with the addition of an associative memory paging box.

This system is a time sharing system and supports 14 virtual machines "360".

These r360Js are standard rIBM360Js and do not include any special changes or modifications to the host machine 40.

Virtual machine 360 can run multiple r360J operating systems.

These operating systems have a standard O8/3
60 and CMS (a "conversation system" developed at the Cambridge Science Center specifically for use with the CP-40 (Cambridge Monitor System)).

This system suffered from the combined limitations of 360/40 processor speed, moderate actual core capacity, and slow disk speed for paging functions.

However, the CP-40 helped demonstrate the viability of the virtual machine concept.

Furthermore, it provided VMTSS (Virtual Machine Time Sharing System) and used CMS (Cambridge Monitor System) when no general-purpose time sharing system for its family of machines was available at the time. We have provided a convenient conversation system for the R360J.

In fact, the success of this attempt led directly to the later system rCP-67J.

) IBM Cambridge Science Center CP-67=rlJ
Type FV (family parturizing, family virtual computer) CP-67 (control program-67) is 19
It was developed as an experimental system in January 1967 in collaboration with MIT Lincoln Laboratory.

Initially, CP-40 was slightly modified to support the heterogeneous memory relocation system in the 360/67.

Subsequently, the entire CP-67 system was rewritten.

CP-67 is a VMTSS (Virtual Machine Time Sharing System) that can operate at 360/67.
It supports as many as 30-40 users.

Currently this is the most widely known virtual machine system.

Virtual system 36 based on CP-67
0 has been extremely successful in running many different r360J operating systems.

This system includes (but is not limited to) (various formats 0 system), LLMPS.

Virtual machines are already used in telecommunications applications.

The University of Grenople connects a real machine R 360/40J to a virtual system I 8M360 and uses IBM
The O8/ASP (O8 for Added Support Processing Equipment) system was operated.

A fundamental limitation of virtual machines created with the CP-67 is that a small number of programs do not work properly.

Programs that do not work correctly include (1) programs that depend on accurate execution time, (2) programs that depend on the relationship between processing time and input/output time, (3) programs that depend on accurate real-time (actual time), (4) A program including a self-modifying channel program.

The first two limitations are the same limitations that arise when creating compatibility between two different processing units in the IBM 360 family of machines.

) "Extended CP-67" to support Virtual System 360/67
dberg) is Virtual System 360/67 (
Equipped with virtual relocation.

) have designed slight enhancements to CP-67 to support a relatively efficient software implementation.

With minor changes and modifications, this design, Virtual System 360/67, was implemented by F. Furtek in the fall of 1969.

Independently of this work, Ny Aurass (A., Aur.
ox) was developed at IBM Cambridge Science Center in C
"Virtual System 360/67" for P-67
We designed an "expanded type".

Both designs were very similar, and the one created by Aurax became part of the standard (IBM-sold) CP-67 system.

Virtual System 360/67 was limited to "24-bit address mode single processor machines."

With this performance, various 360/67 operating systems (including CP-67 and TSS/360) were put into service.

That is, CP-67 was put into service by itself.

In fact, this series was tested over at least four stages.

Another fundamental limitation regarding the operation of Virtual System 360/67 in standard Virtual System 360 (in CP-67 F) is that the segment
nt) or programs that dynamically change the contents of page tables will not execute as intended.

Therefore, the results may or may not be the same as the actual 360/67 results.

In a real machine, the contents of the associative registers affect the results and the results can be unpredictable.

(e) Virtual system 36 by UMMPS (University of Michigan Multiprogramming System) o==
r n J-type F (homogeneous virtualizing, homogeneous virtual computer) Virtual system 360 by UMMPS is r n
It is a J-shaped virtual machine system.

UMMPS is a common multiprogramming system created at the University of Michigan to run on dual processors 360/67.

British Columbia University has slightly changed and modified UMMPS to support Virtual System 360.

This change/modification was made in the form of several additional supervisor invocation functions to perform several important operations when dispatching a virtual machine.

When an apparent exceptional condition occurs in the virtual machine, the condition is returned by the UMMPS supervisor to the user program (which may be simulating a privileged instruction, for example).

) virtual system 360 and this virtual system 360/67 are supported by this system, but in addition to the virtual machine interface, other user interfaces (for example, MTS "Michigan Technical System", ordinary Batch system) can also be set up.

(to) Japan Electrical Technology Research Institute HI TAC-8400 = “
``Type F'' (Homologous Parturizing, Homologue Virtual Computer) HITAC-8400 is an RCA Spectra 70/45 made in Japan.

Like the IBM System/360, this is a regular third generation computer without a memory mapping system.

The new time sharing system (rllJ virtual machine) for the HITAC-8400 as an aid to debugging the ETSS (Experimental Time Sharing System) is compatible with the existing commercial operating system rTO8/TDO8J (tape operating system).・System/Tape Disk Operating・
system).

This virtual machine system is very similar to Virtual System 360, which is based on UMMPS (University of Michigan Multiprogramming System).

One interesting concept is the attempt to simulate various virtual Ilo (input/output) devices that do not have precise physical equivalents (eg, display scopes).

Of course, the virtual machine was only used to debug the supervisor code for the ETSS (Experimental Time Sharing System) and did not perform any productive work, so that purpose was achieved.

(g) IBM360/3 with hardware changed/modified
0 = rlJ type FV (family parturizing, family virtual machine) Virtual machine system is experimental system 360
/30 through a combination of software and special hardware or microprogramming changes and modifications.

This change/modification, made to simplify the configuration of the virtual machine, embodies a special "monitor" mode and relocates the interrupt control area from the normal control program area on physical page "0". used for

This system is not a "VMTS Virtual Machine Time Sharing System" and only supports one virtual machine.

Furthermore, this system is not a self-virtual computer (system), but a virtual machine equivalent to this modified 36Q/30.
Do not support the machine.

This basic use is based on the operating system/3
60 (O8/360), Basic, Disk and Tape Operating System (BO8, DO8,
The aim is to monitor and evaluate the performance of existing operating systems such as TO8/360).

(Power MIT Project MACPDP-10ITS
(Incompatible Time Sharing System) -rn
J-type SVHVM (Self-Virtual Hybrid Virtual Machine) DECPD using ordinary 3rd generation software technology
It is impossible to implement a virtual machine in P-10.

Recently, R.P.Goldbelve (R, P, G
oldberg) and Niss double knee flounder (S
,W.

Ga1ley) is a hybrid virtual
Introduced the concept of machines.

With this technique, all execution mode instructions are interpreted and executed, and all user mode instructions are executed directly.

MIT Project MAC Dynamic Modeling - Compute
erGrcphics) PDP-10 provided an ideal environment for this implementation.

The ITS (Incompatibility Time Sharing System) provides the necessary form to support the R31 type (Extended Machine Host) VC8 (Virtual Computer System).

Furthermore, the hardware configuration is enhanced with sufficient cores (storage areas) and sometimes sufficient CPU (central processing unit) operation cycles to enable running an HVM (hybrid virtual machine).

IBM VM/370 In August 1972, IBM announced a virtual machine mechanism for various models of the System/370.

This system uses common software techniques to create a direct "child" of CP-67 that supports a virtual machine.
It is.

VM/370 (Virtual Machine/370) was the first practical virtual machine officially sold commercially by a vendor.
It is a machine system.

(B-4) Problems with conventional virtual machines In the very early days of virtual machines, a virtual machine monitor (VMM) controlled the state of the virtual machine's processing unit, main memory, and l10 (input/output) operations. It had characteristics.

Simply put, the early VMM (virtual machine)
Since the monitor ran all programs in unprivileged mode, the privileged software nucleus running in the virtual machine
s) cannot enter any privileged mode and cannot have unrestricted access to the entire system, so V
It could have interference with the MM itself or with other virtual machines in the system.

Additionally, these early VMMs typically performed "pine-pink mapping" of main memory through "paging techniques" and always performed all I10 (input/output) operations interpretively.

To this end, these early virtual machines had the ability to trap all instructions that could change or interrupt processor state or initiate an I10 operation, and a type of reconfiguration (memory location). ) could only be realized in a computer system equipped with this function.

For example, CP-67 (control program-67)
Some early VMMs, such as the
The machine could not be operated.

This “recursive capacity”
1ity) Due to the lack of J, testing and development of VMM must be done on the processing device used.

To overcome this difficulty and satisfy a higher degree of logical completeness, CP-67 was modified so that it could be operated recursively.
Modified.

This required effectively performing a "double mapping operation" to handle the additional "paging" operations performed on the VMM itself.

Therefore, in order to run a process in a paging virtual machine, the address A where the process occurred is first mapped to the virtual memory address A' using the page table of the virtual machine, and then It is necessary to map this X to the real (recl) address A" by the page table of the VMM.

In order to effectively perform this double mapping operation,
The VMM software constructs a composite page table (which maps virtual process address A to real address A") and uses this map to control address translation hardware.

When the VMM transfers a page from memory, it must first modify its own page table and then recompute the composite map.

Similarly, if a privileged software kernel modifies a virtual machine's page table, it must be notified so that the VMMR:composite map can be recalculated.

Because the virtual machine's page table is stored in normal memory locations, instructions that reference the table are not necessarily trapped by ■■.

Therefore, this change will not be detected by the VMM, and correct operation cannot be guaranteed.

An r II J virtual machine running on an extended interface is generally easier to configure than a VMM running directly on a bare machine.

The reason is that when performing complex operations such as Ilo, V
This is because the MM can utilize the instruction repertoire of the extended machine.

In addition, the VMM may also include memory management functions (paging functions) for the extended machine.

) and its file system advantages.

The "■" virtual machine was configured for the extended machine interface planned by the UMMPS (University of Michigan Multiprogramming System) operating system.

As mentioned above, UMMPS operates on the IBM Model 67 and therefore VMM operates on the F of UMMPS.
can utilize the same processor state "mapping" function that the CP-67 does.

However, a VMM instruction that initiates a virtual machine operation should not cause subsequent privileged instruction traps generated in the virtual machine to be triggered directly, but should refer to the VMM for proper interpretation. That, U
MMPS must be notified.

Furthermore, the instruction to start the operation of the virtual machine is
UM to change (update) the page table to reflect that the new address space has been used
Command the MPS.

If the virtual machine being created is paged, the pages that appear in the virtual machine's memory
It is necessary to construct the result table using tables.

This operation is performed by paging type virtual in F of CP-67.
It's completely analogous to building a machine.

The I10 operation in the original (7) UMMPS r II J virtual machine traps the instruction that started the channel program execution, and then
S transferred control to the VMM for handling.

The VMM moved the channel program into its address space by applying the virtual machine's page map if necessary and then adding a constant relocation factor to each address.

After this move, the VMM called UMMPS to execute the channel program.

UMMPS then absoluteized the channel program and started its execution.

In addition to the necessary overhead mentioned above, this mapping procedure made it impossible for the virtual machine to execute self-modifying (changing) channel programs.

Recent fixes and changes to the UMMPS Virtual Machine Monitor software have alleviated this situation.

This modification involves positioning the virtual machine memory within real memory so that the virtual and real addresses of each location are the same.

This eliminates the need for absoluteization of channel programs, improving efficiency, and at the same time allows self-correction and change of channel programs.

One of the difficulties that had to be overcome when making this change to the VMM was that the actual location, which was a "copy" of a particular virtual machine memory location, was already in use by the UMMPS.

The solution is to simply rewrite the privileged software kernel in virtual memory so that most locations are never used, since the software kernel 0/S is made to run on the virtual machine monitor VMM. Was that.

One unique approach to the problem of creating virtual machine structures is based on the idea of eliminating privileged states completely.

The proposed scheme notes that the first and practically only function of the privileged state is to protect the address mapping mechanism of the processing unit.

If the address mapping mechanism is removed from the base machine interface and made completely invisible to software (so that it cannot be detected by software), there is no need to protect this mechanism, and there is no need for a privileged state.

The single-state structure described above is a recursive virtual machine.
Good for creating systems.

However, the base machine interface associated with such a structure lacks many privileges that are useful when writing privileged software kernels.

These features, which were included to some extent in later 3rd generation computer systems and will be included in 4th generation systems, include the descr 1p
tor)-based memory addressing mechanism, multiple rings (levels) for protection, and process synchronization primitives.

Recent research into virtual machine architecture for these more complex systems is based on the important differences seen between the two different types of failure.

(Nie O. Gabriardi on the structure of virtualizability at the ACMAICA International Computational Symposium in Penis, Italy)
0. Differences between the proposals of R.P.Gagl 1ardi) and R.P.Goldberg.

) The first type relates to software-visible (detectable) privileges of the base machine interface, such as special@/unprivileged states, address mapping tables, etc.

These faults are handled by a privileged software core running on that interface.

The second type of failure appears only in virtual machine systems and includes resources that are available in the virtual machine but unavailable in the real system (e.g. virtual machine memory that is not in real memory). Occurs when a process attempts to change a resource map that maintains or references a VMM (virtual machine monitor) location.

These failures are handled only by the VMM and are completely invisible (undetectable) to the virtual machine itself.

Failures that result from references to unavailable real resources were not explicitly identified in this sentence.

The differences cited in this application are based on subsequent research by Goldberb.

(Department of Engineering and Applied Physics at the University of Harvard [Structural Fundamentals for Virtual Computer Systems]) A normal VMM (Virtual Machine Monitor) supports both types of failures, since the normal structure supports only the former type of failure. Enables mapping of failures to one mechanism.

As mentioned earlier, this is done by running all virtual machine processes in unprivileged mode and directing all failures to the VMM, and the VMM
A clear improvement to this situation can be realized by creating structures that recognize and support both types of failures.

Few contemporary computer systems created machine systems, and most current computer systems do not and cannot support virtual machines.

A small number of virtual machines are currently running, e.g. CP-
No. 67 utilizes inconvenient and inconvenient technology due to its inappropriate structure.

When computer architectures specifically designed for virtual machines were proposed, they had two fundamental weaknesses.

That is, it is not possible to directly support modern complex operating systems in virtual machines or avoid all of the traditional inconveniences and significant software intervention overhead associated with virtual machine support.

What you need is a descriptor
A memory addressing scheme based on
tive, pseudo-instruction calls, etc.), which can be implemented in existing conventional computer systems or fourth generation computer systems.

Furthermore, it is preferable that these virtual machine concepts can be realized with relatively small changes and modifications to the hardware/firmware.

(The above content is based on G.P. Buzen (J.

P-Buzen) and N. O. Gabrieldi (
"Evaluation of the structure of virtual machines" by U., 0, Gagl 1ardi) and Goldberb (R, P.) mentioned above.

Goldbeng)'s ``Structural Principles of Virtual Computer Systems''.

(C) OBJECTS OF THE INVENTION The main object of the invention is to provide an improved virtual machine.

Another main object of the present invention is to
The objective is to provide a virtual machine that can directly support modern complex operating systems such as Multis.

Another main object of the present invention is to provide a virtual machine that eliminates the inconvenience and time associated with significant VMM (Virtual Machine Monitor) software overhead.

Another main object of the invention is to provide an improved virtual machine that can be added to existing computer systems.

Another object of the present invention is to provide a virtual machine that can be implemented in existing computer systems with relatively few hardware/firmware changes/modifications.

Another object of the present invention is to dynamically configure various resource maps that must be used to run a process in a virtual machine by hardware and firmware, so that a hardware partializer can be used. (virtualization device).

Another object of the invention is to provide a hardware partializer for use in configuring improved virtual machines.

Another object of the present invention is to process processes using a composite f and φ map consisting of an ``f map'' that maps virtual resource names to actual source names, and a ``φ map'' that maps process names to resource names. An object of the present invention is to provide a hardware partializer for running a computer on a virtual computer machine.

Another object of the present invention is to provide a hardware partializer that is applicable to different φ maps and is also applicable to computer systems regardless of the φ map.

Another object of the present invention is to provide a hardware partializer for running processes in a virtual computer system that can be applied to a wide variety of f-maps.

Another object of the invention is to provide a mechanism by which recursively improved virtual machines can be run.

Another object of the present invention is to provide a /'%-doware partializer for running a recursive virtual machine while indicating the active virtual machine with a 1 dentifier register.

Another object of the present invention is to handle virtual machine failures with appropriate virtual machine monitors (without knowing other virtual machines or software running on the virtual machines).

) to provide a hardware partializer that runs a recursive virtual machine by directly notifying the virtual machine.

Another object of the invention is to provide a recursive system operated by special hardware instructions.
The purpose of the present invention is to provide a hardware partializer for running virtual machines.

Another object of the present invention is to
(subtree) fails, the appropriate virtual machine is reactivated without knowing any intermediate virtual machines along the branch, and the virtual machine is activated by hardware instructions. The purpose of the present invention is to provide a hardware partializer for running recursive virtual machine structures.

Another object of the present invention is to create a composite recursive f-map and a φ-map in which the recursive f-map maps virtual resource name levels to source names and the φ-map maps process names to resource names. An object of the present invention is to provide a hardware partializer for running processes in a virtual computer system based on the following.

Another object of the present invention is to provide a hardware partializer that can run multiple φ maps in a partial room machine.

Another object of the invention is to
An object of the present invention is to provide a hardware partializer for running multiple virtual machines with rdecor differences.

Another object of the present invention is to detect all process exceptions in a running virtual machine without the intervention of VMM (Virtual Machine Monitor) software.
ion).

(D) Summary of the Invention Honeywell Series 6000 (Honeywell Series 6000)
A virtual machine, which can be implemented in an existing computer system such as the Series 6000, uses a hardware partializer (virtualization device) that runs a process on a virtual computer machine with a composite f and φ map F. Be equipped.

A ``φ map'' that represents a map visible to (and detectable by) operating system software running in a virtual machine maps process names to resource names.

The f-map, which represents a map that is invisible (undetectable) to all software running in a virtual machine, allows virtual resource names to correspond to real source names or other virtual resource names, and does some recursion. It can have levels.

The φ map is an intralevel map, representing the interrelationships within one level, and the f map is an interlevel map, defining the interrelationships between resources at two adjacent levels of a virtual machine.

The φ map is combined with a recursive f map to create a general composite map.

A hardware partializer uses a database to represent the f-map, provides instructions for running the f-map, provides a means to identify the virtual machines in operation, and・Provides a mechanism for handling failures within the machine.

A hardware partializer allows all process exceptions (interrupts) to be handled directly within a running virtual machine without the intervention of VMM (virtual machine monitor) software.

All resource failures (
VM failures (VM failures, perchamill machine failures) can be detected using the appropriate Virtual Machine Monitor (V
MM).

(E) GENERAL DESCRIPTION OF THE INVENTION The concept of virtual computer machines has just appeared on the horizon of "electronic computer systems" and is still understood by only a small minority of engineers in the computing field.

In order for the present invention to be fully understood and easily implemented by one of ordinary computer engineering, it may be beneficial to review some of the prior art.

However, in order for the subject matter of the present invention to be fully understood, an introduction to the description of the preferred embodiment is provided by developing a model of the present invention that represents resource mapping and addressing functions by processes executing in virtual machines. It would also be beneficial to do so.

Furthermore, in order to derive the structural principle of the virtual machine,
It may be preferable to provide a model that represents the execution of a process in a virtual machine.

This principle can be applied to a wide range of computer systems, from minicomputers to current 3rd generation general-purpose systems, and even future (perhaps 4th generation) machines, so all these systems have something in common. It will be necessary to provide a model that connects the

This model should not depend on the particular map structure visible to the software of the machine being described.

Forms such as memory relocation or supervisory states are features of existing systems, whether or not they are virtual machines.

In describing virtual machines, we use a notation common to all virtual computer systems to define different and independent "mapping" structures.

The unifying theme is the architecture of virtual machines and the concept of a set of "virtual resources."

For example, resources such as the size of main memory in a virtual machine can be controlled by memory relocation (
It is a feature of all virtual machines, regardless of the particular virtual processing device type, that they have capabilities such as relocation (relocation).

The focus is therefore on the relationship between resources in the virtual machine fabric and resources in the real (host) machine fabric.

Once this relationship is fully understood, we address the complexity introduced by any additional mapping structure.

(b) Resource map virtual 'machine resource mapping (photo 1m)
) is a model for resource sets V-V that exist in a virtual machine configuration.

, ■1.・・・・・・・・・, Vm) and the resource set R-(rO+ rl + ・・”・・”・+ r n) existing in the real (host) machine configuration
It is developed by specifying the

(real and virtual resource space (lu area)
Both are represented by squares in the drawings.

) Sets ■ and R contain all main memory names, addressable processor registers, I10 devices, etc.

However, for ease of explanation below, we will treat all resourceizations as if they were memory names (ie, addresses).

Since a memory location can then be used to refer to other resourceizations such as processing registers such as DECPDP-10 or I10 devices such as DECPDP-11, it is not general enough to treat all resourceizations as memory names. not lost.

Since no correspondence is assumed ``a priori'' between virtual names and real (resource) names, a method must be introduced to map virtual names to real names while the virtual machine is running.

Eventually, for each instant the following function is defined:

f:■→RU(t) Here, R is a set of real resources of the system, t is an event ((event)) indicating the occurrence of a trap or fault, and f is [R sum ( uni
on) is a resource map of the set V of virtual resources for the set tJ.

Therefore, if yε■ and 2εR (where yεV represents that y is an element or element of the set ■, and 2εR represents that 2 is an element of the set R, that is, y is a virtual resource. 2 is a real resource) To relate the elements of one set to the elements of another set, f(y)=z... When 2 is the real name for the virtual name y.

Or =t......when y does not have a corresponding real name.

That is, at a particular time, if Z is a real resource corresponding to virtual resource y, then f(y) = 2, and if y does not have a corresponding real resource assigned to it, then f(y - t). be.

At f (y) = t, the trap or fault is routed to some fault handling procedure on the machine with resource collection R, ie machine H.

For clarity, this event (hand injury) is referred to hereinafter as a VM (virtual machine) failure (not an exception-interrupt).

This function f is a resource map, a virtual machine,
It is called a map or f-map.

The software on the real machine R that takes control in the event of a VM failure is called the virtual machine monitor (VMM).

In the model, f maps are page maps, relocation maps,
There is no requirement that it be a boundary (R-8) map or any other type of map.

However, interest in virtual machines is limited to the extent that the virtual machine is an exact replica of a real machine and the performance of the virtual machine can be comparable to that of the real machine.

(b)) Recursion The resource map model created as described above can be used as two adjacent levels of virtual resources.
and recursive ones (recu
rs ion ) directly.

By doing this, the actual physical machine is at level "0" and the f map represents the correspondence from level In+IJ to level rnJ.

Recursion for virtual machines is a very interesting feature in practical terms.

In simple terms, a normal operating system can be run in a virtual machine, and
The motivation for virtual machine recursion is the need to be able to run at least a second level virtual machine in order to test VMM (virtual machine monitor) software in a virtual machine.

Unless virtualization is recursive,
It is possible to create only one separate level of virtual machines, and therefore it is not possible to create software that handles virtual mode exceptions (Virtual Machine Monitor, VMM) while allowing normal processing to occur in the system. It is impossible to derag (remove errors).

In fact, to debug the VMM along with other operations,
It is necessary to run one virtual machine to run the VMM and thereby generate a second level virtual machine.

From a practical standpoint, what is needed is limited recursive capability with two levels encompassing virtual machines.

This minimal capability allows the VMM software to be debugged without other operations taking place in one system.

In the following discussion, we use the rPL/Ij-style naming convention of a tree of qualified names, in which a virtual machine at level rnJ has n syllables in its name.

FIG. 1d shows the virtual virtual machine of the present invention with recursive performance.
A schematic of the machine is shown.

A VMM (virtual machine monitor) exists in an actual machine at level "0".

Two virtual machines rVM1 and VM2j exist at level "1".

VMI has a tree salt of '1' and VM2 has a tree salt of '2'.

There are two VMrVM3 and VM4J at level "2".

VM3 is tree salt r2. IJ VM4 is tree salt r2.
It has 2J.

(In FIG. 1d, the names of the VMs that are being executed, counting sequentially from the "0" level, are r2.1.1.)

) As is clear from this, there are n syllables in the name of a virtual machine at level rnJ, and it takes n syllables to actually make the resources at level rnJ of a virtual machine correspond to the real machine. You will find it necessary to synthesize the map.

This naming convention ensures that the "ancestors" of the running VM,
In particular, its "parent" can be uniquely named.

Therefore, if a running VM experiences a virtual machine failure, the hardware/firmware will fail to update the running VMr 2.1. I J (7) r parent” VMr2.
It can be concluded that control should be transferred to the VMM operating at IJ.

This tree salt is used as a subscript of the f-map corresponding to the virtual resource space.

That is, they become "vl, 1" and "fl, 1", respectively.

Therefore, fl :Vl−-R(level “1” which associates Vl with R
"resource map) fl, 1 :vl, 1v1 (Level "2" rinse map that associates Vl, 1 with V□) As a result, the level "2" virtual resource map y" is r2< ft, t (y) ) or float, 5(y).

This is shown in Figure 2a.

Note that "○" in the second equation above is an ordinary function composition operation symbol for numbers.

The above map and Figure 2a show how to map level ``2'' to level ``1'' to level ``0'', that is, the actual machine (mapping function).
It shows whether two virtual machine maps fl and fl,1 are combined (combined).

Now that the f-map has been defined, the virtual resource will be mapped to a real resource or a virtual resource at a different level, or will fail.

Figure 2a shows the virtual machine ■1.1 virtual
The operation of sequentially mapping machine resources to the perchaf L/7 thin ■1 and then to the real machine R (without any failure),
That is, fl(f,,1(z)) is shown.

In the above function f10f1.1, two possible failures are shown below.

(1) Level “2” for VMM of level “1”
Resource (virtual machine) failure, i.e., t
(y) = t (see Figure 2b), (2) Level "0"
Level “1” resource for VMM (real machine) (
virtual machine) failure, i.e. float, t(
y)=1 (see Figure 2c), Figure 2b occurs when mapping resources from an existing virtual resource space v1.1 to a non-existing virtual resource space v1.

For example, it represents a failure that occurs when a page that exists in 1.1 does not exist in vl.

Therefore, in this case, a fault rtJ occurs.

This is a type (1) failure (ie, a level "2" failure) on ft, t (3') = t.

Figure 2c shows type (2) failure (level "1" failure), in which virtual space v1. Resources existing in □ are mapped to virtual resource space ■□, but cannot be mapped to real resource space R.

In the above (1) type failure, due to the features of the present invention (described in more detail below), it is possible to detect (1) type failure without the knowledge (information) of the VMM (virtual machine monitor) running on the real machine R. Control is transferred directly to the VMM running on vl.

This is an important idea. Similarly, map f1.1 is ■
Even if mapping f1 is successful (finding a resource corresponding to vl), if mapping f1 to R is unsuccessful (unable to find a resource corresponding to R), then due to the failure rtJ. , a VMM running on a real machine without knowledge of the VMM running on vl.
Control is transferred to

In conventional virtual machines such as the CP-67, which attempted to realize recursive performance, if a failure occurred at level ``1'', this failure was handled by referring to level ``0'' (the reason for this is (This is because there was no mechanism to deal with actual failures.)

The software then returned it to level "1".

As a result, software overhead (processing time) has become extremely large.

In general, synthetic f-maps can suffer from both failures.

However, there is a class of maps called "inclusive maps" that cause only the first failure (level "2" failure).

The relocation boundary (R-B) map is inclusive, but the page map is not.

The inclusive case implies the possibility of a simple reification of recursion.

Generally for level rnJ recursivity, flofl,
10...○f1.・・・・・・・・・1
0) is mapped (corresponding is done) n
Use level virtual names.

(See 2nd cl.) This model can be used to describe a single-state recursive virtual machine (see Table ■).

(c) Process map "φ" The model just described represents only the "mapping" of resources in a computer system.

This method does not take a local mapping structure, for example, D
This is sufficient to consider the virtualization of a range of minicomputers such as the ECPDP-8.

However, many current (3rd generation) general purpose systems have additional "software visible" hardware maps.

These additional structures include simple supervisor/problem-like M (IBM System/360) and relocation boundary (R-8) registers (DECPDP-10 and Honeywell 6000), and more complex ones such as segment paging, Ring (Honeywell Information System's Multitics)
J) There is something.

In future 4th generation systems, maps will likely become even more complex and will formally embody the hardware/firmware process model.

The critical point about each of these hardware maps is that they are software visible (detectable).

Some systems extend this visibility to unprivileged software.

However, in all cases the map is visible to privileged software.

Typically, the operators of these machines.

The programming system dispatches the user's process (
will change the map information before completing the process).

Changing or modifying a map is simple in a simple case by changing the processing device mode to a problem state, or in a complicated case by changing the process address.

This corresponds to changing a space by switching its segment table.

However, in either case, subsequent execution of the process and its access to resources will be affected by the current local map.

Therefore, in order to correctly model the operation of a process in a virtual machine, a local manipulating structure must be introduced into the model.

The model of the hardware map visible to software is the set P2 of process names (, po tpl...
p7) as a set of names addressable by processes running on a computer system.

(In Figures 3a and 3b, the process space is represented by a circle)
(rQ , r, ......, rn) (real)
A collection of resource names.

The working process is then provided with a way to associate process names with resource names during execution of the process.

Finally, using all of the software-visible hardware manipulating structures such as supervisor/problem states and segment tables, the following function is defined at each time:

φ:P → RU(e) (Here, R is the set of real resources of the system, e is an event indicating that an exception has occurred (hand injury), and φ is "R
is a software map visible to the operating system that associates a set P of process names with a set ``.''.

) Therefore, if XεP, yεR (here, XεP represents that X is an element or element of the set P of processes, and yεR represents that y is an element of the set H of resources, respectively.

) To relate the elements of one set to the elements of the other set, use φ(x)2 y --- If y is the process name
or = e... If X does not have a corresponding resource, that is, if y is a (1) resource corresponding to process name X, then φ( X) is equal to y, and φ if X does not have the corresponding (real) resource assigned to it at a particular time
(x) is equal to e.

When φ(x)=e, an exception (interrupt) is raised to some "exception" handling procedure, perhaps a privileged procedure in the machine's operating system.

To avoid confusion with the above-mentioned VM (virtual machine) failure, process traps are referred to as "exceptions."

The function φ is called a process map or φ map.

This name "process map" applies regardless of the shape of the φ map.

In future (4th generation) systems, φ will probably actually represent a firmware instantiation of the process, but this need not be the case.

The important point about φ is that, unlike f which is an interlevel map, it is an intralevel map in the φ force button-cal (local) and does not intersect the levels of recursive mapping.

) Virtual machine operation (f○φ) Virtual machine operation
Running a process on a machine is a virtual
It means running a process in a configuration with resources.

Therefore, run the process P = (po, pl, ......, p,) on the virtual machine - (vo, vl, ......, ■IT1). As described above, φ:P→VU(e) Here, the virtual resource name "v" is replaced with the actual source name in the resource range of the map.

Next, the virtual resource name is mapped to the equivalent real name by the map, that is, f: ■→R Therefore, the process name (X) is the real resource f(φ(X)
) corresponds to

Generally, the process name is mapped to the actual source name based on the (composite) map f○φ: P−+RU (t)U (e) (the above symbols are as defined above). Synthesis) map is 2
One of the operations may fail to match a process name to an actual source name.

In the case of the process name "Exception" (Figure 3a), VMM (
Control is transferred to privileged software of the operating system within the same level without the knowledge or intervention of the virtual machine monitor.

However, in the event of a virtual name failure, without operating system sensing or intervention (Figure 3b)
, control is transferred to a lower level virtual machine process.

This fault handling software in the VMM is not the subject of the f-map because it runs on the real machine, but it is the subject of the φ-map just like any other process on the machine.

FIGS. 3a and 3b show a process space P shown as a circle, a virtual resource space ■ and a real resource space R shown as squares.

To provide an effective mapping function, a process name Pa in process space P is mapped to point Va in virtual resource space V and finally to point Ra in real resource space H.

However, FIG. 3a shows that an "exception" e has occurred in virtual space V, where control remains in the virtual machine running within virtual space V.

This "exception" is transferred to the virtual machine's privileged software for handling by the virtual machine's privileged software.

In Figure 3b, ``φ mapping'' was effective for point Va, but when mapping Va (virtual resource) to the lost resource, a failure ``t'' occurred, which caused the virtual - Handled by machine monitor.

Typically, in the case of Figure 3a, the rGcO8J (registered trademark of Honeywell) operating system is running in a virtual machine ■, and the rGcO8J
A user operating in unprivileged mode under
When a program attempts to use privileged instructions of the operating system.

In this case the "exception" is handled by the rGcO8J operating system.

A typical example for the case of Figure 3b is the same r
A GcO8J operating system program references a portion of main memory in rGcO8J's allocated virtual memory, but that portion of virtual memory is not in main memory at that particular point in time. In this case, a failure occurs in the virtual machine monitor of real machine H.

This fault is sent to the R VMM for handling by the R VMM.

The φ map is combined with the recursive f map to form a "general" synthetic map flofl, 10...○f1.1...
・・・・・・Make 110ψ.

Therefore, regardless of the level of recursion, there is one application of the ψ map to a virtual machine, and an application of the f map to n
There are several applications.

This is an important consequence of the definition that distinguishes between f-maps and φ-maps.

Therefore, in a system with a complex φ map and a simple f map, it is easy and inexpensive to implement n-level recursion.

In the submitted model, the f-map maps resources at level rn11 to resources at level rnJ.

Similarly, an f-map can be easily defined that maps resources at level rn1 to process names at level rnJ (which process names are then mapped to resource names at level rnJ).

This new f-map is called a "■"-type f-map to distinguish it from the rlJ-type f-map described elsewhere.

(e) Interpretation of the Model Models are very important because they show that there are two very different basic maps of virtual machines.

Traditional concepts did not clearly distinguish between maps.

The main point is that f-maps and φ-maps are very different and are used for different functions and purposes.

There are no overriding conditions for these maps, such as that they must take a particular form or have certain relationships.

φmap is an interface (
The f-map is the interface visible to the resource.

To add a virtual machine to an existing computer system, only the f map must be added since the ψ map is already defined.

The choice of making the f-map relocation boundary (R-B) type, paging type, etc. depends on how the virtual machine's resources are used.

In any case, the f-map is recursive, and the ψ-map need not be recursive.

When a new machine is designed, neither the φ map nor the f map has yet been defined.

The φ map may be chosen to idealize the structure visible to the programmer, while the f map may be chosen to optimize the utilization of resources in the system.

Another essential difference between maps is that f-machines are virtual
It supports levels of resource allocation between machines, while the φ map establishes layers of privilege (ring, master/slave mode) within a virtual machine.

The following table (1) shows a comparison of the characteristics of virtual computer systems that use or are intended to use the model described above.

As is clear from Table I, no existing or proposed prior art system directly supports a fully general-purpose virtual machine.

The CP767 has a unique φ map but does not provide direct hardware support for an f map.

The Lauer and Snow scheme provides direct hardware support for the f-map, but has an ordinary φ-map (φ=identity).

For this reason, CP-67 must use the layer correlation between the software and the φ map to simulate the level, but in the case of Lower and Snow, the level reciprocity between the software and the f-machine is required to simulate the layer. must be used.

As such, these systems are uncommon and do not support modern operating systems running directly on individual virtual machines.

Gagliard - Goldberg
i-Goldberg)'s "Venice Proposal"
Proposal) J (VP) suggests support for layer and level correlations.

However, since vP does not directly provide hardware support for f-maps, software intervention is still required.

References for ■ to ■ in the table ■ above: ■ 1970 IBM System Journal vol.
9A3 “Virtual Machine Time Sharing
System'' ■ 1972 A, CM AlCAl International Computing Minbosium ``Practicalizer Pull Architecture'' ■ Same as above ``Is Supervisor State Necessary?'' ■ 1973
ACM 5IGARCH-8 IGOPS Workshop Conference "Recursive Virtual Machine Architecture" (F) Description of Embodiments Next, embodiments of the present invention will be described.

(b) Hardware partializer (HV) A hardware partializer (HV) capable of identifying existing or proposed systems of the virtual machine model described above, and capable of materializing (realizing) virtual machines in all ordinary computer systems. ) show natural means of doing.

Since the f-map and the φ-map are separate and possibly different in the virtual computer system, each map should be represented by an independent construct.

When a process running in a virtual machine refers to a resource using a process name, the required actual source name should be obtained by dynamic composition of the f map and the φ map at the time of execution.

Furthermore, the results should hold regardless of the recursion and regardless of the particular form of the f and φ maps.

The first embodiment is a generalized one, and FIGS.
It has the configuration shown in Figures a and 6b.

The second embodiment is a special one, in which the φ=RB map and the f nipaging map (in the main memory area)
This is shown in FIG. 7.

), “It can be added to the Honeywell 6000J.

The third embodiment can be added to the Honeywell 6180J, and as shown in FIGS. 8a and 8b, the φ
- Contains a projection map and an f=R-8 map in the main memory area.

The hardware partializer rHVJ described below embodies the inventive concept described above.

This HV can form part of an extension of an existing system and can be part of a new machine design.

(b) HV design and requirements Hardware virtualizer The following points should be considered when designing the HVJ.

(1) Database for storing f (shared data) (2) Mechanism for calling f (3) Mechanism for map synthesis (4) Operation in the event of a VM (virtual machine) failure・The parturizer is
The map synthesis function will be accomplished, and the partializer itself, supporting control mechanisms, typical instructions used to create recursive virtual machines, and various failure handling mechanisms will be described.

Since existing computer systems such as the Honeywell 6000 series, DEC PDP-10, IBM Systems/360 series, etc. include some type of φ map, additional structures related to the f map will be described.

In the following, the present invention will be described with reference to the four considerations discussed above, and the structure and operation of the hardware partializer will be detailed with respect to two specific embodiments.

The VMM (virtual machine monitor) of database level rnJ to represent Gl f has two adjacent levels, namely level rn+IJ
Create and maintain a database representing f-map interrelationships between virtual machine resources at level "n" and virtual machine resources.

This database is stored so that it is invisible (undetectable) to level In+IJ, even the virtual machines containing the most privileged software.

For economic reasons, we assume that the database is stored in main memory.

Therefore, although f will not exist in the (virtual) memory of level /1zrn+IJ, it must exist in the (virtual) memory of level rnJ.

One requirement to write a memory at level rnJ is that it allows the HV (hardware partializer) to write a memory at level rnJ by applying a "decision algorithm" from the starting point (ROOT, base point) of memory at level rnJ. The purpose is to be able to find the f-map.

The f-maps corresponding to other virtual machines at the same level are given implicitly or explicitly.

FIG. 4 is a block diagram for explicitly showing the f-map.

Specifically, FIG. 4 depicts in block diagram form main memory 400 in a level rnJ virtual machine of a typical computer system such as the Honeywell 6000.

ROOT 401 is a fixed, known address within memory block 400 and includes (among other information) a VMTAB (virtual machine table) pointer 407.

This VMTAB pointer 407 is the VMTAB (virtual machine table) 40 in that memory block.
Indicate the location of 2.

The VMTAB 402 includes entries for VMCB (virtual machine control block) pointers VMI to VMK.

Each VMCB pointer points to a respective virtual machine control block.

For example, VMCB pointer VMI is VMCB-1,40
3, pointer VM2 points to VMCB-2, 404, respectively.

The VMCB (Virtual Machine Control Block) provides information for the mapping of virtual machine resources, so typically the VMCB
includes data/hardware structures such as memory maps, process maps, 10 maps, virtual machine state information, etc.

So basically the VMCB is an f-map of a particular virtual machine.

For example, VMCB-1 is the f-map for virtual machine "1" and VMCB-2 is the f-map for virtual machine "2".

The specific shape of the VMCB varies depending on the f-map actually used, such as for R-B paging.

If a paging scheme is used, the VMCB's memory map typically includes page tables 405, 406.

Additional information that may be maintained in the VMCB includes capability information about the virtual processor, indicating special capabilities, instructions, their presence, or absence.

Examples of this capability bit include scientific instructions and virtual machine instructions (recursive).

If recurrence is supported, VMCB will have a low irregular VMi.
Contains sufficient instructions to automatically restart a high-level virtual machine upon failure (see blocks 506-512 of FIG. 2C and FIG. 5).

The data structures are known to the firmware and can be automatically invoked during map synthesis operations, and the data structures are relative between levels rn+1j and rnJ.

) Mechanism for invoking f To invoke an f map, the HV (hardware partializer) requires one known register and one instruction to manipulate it.

This register is the virtual machine identification register (VM
ID), 653 in FIG. 701 in FIG. 1, and includes the "tree name" of the virtual machine currently running.

VMID is a multi-syllable register,
The syllable represents all of the f-maps that must be synthesized to provide the actual source name.

When it is desired to run a virtual machine at level "2", the VMID contains two syllables and forms the tree name of the current virtual machine at that level.

The command rLVMIDJ (load into VMID) shown in FIG.

) adds a new syllable to the VMID register.

Therefore, the syllable in VMID at that point is 1.
And when the VMM wants to start virtual machine number "3", it adds "13" to the current number of VMID registers using the LVMID command to create a chain number r1.3J.

The VMID register (and LVMID instruction) has four determining characteristics:

(1) The "absolute" contents of the VMID register cannot be read or written by software. (2) The VMID of the real machine contains a blank representation or "zero." (3) Only the LVMID instruction can append a syllable to the VMID. (4) Only VM failures (or instructions that terminate virtual machine operation) remove the syllable from the VMID.

FIG. 5 is a flowchart of the LVMID command, except for the implementation part related to the specific selection of the map.
It represents the operation of the D instruction.

In FIG. 5, the LVMID instruction is called at r501J and the virtual machine (V
M) A determination is made whether a capability exists.

That is, it is determined whether the machine is allowed to create virtual machines.

If virtual machine capability does not exist, a VM capability "exception" occurs in r503J.

Otherwise, the VMID syllable is called in r504J.

Next, the VM running at that time on r505J is 0.
Determined whether it is at a larger level.

If the level is thicker than O, in r506J, the called syllable (the oscilland of the LVMID instruction) is stored in the "next syllable" field (area) of the VMCB (virtual machine control block) at that point.
is memorized.

(In box 506 of FIG. 5, VMID is used as a subscript to indicate the current control block, i.e. vMcB[VMIDl, so that the syllable of the operand of the LVMID instruction is the current VMCB ``Next Syllable'' field.

) syllable is appended to the VMID and the level is incremented (see boxes 507, 508, 509 in Figure 5).

This newly identified virtual machine is now running and its processor registers, memory map, etc. are loaded from its VMCB (box 5).
10).

The "next syllable" field of the active VMCB in r511J is called.

If this field is blank, i.e. zero (r
512J), the instruction completes with r513J.

If the "Next Syllable" field is blank, then the flowchart in boxes 508 through 513 will cause the fault to jump through at least two levels of virtual machines and then jump to a virtual machine structure lower than the level at which this jump occurred. When present, a procedure is provided to create a virtual machine subtree.

(E) Map synthesis The map composer (com) shown in Figures 6a and 6b
poser (synthesizer) performs dynamic synthesis of the φ map (possibly the identity map) and the operational f map each time a resource is accessed.

The φ map is known and the operating f map or VMCB
(virtual machine control block) is V
Determined from the MID register.

The flowchart of FIG. 6a depicts the map composition image configuration except for the implications of specific selections of maps.

As is clear, this map composer receives a process name P and generates a source name R to be executed, but causes a VM failure.

In Figure 6a, the map composer is called at r601J and the process name P is retrieved at r602J.

In r6G3J the φ map is applied to process P to obtain φ of P, and in r504J a determination is made whether a valid mapping exists.

If an invalid mapping occurs, for example when attempting to refer to boundary-based memory, a process ``exception'' will occur.
happens.

This "exception" is already a local "exception" handled within the same virtual machine that is the call.

This "exception" is therefore visible to and handled by privileged software, and the VMID register is unaffected.

On the other hand, if the φ mapping of the process is valid (when the value "φ" of P can be calculated), the value φ of P is temporarily stored in the internal register [resource name RJ] in r606j.

The VMID register is then checked to determine if it is blank, and if so, the composition operation is complete and the computed resource name R is the actual source name.

This process consists of V (copied to internal register V)
Change the value of MID to ``607J and set the level value (copied to scratch pad (temporary use) register L) to 1.
608'' respectively, and r609J takes out the level value (
This is effectively done by determining whether L) is zero.

If the "0" level exists, that is, if the VMID is blank, R, which has already been mapped, is indeed a real resource, and the 6109 synthesis is completed in r611J.

On the other hand, if there is no "0" level in r609J, then R must apply the f-map represented by the next syllable in the VMID register, rather than the real resource.

Next, go to r612J, f? ', /p is obtained from the VMCB represented by the current contents of the 7MID register.

In r613j, it is determined whether a valid mapping exists, and in r613J, if a valid mapping exists (that is, if a value f(R) that appears to be a real resource has been calculated), box 6
14,615,616 and 609 to obtain f(R)
It is necessary to determine whether or not the resource is a real resource.

Therefore, the value f(R) mapped to f
is copied as if it were a real resource R (box 614), ie, R is replaced by f(R).

Next, the Lth syllable of ■, that is, the internal register copy of VMID is blank (null) in r615J.
) and the internal level count "L" is decremented by "1" at 616.

A check is made in r609J to see if level "L" is 0 (i.e. the machine is 0).

A check is made to see if it is at the real machine level), and if not, boxes 612-616 are repeated until L=0.

If L=0, R is determined to be a real resource in r610J, and the synthesis is completed.

Ru.

To illustrate the process of boxes 612-616:
The VMID register contains the tree salt r1.2.4. Assume that J exists.

The contents of the VMID register have been copied to V (see box 607).

Furthermore, as is clear from box 614, R is f(
R).

r615", the syllable of ■ is "4" and "o
"isn't it.

Therefore, the level rL held in the internal register
J is decreased by "1" and the last level "4" is taken.

Since the tree salt in ■ has been removed, the tree salt in ■ is now rl
, 2J.

Therefore, there are now two levels, and when level "L" is checked at "609", this is "0".
Instead, boxes 612-616 are repeated again.

At this point, the internal identification register V has two levels "1.
2'' and the Lth syllable ``2'' is at the second level, so one more level is removed in r616J, so the tree salt is ``1'', and whether the level is O or not in r609J. is checked.

Although it is not an operation that is repeated only once, when this time is checked in r609j, L is 0 and flow branches to box 610 and the synthesis is completed in r611j.

Proceeding to box 613 of Figure 6a, the virtual machine failure is determined by r61 because there was a mapping that was not valid (i.e., the resource was not found).
Occurs in 7J.

The current syllable utilized in the internal identification register "■" is removed in r618J and the internal level register rLJ is decremented in r619J.

The new level is tested in r620J to see if it is O.

If L is not 0, then VMCB's "next syllable"
The field must be set to blank in r621J.

In either case, the internal level register rLJ is copied to the level register at ``622'' and the internal identification register ``v'' is copied to the item vIMD register at r623J.

In r624J, a VM failure is notified to the virtual machine running at the time.

FIG. 6b is a block diagram of a portion of a generalized embodiment and is directly related to FIGS. 5 and 6a.

Reference numeral 650 represents a map composer and includes hardware/firmware and internal registers 657, 658, 659, 660 utilized in a generalized hardware partializer.

Scratchpad (temporary use) registers 651 and associative registers 652 may be utilized in certain embodiments to improve execution performance (see Figure 8b and its description).

Specific identification means (1 denti
The hardware partializer takes out the given process name rPJ 654, applies the set of φ map 661 and f map 662 to F under the control of fier), and generates the actual source name 655.

Associated with the VMID register 653 is a level register 656 that indicates the current level of the active virtual machine, ie, the number of valid syllables in the VMID register.

VMID register 653 and level register 656
are both selected to have arbitrary maximum dimensions (capacities).

A generalized embodiment uses the following explicit internal HV resistor.

(1) The v register 657 (see 607 in Figure 6a) where the VMID is copied 663 - this register is used to obtain the f-map value in the synthesis algorithm (see 612 in Figure 6a) and the failure Sometimes V
The contents are returned to the MID (664, see 623 in Figure 6a); (2) the level is copied 666 to the L register 659 (see 608 in Figure 6a) - this register is utilized in the synthesis algorithm (see 623 in Figure 6a); 60 in figure 6a
9.616) and the contents are returned to the level in the event of a failure (661, see 622 in Figure 6a); (3) an R register 660 (see Figure 6a) which holds the partially synthesized result until the synthesis is complete; 606, 614) - the R is sent to the real resource register 668 (see 61 in Figure 6a).
0), (4) L VM ID command nod VMID
I register 658 (507.509 in FIG. 5) is used to add syllables to 665.

511.512).

The above-mentioned map synthesis means and LVM for calling f
The ID instructions are embodied in firmware and hardware that utilizes well-known typical computer control units (Samia Nis Husanr, 1970).
samir s.

(See "Microprogramming: Principles and Practice" by Husson J.)

Further, a typical associative memory disclosed in U.S. Patent Application No. 283,617 [Address Generation Technique Using Content Addressable Memory J (filed in the United States on August 24, 1972) is utilized to improve operational performance. .

There are fundamental reasons why a process can effectively run in a virtual machine in a way that resembles a real machine.

Most computer systems that use memory mapping (in the φ map) make the designer's assumptions about program execution performance.

This assumption is equally applicable to virtual machines.

Some of these assumptions that affect the execution performance of a computer system can be "referenced" by running a program.
This is the temporary and special locality (1locality) of .

In multiprogramming systems, processes
Maps are not often changed (process locality), and in virtual machine systems VMIDs are not often changed (virtual machine locality).

Combining all these locality concepts, we can conclude that a multi-level recursive virtual machine need not have significantly different performance from a real machine.

To express this point in other words, it can be said that temporal and spatial locality is name immutability.

Which memory block is called or (composite f
No matter how many times a map is renamed, there is still an inherent possibility that it will be referenced by an executing program.

Therefore, a virtual machine supported by the map composer and associative memory means can have operational performance comparable to a real machine.

If the f-map and φ-map are very simple, no associative device is necessary.

For example, in f2R-B (relocation/boundary register), φ-blank (identity) is used to maintain the R-B value of static synthesis, which is changed only when the level is changed (generally C
HV (hardware partializer) by simply providing an "invisible scratchpad register" (within the PU)
would be sufficient.

If φ includes paging or segmentation techniques, the real machine itself requires an associative unit for performance reasons.

The HV associator can be replaced with this.

If the f map is simple, for example, if f = R-B,
The HV associator is extremely simple.

If f paging is included, things will be somewhat different.

The choice of whether to include the VMID or the "level" as part of the associative device's search key is determined from the viewpoint of price and performance.

The typical associator described above "short-circuits" the composer mechanism described above to directly map process names to actual source names.

This point is discussed in R.P. Goldberb's paper [Structural Principles of Virtual Computer Systems (Archit
ectural principles for Vir
tul Computer Systems) J.

Exemplary Implementation of a Hardware Particularizer As previously mentioned, a hardware partializer serves as a central facility in the design of a new computer system or as an extension to an existing computer system.

In the latter case, it is assumed that the conventional computer system M is provided with a predetermined φ map.

HV configuration e.g. additional data structures, new instructions (LV
MID), VM failure, etc., a new machine M' with a different and unique function is defined.

The hardware partializer optionally M(ll
We ensure that M' becomes a recursive virtual machine capable of supporting an organization of M' machines with ia's machine as the terminal means.

Clarifying the operation of hardware partializers.

In order to do so, we will illustrate two examples of its use.

The first example revolves around a typical third generation system similar to the Honeywell 6000.

The second example revolves around a more complex computer system similar to the Honeywell 6180.

The first example presents some features of a typical third generation structure, shows the introduced extensions of the hardware partializer, and also shows the execution of some instructions.

The examples described below are Honeywell 6000, DECPD
It revolves around standard third generation computer systems similar to the P-10 or IBM System/36o.

The salient features of these structures are (1) instruction counter (I
C) Differences in privileged/unprivileged (master/slave, supervisor/froblem, etc.) modes as part of (
2) one relocation and boundary (R-B) register that can be loaded with "absolute" contents in privileged mode; (3) the main register where the exchange of old and new R-B and IC registers takes place during process execution; It is a fixed memory location.

To simplify the example, assume that the R-B register is active even in privileged mode.

Furthermore, it is assumed that all instructions are executed in privileged mode.

Since a mode violation is a local process "exception" and is treated similarly to an R-8 violation, there is no peace of mind indicating both violations.

When extending the example to include homogeneous operations of Ilo, we utilize the principles, hardware, and techniques described above.

However, this example shows the case where the rR-8 map is a φ map.

The hardware partializer is implemented by the following extensions to the third generation structure.

Adding verge f-maps (in memory areas) to make changes is shown and a 1000 word page is assumed.

(See Figure 7) Changes and corrections (1) Database for storing f.

Level “n” memo IJ-700 (in Figure 7)
Several fixed known locations 704, 714
is a virtual machine (VMCB) with level rn+IJ.
A virtual machine table (VM
TAB) 707.717.

In this case, each virtual machine control block (VMCB708.710,718) has memory
Maps (page tables) 709, 711, 719 and processor maps 708a, 710a.

118a is illustrated.

Page maps correspond to f maps, e.g. fl
corresponds to 709 and fl corresponds to 711'.

The processor map is level In+IJ IC and R.
-8.

What is also included but not shown is the level "
"n+1" is the "next syllable" at level rn+2J that is always stored when an LVMID instruction is issued.

(2) Mechanism for calling f.

Multi-syllable VMID70 Lugistar and the above-mentioned LVMI
D command is added.

virtual·? -// When the switch is activated, its IC and R-B are connected to its control block (VMCB) 7.
Loaded from 08a, 710a, 718a.

(3) Composer (composition means).

The hardware firmware composer and associator described above supported by scratchpad memory (for performance reasons) is added.

(4) Behavior in case of VM failure.

IC and R-8 are stored in their VMCB, the appropriate syllable is removed from the VMID, and control is transferred to the VM failure location γ05. in the VMM (Virtual Machine Monitor). Move to a fixed known location such as γ15.

Note that this example shows an rIJ-type f map, in which a resource at level In+IJ is mapped to a resource at level rnJ.

Therefore, R of the relocation/boundary register at level rnJ
-B value and φ map are not included in mapping.

When LVMID is performed in this example, the relocation matches zero, but that is not necessary.

DESCRIPTION OF THE FIRST EXAMPLE FIG. 7 is a schematic diagram showing the state of the main memory in a machine with virtualized hardware.

FIG. 7 further shows three registers VMID, R-8 and I.
C, but does not indicate its value.

Table 3 instead shows six sets of values for VMID, RB, and IC.

The instructions executed for each set are shown, and the ``number'' procedure used to generate the absolute physical memory address is illustrated.

The table shows process "exceptions", VM failures, and changes to the VMID.

For the value of the R-B register, r is the rearrangement (1000
unit of word), where b is the size of the consecutive assignment 100
(in units of 0 words).

The six columns in Table ■ are divided into three, namely, columns 1 to 3.
, 4.5 and 6.

Of these three sets, columns 1 to 3 are executed consecutively, and columns 5 and 6
will continue to be executed.

Referring to FIG. 7, physical main memo IJ-700 begins at location 0 and extends to word IIK.

The first boundary of the main memory is the 3000th word, and thereafter there is a boundary every 1000 words, continuing up to 1100.0 words.

This memory is part of a Honeywell 6000 system that typically utilizes the GCOS operating system to manipulate the φ map.

In addition to an instruction counter (IC) 703, a relocation/boundary register (R-B) 702, and a virtual machine identification register VMID 701 are added.

VMID register 701 is invisible to software (i.e., cannot be accessed), but R-
8 register 702 and IC register 703 are visible to software (accessible to software)
.

Within the real machine, the VMM (Virtual Machine Monitor) runs between memory locations O and 3.

1st cr) bar-f-yal-masi 7VM, is 3K (!
:8K (7), another virtual machine VM at the second level, , 1 is located between memory locations 5K (!
18 and has VM as the parent virtual machine.

Yet another virtual machine VM2 is shown between memory locations 8 and IIK.

Local process "exceptions" to the real machine are handled in the local process exception location 706, and vMl
Local process "exceptions" to are handled in the local process exception VM, location 716.

These locations are process exceptions, i.e.
It shows the ``point (location)'' to which the program running on each machine should be transferred when an ``exception'' exists.

In this case privileged software (GeO2 in this example)
gains control.

Similarly, when a failure occurs in the f-map area as described above, the program running in a given virtual machine is moved to the appropriate VM failure location area 7.
05°715, the VMM (Virtual Machine Monitor) gains control.

Examine the first few evaluation procedures with reference to Figure 7 and Table ■.

In column 1 of Table ■, the VMM is running on a real machine.

That is, VMID 701 is blank.

With all control blocks VMCB set, it is time to activate virtual machine VM1.

The value of the instruction counter 703 is 2000.

Since the value of the R-B register 702 is 0-14, 20
By adding O to 00 (checking that 200 is less than 1900), we get φ(2000)=2000.

VMID is blank. Therefore resource name 2000
is a real resource, physical location 20 in FIG.
00 (reference number 712) (LVMID28
00) is fetched.

Apply the R-B map to 2800 using the machine's φ map, i.e. location 2800 (reference number 71
3), (which is the content of location 2800)
Fetch 1 last.

This “1” is loaded into the VMID register 701.

At this point, the virtual machine VM1 at level "1" is activated and its IC and R-8 registers contain VMCB.
I, 708a.

Column 2 of Table H shows that IC703 received 2100 and R-8
702 receives rl-3J.

Although the memory of virtual machine vMl is 5000 words (as evident from page table 709),
R-B register 102 controls its operating process to address only 3000 words.

This limit is likely set by the virtual machine VM's operating system.

The reason is that the operating process is that of a standard (non-monitor) user.

As is clear from column 2 of Table 2, the IC is 2100.

1000 is added to apply the φ map, 210
Check that 0 is less than 3000 and use φ(210
0)=3100 is obtained.

Since the VMID is "1", we are operating on a virtual machine, so fl must be applied to map the virtual resource 3100 to its "real" equivalent.

Page table f 1709 pointed to by VMCBl 708 shows that virtual page 3 is at location 4000.

Therefore, fl (3100)=4100 (reference number 720) and the rLOAD128J instruction is fetched.

Other procedures can be similarly evaluated using Table ■.

Column 3 shows the process "exception" to the VMI's local "exception" handling, column 5 shows the recursive behavior, and columns 4 and 6 show the VM failure to each VMM's failure handling.

The scratchpad register (651 in Figure 6b) is
The absolute location of the working page table, e.g., f, 709, is directly indicated to improve performance.

The associative register (652 in FIG. 6b) improves performance by storing several recently synthesized map values, P and "f○φ(P)".

Therefore, after the completion of line 2 in table ■, there is an entry (input) in the associative memory, process name 2000 is the actual source name 4000, process name 6000 is the actual source name 6
000 respectively.

After the completion of the instruction fetch in column 6 of Table H, there is an entry in the associative memory, and the process name 1000 is mapped to the actual source name 5000.

As can be seen, a paging f-map is added that is invisible to level rnJ software.

The already existing rR-BJφ map remains visible at level rnJ.

Therefore, operating systems that are aware of R-8 maps, such as GeO2, or that are not aware of page maps, can run in virtual machines without modification.

It is possible to add an rR-BJf map instead of the paging f-map.

This new rR-Bjf map exists rR-BJφ
It is something different from the map and something that is added to it.

Furthermore, the recursive property of the f-map would have to be satisfied.

Similarly, the paging f-map added to a machine such as the I8M360/67 will be separate from the existing basing-map.

Description of the Second Example The second example revolves around a more complex computer system such as the Honeywell 6180.

A complication added to third generation computers for this example is a segmented address space.

Addresses within the machine are expressed as Is/dJ, where S is the segment number and d is the deviation within the segment.

Therefore, for normal address generation, the hardware partializer in this example, which uses a segment table to find each segment, uses It is materialized in the same way as the example above.

This second example shows only the differences from the first example.

In FIG. 8a, a fixed known location 804 in memo IJ-800 at level rnJ is a VMT that describes a virtual machine (such as vMCBl) at level rn+IJ.
AB (virtual machine table) 805 is specified.

In this example, each VMCB 806, 807 has an R-8 memory map 808 stored adjacent to the rest of the VMCBs.
,809.

Processor map, I10 map, and "Status" are not shown.

Therefore, in the main memory area, the R-B map is an f-map.

A VMID register 801 and the aforementioned LVMID instruction are added.

The map composer and VM failure mechanisms described above (of Figures 6a and 6b) are also added.

In FIG. 8a, physical main memo IJ-800 begins at location 0 and extends to word 14.

The solid boundaries shown in main memory are virtual
The machines are separated.

That is, the VMM (virtual machine monitor) is located between 0 and 3, VM1 is located between 3 and 8, and VM2 is located between 8 and 14.

The dotted border indicates the virtual
It represents segment separation for process P running on machine VMI.

When execution begins, process P1 is activated and its segment table 802 is used to generate addresses for the φ map.

The value of the instruction counter C803 is 21,500.

Segment 2 is vMl memory location 200
Since it is at 0, φ(21500)=2500.

Since the value of VMID 801 is 1, map f1 must be applied to the above result.

Therefore, fl (2500)=5500.

Therefore, instruction 810 at location 5500 is fetched and executed.

This requires generating the address of the operand field.

That is, φ(1/20)=4020, fl(4020
)=7020 is obtained.

The contents 812 of location 7020 are thereby loaded.

The IC (instruction counter) is incremented to 21501 and execution continues.

The next instruction is φ (21501) = 2501 and fl (2
501) = 5501, the location 5501.8
11, and it is fetched.

For this instruction 811, the operand field rl
/2000J needs to be mapped.

However, if the deviation 2000 is the segment dimension i o
Since it is larger than o o, an "exception" occurs due to φ(1/2000)=e.

With this "exception", the current virtual machine VM1
control is transferred to privileged software within the

Therefore, VMID 801 is not affected by this "exception".

To improve performance, scratchpad registers (651 in Figure 6b) and associative registers (652 in Figure 6b) may be provided.

FIG. 8b shows the associative device 85 after execution in FIG. 8a.
It represents the content of 0.

In Figure 8b, segment 2 is the search key for its absolute physical location regardless of recursion.

[Brief explanation of drawings]

FIGS. 1a to 1c are block diagrams showing conventional technology;
1d and 2a-2d are block diagrams illustrating the recursive f-map process of the present invention, and FIGS. 3a and 3.
Figure b is an explanatory diagram showing the process 1 exception of this invention and the occurrence of a VM failure, and Figure 4 is an explanatory diagram showing the occurrence of a VM failure.
MTAB) (!: Virtual Machine Control
Blocks (VMCB) and Virtual Machine Pages
FIG. 5 is a high-level flowchart illustrating instructions that can be implemented in firmware to modify virtual machine identification registers; FIG. Figure 6b is a block diagram of the hardware partializer registers; Figure 1 is a hardware parcher with a particular f-map and φ-map; Figure 8a showing one embodiment of the riser
FIG. 8b is a block diagram illustrating another embodiment of a hardware partializer having an alternative f-map and φ-map. In the drawing, VM is a virtual machine, VMCB is a virtual machine control block, and VMI is a virtual machine.
"D is a virtual machine identification register, VMM is a virtual machine monitor, VMTAB is a virtual machine table, and LVMID is a load into rVMID," respectively.

Claims (1)

[Claims] 1. A general-purpose host that has real resources such as a central processing unit and main memory for executing instructions for user program processing, and includes a φ map for mapping software and process names to resource names. a computer; and at least one virtual machine having virtual resources that simulates the host computer and real resources, respectively; an individual virtual machine and a monitor for the host computer to control each of the virtual computers; and is mapped to the level of a combination of the host computer and each virtual machine, each level of the virtual machine has a virtual resource, and successively higher levels of the combination are such that n is greater than or equal to 0. Any lO decimal number of (n+1
) to O, the levels (n+1) to 1 are the virtual operating levels of the virtual machine, and the 0 level is the real operating level of the host computer with real resources, where instructions of the user program are mapped to real resources. In a computer system that is an internal level, the host computer further performs the following (A), (D), r
(b) register means for controlling access to the individual virtual operator levels from (n+1) to 1; ) is invisible to all software of the virtual machine and is responsive to said register means to establish an association between virtual resources of adjacent levels of the virtual machine.
The (n+1)th virtual resource of the n+1)th level is
(c) visible to at least privileged software of the virtual machine and only from levels 1 to 0 of operations; a) means for displaying a correspondence between a selected one of said processes and a selected one of said real resources in response to said register means, mapping means and display means; Means for establishing a correspondence between said 0 level real resources and said level 1 virtual resources of operation. 2. The apparatus according to claim 1, wherein the register means includes means for identifying the virtual operating level, and the identifying means includes a plurality of syllables corresponding to respective numbers of the virtual operating levels. Apparatus comprising a virtual machine level identifier having a respective virtual machine level identifier, and wherein said register means also includes means for removing syllables from said identifier in order to increase the level represented by said identifier. 3. The device according to claim 1, wherein the universal means includes an interlevel f-map for mapping virtual resource salts to actual source names, and the correspondence display means maps process names to resource salts. An apparatus characterized in that the apparatus includes an intra-level φ map for mapping, and wherein the correspondence establishing means includes a synthesizing means for combining the f map and the φ map. 4. The device according to claim 1, wherein the host computer also includes a virtual machine monitor that operates at the 0 level, and the device controls virtual resources at the level of the universal means by: generates a first signal when the virtual machine monitor fails to move to a higher virtual level, and directly sends the signal to the virtual machine monitor controlling the next higher virtual level without the knowledge of the virtual machine monitor operating at the O level; Apparatus according to claim 1, further comprising means for sending said first signal. 5. The device according to claim 4, further comprising:
The correspondence establishing means generates a second signal when the correspondence establishing means fails to establish a correspondence between the level 1 virtual resource and the level 0 real resource, and without knowledge of any virtual machine monitor controlling the virtual level. , further comprising means for sending the second signal to the virtual machine monitor operating at the zero level.