JPS58199169A - Apparatus for controlling print head - Google Patents
Apparatus for controlling print headInfo
- Publication number
- JPS58199169A JPS58199169A JP8249282A JP8249282A JPS58199169A JP S58199169 A JPS58199169 A JP S58199169A JP 8249282 A JP8249282 A JP 8249282A JP 8249282 A JP8249282 A JP 8249282A JP S58199169 A JPS58199169 A JP S58199169A
- Authority
- JP
- Japan
- Prior art keywords
- solenoids
- solenoid
- currents
- drive
- print head
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J9/00—Hammer-impression mechanisms
- B41J9/44—Control for hammer-impression mechanisms
- B41J9/52—Control for hammer-impression mechanisms for checking the operation of print hammers
Landscapes
- Dot-Matrix Printers And Others (AREA)
Abstract
Description
【発明の詳細な説明】
〔開明の技術分野〕
本発明はワイヤドツトインパクト式のプリンタ等のプリ
ントヘッド制御#C−に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a print head control #C- of a wire dot impact type printer or the like.
ワイヤドツトインパクト式プリンタ等の谷ワイヤビンを
駆動するソレノイドに龜れるi+uit検出し、帰還を
かけて電流wJ#を行なう場合、従来は否ンレノイド単
位に構出回路と帰i1回路が設けられていた。In the case of detecting i+uit which is fed to a solenoid that drives a valley wire bin of a wire dot impact printer, etc., and applying feedback to generate a current wJ#, a construction circuit and a return i1 circuit have conventionally been provided for each solenoid.
上mll従来ノンレノイド電流定値制御方式は、漢字プ
リンタなどのようにワイヤピン数の多い場合には、ハー
ドウェアが大きくなり過ぎる欠点があった。The conventional non-lenoid current constant value control system has the disadvantage that the hardware becomes too large when the number of wire pins is large, such as in a kanji printer.
本発明は上記の欠点を除去することを目的とする。 The present invention aims to obviate the above-mentioned drawbacks.
Olの4g費〕
本発明は上記目的を造成するために、全ワイヤビンを1
つのHIR1!ll路で制御できるようにし、たもので
ある。4g cost of Ol] In order to achieve the above object, the present invention reduces the entire wire bin to 1
One HIR1! It was designed so that it could be controlled by the road.
第1#Aは本発明の一拠施例をがす回路図である。 No. 1 #A is a circuit diagram showing one embodiment of the present invention.
同図Kbいて、(11((1aL(lb)、(1’)・
・)は各ビンをドライブするための入力信号% (2)
((2!L(2b)#(2C)・・・〕はAND回路
、(3)は各ビンのうち同時にいくつがドライブされた
かを検出する加算器、(4)はドライブされているピン
数を電圧に変換するディジタル・アナログ変換−1(5
)はドライブされたビン数の変換された電圧を基準人力
とし、この基準−と各ワイヤビンに対応するソレノイド
(67((6Ji) 。In the same figure, Kb is (11((1aL(lb), (1')・
・) is the input signal % to drive each bin (2)
((2!L(2b)#(2C)...) is an AND circuit, (3) is an adder that detects how many of each bin are driven at the same time, and (4) is the number of pins being driven. Digital to analog conversion-1 (5
) takes the converted voltage of the driven bin number as the reference human power, and the solenoid (67 ((6Ji)) corresponding to this reference and each wire bin.
(6b)、(6C)・・・〕に流れる電流の騙和櫨とを
比較するための比較器、(7)は各ソレノイド(6a)
t(6bL(6C)・・・Kmれる電−の総和を螺圧に
変換するための抵抗器、(g) ((sa) e (8
b) * C8c> ・)はドライブトランジスタ、(
91Fiドライブ亀離である。・鵡2図は本弛#40協
の実施例を示す回路図であり、(in ((IOJ)
e (ム@)A1(Jc)−)−、a倫−路、Oυ((
11a >(oh) 、 (uc) ・・・)は、ドラ
イブトランジスタ(8a)。(6b), (6C)...] is a comparator for comparing the current flowing through the solenoids (6a), (7) is for each solenoid (6a)
t(6bL(6C)...Km Resistor for converting the sum of electric current into screw pressure, (g) ((sa) e (8
b) *C8c> ・) is the drive transistor, (
91Fi Drive Kamiri.・Figure 2 is a circuit diagram showing an example of this #40 association, (in ((IOJ)
e (Mu@)A1(Jc)-)-, arun-ro, Oυ((
11a>(oh), (uc)...) is a drive transistor (8a).
(8a))、(8C)・・・をONするためのバイアス
抵抗器、0は同時に幾つのソレノイドがドライブされて
いるかをトランジスタ(8a) 、 (8b) # (
8C)・・・のペース電圧の酩和で検知するための抵抗
W、(tlは前記ベース′#4ttltの電源、Iは差
励瑠轍器であり、Uωは引込みダイオードである。その
他は第1図と同じであるO
鴫3図は前ml第1図および記2図の動作をタイミング
図で示したものでμQ1ニドライブ入力波形、俵0は各
ソレノイドの電流波形、uIl!lはドライブトランジ
スタ(8a) * (8b) * (8c)・・・の各
ベース1を流涙形である。Bias resistor to turn on (8a)), (8C)..., 0 indicates how many solenoids are being driven at the same time transistors (8a), (8b) # (
8C) Resistor W for detection by the sum of the pace voltages, (tl is the power supply of the base '#4ttlt, I is the differential excitation rutter, Uω is the pull-in diode, etc. Figure 3 is the same as Figure 1. Figure 3 is a timing diagram showing the operation of Figures 1 and 2. μQ1 drive input waveform, Tawara 0 is the current waveform of each solenoid, and uIl!l is the drive Each base 1 of the transistors (8a) * (8b) * (8c)... is in the shape of a teardrop.
次に第1図の動作を説明する。入力にドライブ備考が加
えられると、”ANL)回路(2)の各一方の入力会よ
、ソレノイド電流が流れていないので“l”レベルにな
っている。値って入力信号に対応してトランジスタ(8
)のいずれか又は仮載−がONI、てソレノイド(6)
鴫電流がほれる。Cの′I4流はすべて抵抗器())に
はれるため、その両端O′鴫螺圧調べることで作動中の
ソレノイドの′IIILdL1iiの総和を検出するこ
とができる。−万、入力信号は加算器(3)とディジタ
ル・アナログ変換器(4)で同時に入力した入力信号の
数が電圧値に変換される。例えば2つの入力があったと
きの電圧は1′)Oとき0倍の電圧があるようになって
いる。従ってM紀変換された基準電圧と前記O抵抗@(
7)の両端の電圧とを比較−(−ると、入力がいくつあ
っても各ソレノイド(6a) 。Next, the operation shown in FIG. 1 will be explained. When a drive note is added to the input, each input of the "ANL" circuit (2) is at the "L" level because no solenoid current is flowing. (8
) or temporary mounting is ONI, solenoid (6)
The electric current is flowing. Since all of the 'I4 current of C enters the resistor ()), the sum of 'IIILdL1ii of the operating solenoid can be detected by checking the O' screw pressure at both ends thereof. -10,000 input signals are converted into voltage values by the adder (3) and the digital-to-analog converter (4), in which the number of input signals input simultaneously is converted into a voltage value. For example, when there are two inputs, the voltage is 1')0, which is 0 times the voltage. Therefore, the M-era converted reference voltage and the O resistance @(
7) Compare the voltage across each solenoid (6a).
(@bL(6C)・・・に定まった値の11L流が流れ
たとき1ζ比較器(5)の出力が得られる。この比較器
(5)の出力Fiυ山ゲート(5)のそれぞれを頬止す
る方向に−くのでトランジスタ(7a) # (7b)
# (7C)−・・は全@OFFとなり、各ソレノイ
ドには電流が流れな(なる・帰Jli製回路であるので
入力信号がある間、前記O系でON 、 OFFを繰返
し、Jii3kAにみられるように、ソレノイドwaF
1目的とするt[に抑えられる。(When a 11L flow with a predetermined value flows through @bL(6C)..., the output of the 1ζ comparator (5) is obtained.The output of this comparator (5) is Transistor (7a) # (7b)
# (7C) -... is all @ OFF, and no current flows through each solenoid (Nara) Since it is a Jli circuit, while there is an input signal, the O system repeats ON and OFF, and the current flows to Jii 3kA. Solenoid waF
1 target t[.
譲2図に於てもそC動作社全く同じである。坤ち、トラ
ンジスタ(8a) # (8b) e (sc)−・・
のベースwLDttI41限抵抗(lla ) 、 (
nb ) 、 (uc )−o共通接続11に全体に影
醤を与えないago小抵抗輪を接続し、これに妬生する
電圧を入力した増III&@α尋で入力信号の本数を検
知する。更K ANDゲートの代りにダイオードで各ト
ランジスタ(8”)s(8b)−(8c)・・・のベー
スをOFF方向に引込むようにしたものである。The operation in Figure 2 is exactly the same. Go ahead, transistor (8a) # (8b) e (sc) ---
The base of wLDttI41 limiting resistor (lla), (
nb), (uc)-o An AGO small resistance ring that does not affect the whole is connected to the common connection 11, and the number of input signals is detected by the intensifier III&@αhiro to which the voltage generated is input. Furthermore, instead of the AND gate, diodes are used to pull the bases of the transistors (8"), s (8b), (8c), . . . in the OFF direction.
本発鳴は以上のようになるものであって、1)帰慮型の
回路のため安定度がよい、ii)ハードウェアが小さ・
くできる、ll)1g回路が簡単になる、等の効果が得
られるものである。This generation has the following advantages: 1) It has good stability because it is a consequential circuit, ii) The hardware is small.
The following effects can be obtained: 1) the 1g circuit can be simplified;
JIIImは本発明〇一実施例を示す回路図、[I2図
は本発明の弛O実施例を示す回路図、菖3図は纂門図及
び嬉2図の動作タイミング図である。
ta、ib、tc・・弓ドライブ入力信号、5:比較器
、
6a、6b、6c・・・:ソレノイド、(3,4,5,
7) :基準値設定回路、(5,7,11,12,14
,ii) :基準値設定−路。
代理人 弁通士 井 上 −男JIIIm is a circuit diagram showing an embodiment of the present invention. [I2 is a circuit diagram showing an embodiment of the present invention. Diagram 3 is an operation timing diagram of the general diagram and the second diagram. ta, ib, tc... Bow drive input signal, 5: Comparator, 6a, 6b, 6c...: Solenoid, (3, 4, 5,
7) : Reference value setting circuit, (5, 7, 11, 12, 14
, ii): Reference value setting-road. Agent Bentsu Attorney Inoue - Male
Claims (1)
トワイヤを叩打して印字するワイヤドツトプリントヘッ
ドにおいて、複数のソレノイドと、ζOソレノイドを駆
動制御する複数のスイッチ素子と、前記ソレノイドを駆
動するために各々入力されたドライブ人力信号の総数に
相当する1圧を得るillの手段と、駆動されたソレノ
イドに流れた電流の総−に相当する電圧を基準電圧とし
て得る82の手段と、前記ill及び嬉2の手段で得た
電圧を比較し、その結果を出力する比較器と、−記スイ
ッチ素子に接続され、前記ドライブ入力信号を入力する
とともに前記比較器の出力をゲート制御信号として入力
し、#III記スイッチ素子の動作を111#するゲー
ト手段とを具備することを籍倣とするプリントヘッドl
II制御装置。A wire dot print head that prints by striking a flint wire by suctioning an armature with a solenoid includes a plurality of solenoids, a plurality of switch elements for driving and controlling a ζO solenoid, and a plurality of switch elements each having an input to drive the solenoid. The means of ill to obtain one voltage corresponding to the total number of drive human power signals, the means of 82 to obtain a voltage corresponding to the total of the current flowing through the driven solenoids as a reference voltage, and the means of ill and 2. a comparator that compares the obtained voltages and outputs the result; and a switch element connected to #III, which receives the drive input signal and inputs the output of the comparator as a gate control signal; The print head is equipped with a gate means for controlling the operation of 111#.
II control device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8249282A JPS58199169A (en) | 1982-05-18 | 1982-05-18 | Apparatus for controlling print head |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8249282A JPS58199169A (en) | 1982-05-18 | 1982-05-18 | Apparatus for controlling print head |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58199169A true JPS58199169A (en) | 1983-11-19 |
Family
ID=13775986
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8249282A Pending JPS58199169A (en) | 1982-05-18 | 1982-05-18 | Apparatus for controlling print head |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58199169A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4813802A (en) * | 1986-09-04 | 1989-03-21 | Alcatel Business Systems Ltd. | Device for verifying if thermal printer is operating correctly |
-
1982
- 1982-05-18 JP JP8249282A patent/JPS58199169A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4813802A (en) * | 1986-09-04 | 1989-03-21 | Alcatel Business Systems Ltd. | Device for verifying if thermal printer is operating correctly |
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