JPS58197877A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a highly integrated, high performance, bipolar type, integrated circuit, by reducing intervals between electrodes such as a collector, an emitter, and a base, thereby reducing parasitic resistance of Rsc and the like of a transistor. CONSTITUTION:An N<+> type embedded region 2 is formed in a P type semiconductor substrate 1. An N type epitaxial layer 3 is formed on the region 2. By utilizing an etched film 13, ion implantation of boron, selective removal of a silicon layer, and selective oxidation are performed, and a thick oxide film 4 and a P type channel stopper 5 are formed. After a resist film 14 is removed, the etched film 13 is utilized and the selective oxidation is performed so as to form an oxide film 16. The etched film 13 is selectively removed, and a N type phosphorus diffused region 6 is formed. With the resist 14 as a mask, the etched film 13 is selectively removed. Boron and arsenic ions are implanted through the window made by said etching, and a base region 7 and an emitter region 8 are formed. A platinum silicide layer 9 is formed at the contact parts of a collector, an emitter, a base, and a Shottky barrier. Then a Ti-W layer 11 and an aluminum layer 12 are formed and the device is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bipolar semiconductor integrated circuit.

FIG. 1 shows a typical bipolar NPN transistor with a Schottky clamped between the pace and the collector. In such a transistor, the collector, base, and emitter are formed using separate photoresist processes, and the base and Schottky contacts are formed using separate photoresist processes.

Therefore, a design margin of 2 to 3 microns is required between each process. Therefore, a considerable distance is required between the collector and emitter electrodes and between the emitter and base ta. For this reason, it is not possible to improve the degree of integration in the direction parallel to the collector, emitter, and pace of the transistor (hereinafter referred to as the vertical direction). This also causes the collector-emitter resistance (hereinafter referred to as Rs).

This also makes it impossible to improve the degree of integration in the perpendicular direction (hereinafter referred to as the lateral direction) along with the collector, emitter, and base of the transistor. Inevitably, parasitic violets such as the capacitance between the base and collector of the transistor cannot be reduced, which becomes a major obstacle to achieving higher speeds or lower power.

The purpose of the present invention is to improve the vertical integration of transistors by reducing the distance between each electrode such as the collector, emitter, and paste.
The objective is to reduce the parasitic resistance of transistors and improve the lateral integration of transistors, thereby realizing a highly integrated and high-performance bipolar integrated circuit.

The basic number of tanks of the present invention to achieve the above object is as follows.

The semiconductor substrate of the first conductivity type and the collector region of the second conductivity type (
In some cases, the collector region has multiple concentration regions. )
and a first conductivity type emitter region formed from the same window surrounded by a dielectric and a 24% type emitter region, and an #s dielectric formed on the silicon surface between the emitter contact and the base contact. , is provided with a head of wJl conductivity type formed directly under the dielectric material of the above-described first conductivity type base region so as to be in contact with the base region. There are cases where the contact KM end of the first conductivity type region directly under the dielectric material is used, and where the metal is terminated in the first conductivity type region for pace ohmic contact.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings, regarding an NPN and key clamp transistor using an isoplanar as in FIG. Figure 2 (as shown in at.
An n-type buried region 2 is formed in a P-type semiconductor substrate 1, an nM epitaxial layer 3 is formed thereon, and a nitride layer 11!41 is formed.
3, boron ion implantation, selective removal and selective oxidation of the silicon layer are performed to form thick oxide a4 and P-type channel horns-5. Next, as shown in FIG. 2 (bl), after selectively removing the TERRA film 13, a resist 14 is formed on the entire surface.Next, as shown in FIG. ) 14 and nitride 13 by implanting boron ions into them to form a P-type region 15.

Next, as shown in FIG. 2(d), after removing the resist 14, selective oxidation is performed using the terra film 13 to form oxides 11116. Next, as shown in Figure 2 (el K), the TERRA film 13
is selectively removed to form an n-type phosphorus-diffused i-region 6. At this time, since phosphorus has a larger diffusion coefficient than boron, the collector region of No. 6 is deep and the P-type region of No. 15 is not deep-rooted. Next, after forming a resist 14 as shown in FIG. 2 (fl), it is selectively removed. Next, as shown in FIG. Then, boron and arsenic ions are implanted through this removed window to form the pace region 7 and the emitter region 8.
As shown in FIG. 2(h),
Then, as shown in FIG.
As shown in Figure DJ, 11 Ti-W layers and 12 aluminum layers are formed to complete the process.

The effects of the present invention will be shown below.

As is clear from the examples, the pace and the emitter were formed from the same window, and the diffusion region below the selective oxidation waist was formed in Fig. 2 (a
Since 15 of t~(j) is used, when the accuracy of the turning process is ±2μ, it is possible to set the pitch and emitter, and between the emitter and collector valley contacts to 4μv4K. is less than 3 in the case of Fig. 1. Therefore, since the length of the transistor can be shortened, the Rso of the transistor and the Schottky series resistance can also be lowered. The direction also means that it can be done with a small shape.

[Brief explanation of drawings]

FIG. 1 shows a cross-sectional view of an npn (npn) run sister with a Schottky clamped between the pace and the collector. A so-called isoplanar is used, with platinum silicide for the electrodes and aluminum and Ti- to prevent aluminum from entering the wiring.
W is used. FIGS. 2(al) to 2(j) show an embodiment according to the present invention, which is similar to that shown in FIG.
, is a cross-sectional view showing the procedure for realizing Ti-W and M wiring. In the case of helmet, 1... P-type cow conductor base, 2...
-...n+ type buried region 3...n type epi region,
4...Oxide film, 5...P type channel block -16...1 type collector region, 7...
...P-type base region. 80911. n-type emitter region, 9...Platinum silicide, 10...Oxide film, 11...Ti
-W layer, 32... aluminum region, 13... nitride Ths 14... photoresist, 15...
...P-type region, 16...isthmus experience. #-2 Figure (C) 2nd closed (e) Fist 2 TI (fn' Figure 2 (h)' l Figure 2 (i) / 2nd closed <j> 〒

Claims (1)

[Claims] A semiconductor substrate of a first conductivity type, a collector region of a second conductivity type, a base of a first conductivity type and an emitter steel region of a second conductivity type formed in the silicon region through the same window, an emitter contact and a base contact or a paste. A dielectric formed on the silicon surface between the Schottky contacts,
A semiconductor integrated circuit comprising a region of a fourteenth conductivity type formed directly under a dielectric between the emitter contact and the base contact so as to be in contact with the space region of the first conductivity type.