JPS58194547U - Muting circuit - Google Patents
Muting circuitInfo
- Publication number
- JPS58194547U JPS58194547U JP9018982U JP9018982U JPS58194547U JP S58194547 U JPS58194547 U JP S58194547U JP 9018982 U JP9018982 U JP 9018982U JP 9018982 U JP9018982 U JP 9018982U JP S58194547 U JPS58194547 U JP S58194547U
- Authority
- JP
- Japan
- Prior art keywords
- muting
- circuit
- muting circuit
- power switch
- muting element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Noise Elimination (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のミューティング回路の一例を示す回路図
、第２図は本考案によるミューティング回路の一実施例
を示す回路図、第３図は本考案によるミューゲインク１
回路の他の実施例を示す回路図、第４−は本考案による
ミューティング回路のさらに他の実施例を示す回路図、
第５図は本考案によるミューティング回路のさらに他の
実施例を示す回路図である。
２・・・・・・Ｗスイッチ、３・・・・・・コンデンサ
、４・・・・・・抵抗、７五・・・トランジスタ、１２
・・・・・・ツェナーダイオード。Fig. 1 is a circuit diagram showing an example of a conventional muting circuit, Fig. 2 is a circuit diagram showing an embodiment of a muting circuit according to the present invention, and Fig. 3 is a circuit diagram showing an example of a muting circuit according to the present invention.
A circuit diagram showing another embodiment of the circuit, No. 4- is a circuit diagram showing still another embodiment of the muting circuit according to the present invention,
FIG. 5 is a circuit diagram showing still another embodiment of the muting circuit according to the present invention. 2...W switch, 3...Capacitor, 4...Resistor, 75...Transistor, 12
...Zener diode.
Claims (1)
接続され、該電源スイツチ投入後所定期間前記ミューテ
ィング素子を動作させることによって信号伝送路を遮断
せしめるミューティング回路において、前記微分回路と
ミューティング素子との間にツェナーダイオードを設け
、電源電圧の変動にともない前記ミューティング素子が
誤動作することを防止することができるように構成した
ことを特徴とするミー−ティング回路。A muting circuit in which a muting element is connected to a power switch via a differentiating circuit, and a signal transmission path is cut off by operating the muting element for a predetermined period after the power switch is turned on, wherein the differentiating circuit and the muting element are connected to each other. 1. A meeting circuit characterized in that a Zener diode is provided between the two terminals to prevent the muting element from malfunctioning due to fluctuations in power supply voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9018982U JPS58194547U (en) | 1982-06-18 | 1982-06-18 | Muting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9018982U JPS58194547U (en) | 1982-06-18 | 1982-06-18 | Muting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58194547U true JPS58194547U (en) | 1983-12-24 |
| JPS6316182Y2 JPS6316182Y2 (en) | 1988-05-09 |
Family
ID=30098731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9018982U Granted JPS58194547U (en) | 1982-06-18 | 1982-06-18 | Muting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58194547U (en) |
-
1982
- 1982-06-18 JP JP9018982U patent/JPS58194547U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6316182Y2 (en) | 1988-05-09 |
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