JPS58192122A - Terminal controlling device - Google Patents

Terminal controlling device

Info

Publication number
JPS58192122A
JPS58192122A JP7521882A JP7521882A JPS58192122A JP S58192122 A JPS58192122 A JP S58192122A JP 7521882 A JP7521882 A JP 7521882A JP 7521882 A JP7521882 A JP 7521882A JP S58192122 A JPS58192122 A JP S58192122A
Authority
JP
Japan
Prior art keywords
pol
processor
terminal device
occurrence
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7521882A
Other languages
Japanese (ja)
Inventor
Hideo Suzuki
英夫 鈴木
Yusuke Hino
裕介 日野
Kazutoshi Shimizu
清水 一俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7521882A priority Critical patent/JPS58192122A/en
Publication of JPS58192122A publication Critical patent/JPS58192122A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt

Abstract

PURPOSE:To decrease the load of a job processing processor, by performing the detection of interruption source generation of a terminal device and data READ/ WRITE processing with an AUTO-POLLING controlling processor. CONSTITUTION:The job processing processor 2 sets A-POL information on an A-POL controlling table 6 and gives an A-POL processing start command to the A-POL controlling processor 3. The processor 3 gives a command for the start of A-POL to an A-POL controlling circuit 4. The controlling circuit 4 transmits the A-POL to a terminal device 8. When a response controlling circuit 10 receives the A-POL, the reception is informed to a processor 9. The processor 9 instructs the transfer of data of an A-POL response storing memory 12 to the response controlling circuit 10 to perform the data transfer. When the POL type requires data READ or WRITE, the processor 3 outputs a READ/WRITE issusing command to the A-POL controlling circuit 4 and when the response is received from the terminal, whether or not the processing of the commanded POL type is finished is discriminated.

Description

【発明の詳細な説明】 発明の対象 本発明は端末制御装置に1糸り、複数の端末の’/i、
IJ込み要因発生検出なA−)’0L(AUTO−PO
LLING)により検出し、業務処理と並行して端末装
置の割込み要因発生検出を行なう装置叡に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention provides a terminal control device for controlling a plurality of terminals'/i,
IJ included factor occurrence detection A-)'0L (AUTO-PO
LLING) and detects the occurrence of an interrupt factor in a terminal device in parallel with business processing.

従来技術 第1図を用い従来技術を説明する。Conventional technology The prior art will be explained using FIG.

端末制御装置1内の業務処理プロセッサ2は、処理がl
l)LE状態になった時、データ線9を介し、コマンド
制御回路3に)LEAI)コマンド発行指示を出し、デ
ータ線10を介し端末装置t 5に1tjJA1)コマ
ンドを発行する。
The business processing processor 2 in the terminal control device 1 performs processing l.
l) When the LE state is entered, a)LEAI) command issue instruction is issued to the command control circuit 3 via the data line 9, and a 1tjJA1) command is issued to the terminal device t5 via the data line 10.

端末装置内プロセッサ6は、ステータス情報格納メモリ
8に、データ線11を介し割込要因発生の有無、割込み
要因発生時に&ま割込み要1刈を格納しておき、当該エ
リア絖み出しのルEAI)コマンドを受ければ、データ
線12を介し応答市制御回路7にデータ転送指示を出し
、データ線13を介し、ステータス情報をデータ線10
を介し転。
The processor 6 in the terminal device stores in the status information storage memory 8 via the data line 11 whether or not an interrupt factor has occurred, and when an interrupt factor has occurred, an interrupt is required. ) When a command is received, a data transfer instruction is issued to the response city control circuit 7 via the data line 12, and the status information is transferred via the data line 13 to the data line 10.
Transferred through.

送する。send

業務処理プロセッサ2は、コマンド制御装置3からの、
データ線14を介しデータ格納メモ1ノ4に端末のステ
ータス情報を格納児了した事を受け、データ線15を介
しステータス情報を見、判定し割込み要因発生であれば
、割込み要因を解析し処理を開始する。割込み要因カー
発生′シーこいなければ、データ線16.17・・・・
・・を介し順次同様に他の端末装置の割込み要因発生の
検出を行なう。
The business processing processor 2 receives the command from the command control device 3.
When the status information of the terminal is stored in the data storage memo 1 and 4 via the data line 14, the status information is checked and determined via the data line 15, and if an interrupt factor has occurred, the interrupt factor is analyzed and processed. Start. If no interrupt factor occurs, data lines 16, 17...
. . , the occurrence of interrupt factors in other terminal devices is detected in the same way.

従来技術の問題点としては、業務処理プロセッサ2で、
条dの処理及びシー末装置の割込み要因発生の検出をF
LEAl)コマンドを発行し行なっているので、業務処
理を行なっている時&上端末装置の割込み要因発生を検
出できない。
The problem with the conventional technology is that the business processing processor 2
F
LEAl) command is issued and executed, it is not possible to detect the occurrence of an interrupt factor in the upper terminal device during business processing.

また、端末装置−白筋にREAI)コマンドを発行し、
割込み要因発生を判定しなければならず、割込みが発生
していない時も、端末装置のステータス情報のREAl
)を行ない業務処理プロセッサが判定を行なわなければ
ならない。この為、業務処理プロセッサへの負荷が大き
くなり、業務処理の効率が悪い。
Also, issue the REAI) command to the terminal device - white line,
It is necessary to determine the occurrence of an interrupt cause, and even when no interrupt has occurred, the status information of the terminal device is
) and the business processing processor must make the determination. For this reason, the load on the business processing processor increases, resulting in poor business processing efficiency.

発明の目的 この発明の目的とするところは、上記の如き従来の間m
4を除去するものであり、A−)’01・制御プロセッ
サで、端末装置ρの割込み要因発生検出及び、データR
HA IJ/WRI T );処理を行なうことにより
業務処理プロセッサの負荷の軽減、業務処理と端末装置
の割込み要因発生検出との並行処理を可能とするもので
ある。
OBJECT OF THE INVENTION The object of the present invention is to solve the conventional problems as described above.
A-)'01・The control processor detects the occurrence of an interrupt factor in the terminal device ρ and processes the data R.
HA IJ/WRIT); By performing this processing, the load on the business processing processor can be reduced, and business processing and interrupt factor occurrence detection on the terminal device can be processed in parallel.

従来は、業務処理プロセッサで業務の処理及びREAI
)コマンドによる端末装置の割込み要因発生検出を行な
っているので、業務処理中に割込み要因発生検出はでき
ず、又、割込み要因が発生していない時も端末装置のス
テータス情報をREADシ、業務処理プロセッサが判定
を行なわなければならず、業務処理プロセッサへの負荷
が大きくなり、業務処理の効率も悪い。
Conventionally, business processing and REAI were performed using a business processing processor.
) Since the occurrence of an interrupt factor on the terminal device is detected using commands, it is not possible to detect the occurrence of an interrupt factor during business processing, and even when no interrupt factor has occurred, the status information of the terminal device can be read and used for business processing. The processor must make the determination, which increases the load on the business processing processor and reduces the efficiency of business processing.

故に、A −P (J L ?B11 #プロセッサで
、端末装置の割込み要因発生検出が、業務処理プロセッ
サの指示によるl) OL 棹によるデータのREAL
) 。
Therefore, A-P (J L ?B11 #The processor detects the occurrence of an interrupt factor in the terminal device according to the instruction from the business processing processor).
).

WRITE処理を行なう事により業務処理プロセンサの
負荷が軽減され、業務処理の効率向上が計れ、又、業務
処理プロセッサによる業務処理と端末装置の割込み要因
発生検出との並行処理をe=J’能とするものである。
By performing WRITE processing, the load on the business processing processor is reduced, the efficiency of business processing can be improved, and the parallel processing of business processing by the business processor and the detection of the occurrence of an interrupt factor on the terminal device can be performed with e=J' function. It is something to do.

発明の実施例 次に本発明の実施EFIJにつき、図面を用いて詳細に
説明する。              飄実施例の構
成 第2図は、本発明の一実施例である端末制御装置のブロ
ック図を示すものである。
Embodiments of the Invention Next, implementation EFIJ of the present invention will be explained in detail with reference to the drawings. Configuration of Embodiment FIG. 2 shows a block diagram of a terminal control device which is an embodiment of the present invention.

A−POL制岬制御テーブル6データ格納メモリ7から
成るメモリ5、業務処理プロセッサ2、A−1’OL?
!IJ御プロセツサ3、A−POL制御回路4(コマン
ド発行を1すむ)を内蔵する端末制御装置1及び、端末
制御プロセッサ9、又、A−POL応答格旬ノモリ12
とステータス情報格納メモリ13から成るメモリ11、
応答制御即回路10を内威する端末装置8から構成され
る。
Memory 5 consisting of A-POL system control table 6 data storage memory 7, business processing processor 2, A-1'OL?
! A terminal control device 1 incorporating an IJ control processor 3, an A-POL control circuit 4 (which issues commands once), a terminal control processor 9, and an A-POL response memory 12
and a status information storage memory 13.
It consists of a terminal device 8 that controls a response control circuit 10.

実施例の動作 ゛端本制御装置It1内の業務処理プロセッサ2は、メ
モリ5内のA−LPOL制御テーブル6(端末装置対応
のA−POL制向悄@i:A−POL種、A−POLの
起動/停止指令:を格納)にA−POL+に報をデータ
線14を介しセットし、データ線15を介しA−POL
制御プロセッサ3にA−POL処理開始指示を出す。A
−PUL制御制御セロセンサ3−タ線16を介しA−、
t’OL制御テーブルを見、A−POL開始指示の有る
端末装置にA−POLを開始させる為、データ線17を
介しA−POL制御回路4にA−P(JL開始を指令す
る。A−POIJIJ御回路4はデータ#!19を介し
A−POLを端末装[8に送出する。
Operation of the embodiment The business processing processor 2 in the main control device It1 reads the A-LPOL control table 6 in the memory 5 (A-POL control table corresponding to the terminal device @i: A-POL type, A-POL type, A start/stop command: is set to A-POL+ via data line 14, and A-POL+ is set via data line 15.
An instruction to start A-POL processing is issued to the control processor 3. A
-PUL control control cello sensor 3-A- via the data wire 16;
Looking at the t'OL control table, in order to start A-POL to the terminal device that has the A-POL start instruction, the A-POL control circuit 4 is instructed to start A-P (JL) via the data line 17.A- POIJIJ control circuit 4 sends A-POL to terminal device [8 via data #!19.

端末内プロセッサ9は、割込み要因発生時、割込み要因
発生をA−POL応答賂納メモリ12に、割込み要因を
ステータス格納メモリ13にデータ線21を介し格納し
ておく。割込みが発生していなければ、割込み要因無し
の情報7 A−1’OL応答格納メモリ12に格納して
おく。
When an interrupt factor occurs, the in-terminal processor 9 stores the interrupt factor occurrence in the A-POL response payment memory 12 and the interrupt factor in the status storage memory 13 via the data line 21. If no interrupt has occurred, information 7 A-1' that indicates no interrupt cause is stored in the OL response storage memory 12.

端末装置内のj、6答制御回路10は、A−1’OLを
受けるとデータ線20を介しプロセッサ9に八−POL
E信を知らせる。プロセッサ9は端末内メモリ11内の
A−POL応答格納メモリ12のデータの転送を応答制
御回路10にデータ縁20を介して指令する事により、
データ縁19を介し転送する。また、割込み要因発生時
は、ステータス情報格納エリア13のデータを付加する
事もできる。
When the j, 6 answer control circuit 10 in the terminal device receives A-1'OL, it sends 8-POL to the processor 9 via the data line 20.
Notify me of e-mail. The processor 9 instructs the response control circuit 10 to transfer data from the A-POL response storage memory 12 in the terminal memory 11 via the data edge 20.
The data is transferred via the edge 19. Furthermore, when an interrupt factor occurs, data in the status information storage area 13 can be added.

端末制御装置1内A−POL制御回路4は、A−POL
への応答を受けるとデータ線18を介し、ステータス情
報格納メモリ7に応答を格納し、データ縁17を介しA
−POL制呻プロセッサ6に応答受信を知らせる。
The A-POL control circuit 4 in the terminal control device 1 is an A-POL
When a response to A is received, the response is stored in the status information storage memory 7 via the data line 18, and is sent to
- Notify the POL control processor 6 of the receipt of the response.

A−)’OL制両グロセノサ3はデータ線16を介し、
ステータス情報格納メモリ7内のA−POL応答を見、
割込み要因発生状況を判定し、割込み要因発生でなけれ
ば、A−POL制御テーブル6を見、次のA−POL起
動要求の端末装置を調べPOL起動要求のセットされて
いる端末装置に、A −P U Lを発行し端末装置の
割込み要求)ら生の検出をくり返す。
A-)'OL system both Grossenosa 3 is connected via data line 16,
Look at the A-POL response in the status information storage memory 7,
The interrupt factor occurrence status is determined, and if no interrupt factor has occurred, the A-POL control table 6 is checked, the terminal device for the next A-POL activation request is checked, and the A-POL activation request is sent to the terminal device for which the POL activation request is set. PUL is issued and raw detection is repeated from the terminal device's interrupt request).

割込み要因発生であれば、A −P (J Ti fb
lJ 釧テーブル6のPOL 44を見、業務処理プロ
セッサ2への通知が可能かを判足し、可能であればA、
−POL制御テーブル6内の占該端末装置のA−PUL
情報をクリア(POL停止等に)しデータ線15を介し
業務処理プロセッサに割込む。
If an interrupt factor occurs, A -P (J Ti fb
lJ Look at the POL 44 of the Kushi table 6, determine whether it is possible to notify the business processing processor 2, and if possible, select A.
- A-PUL of the occupied terminal device in the POL control table 6
Clears the information (stops POL, etc.) and interrupts the business processing processor via the data line 15.

データのREAL)あるいはW l(+ T F2が必
要なPOL柚であれば、A−POI、制御プロセッサ3
はデータ縁17を介し、A−POLtHIJ商1回路に
1打]A1)/WRITEコマンド発行指令を出し、端
末からの応答受信時、指示されたi’ o L(=の処
理完了かを判定し、処理完了であればA−POL制御テ
ーブル6をクリアしデータ縁15を少し業務プロセッサ
に割込む。
data REAL) or W l (+ T F2 is required, A-POI, control processor 3
issues a command to issue the A-POLtHIJ quotient 1 circuit]A1)/WRITE command via the data edge 17, and upon receiving a response from the terminal, determines whether the instructed i' o L(= processing is complete). If the processing is completed, the A-POL control table 6 is cleared and the data edge 15 is slightly interrupted to the business processor.

業務処理プロセッサは、業務処理を行なう。The business processing processor performs business processing.

A−4’tJL制叫グロセツサ6は、A−POI、制御
テーブル6を見、次のA−P(JL起@妥求端末装置を
調ベデータ線26.24・・・・・・を介し端末装置の
古11込み発生検出を順次くり返す。
The A-4'tJL scream control glosser 6 looks at the A-POI and the control table 6, and checks the next A-P (JL start @ compromise terminal device). Detection of occurrence of old 11 in the device is repeated one after another.

業務処理プロセッサ2は、端末装置の割込み。The business processing processor 2 handles interrupts from terminal devices.

要因発生検出の必要が起きた時に、A −P OL制御
テーブル6内の該当端末装置A−POL惟報悄納エリア
に、業務に有効な205種をセットし、割込み発生検出
をA−POL制御プロセッサ6に指令する。
When it is necessary to detect the occurrence of a factor, set 205 types that are effective for business in the corresponding terminal device A-POL notification area in the A-POL control table 6, and perform A-POL control to detect the occurrence of an interrupt. command to the processor 6.

発明の効果 以上述べた如き構成であるので、本発明にあっては次の
如き効果を得る事ができる。
Effects of the Invention With the configuration as described above, the present invention can provide the following effects.

■ A−POL制御プロセッサで、端末装置の割込み要
因発生検出及び、業務処理プロセッサの指示によるPu
L 棟によって、データの+v EA l)、W)tI
i″E処理を行なう事により業務処理プロセッサの負荷
が軽減される。又、業務処理プロセッサによる業務処理
は、端末装置の割込み要因発生検出と並行して行なう事
が出来る。
■ The A-POL control processor detects the occurrence of an interrupt factor in the terminal device and executes the Pu
+v EA l), W) tI of data by L building
By performing the i''E process, the load on the business processor is reduced. Furthermore, the business process by the business processor can be performed in parallel with the detection of the occurrence of an interrupt factor in the terminal device.

■ 多棟のA−POLを用意する事により、業務処理の
効率UPが可能である。
■ By preparing multiple A-POLs, it is possible to improve the efficiency of business processing.

以下にA−POL柚の一例を記す。An example of A-POL Yuzu is described below.

o ATTENTION POLLING端末装置の割
込み要因発生を監視(要因検出時、A−POL制御グロ
セノサは業務処理プロセッサに通知) 0 )tEAl)Y POLLING 端末装置の割込み要因発生を監視(端末装置のTiME
−OU’l”検出時は割込まずに、端末装置からの応答
受信時業務処理プロセッサに通知) ONOT BUSY POLLING 端末装置のBUSY状態の解除を監視 o  iNe  POLLING キー人力装置のキー押下によるINC A’l’TENTION 発生を’n視特定のINCA
i’TI!JN’l”IC)N発生の監視も可(当g 
A −P OL ハA’rTENTIUN P(JL、
L INuによる割込み要因発生検出時、端末装置のス
テータス情報をREAL) シ、INC発生を検出する
ものである) O8)すNSE; ATTENTI(JN POLLI
NG端末装置のINITIAL  P几0 (iRAM
LOAIJ景求、5YSi”EM )tEADY状態等
、5ENSI(ATTENTION 発生を監視。特定
の5ENSEATTENTION 発生の監視も可。(
上記INCATTENTION  POLと同様ステー
タス情報を)LEADL、5ENSE発生を検出するも
のである) 0データREAI)/W[TE付加 上記A−POLで、端末装置の割込み要因検出時、端末
装置内のデータI(、EAD、端末装置へのデータVI
I’l”E処理を行なう事も可。
o ATTENTION POLLING Monitors the occurrence of an interrupt factor in the terminal device (when a factor is detected, the A-POL control grossenosa notifies the business processor) 0)tEAL) Y POLLING Monitors the occurrence of an interrupt factor in the terminal device (TiME of the terminal device
-OU'l'' is detected without interrupting, but notifies the business processor when a response is received from the terminal device) ONOT BUSY POLLING Monitors the cancellation of the terminal device's BUSY state o iNe POLLING key INC A by pressing a key on a human-powered device 'l'TENTION Specific INCA of 'n' occurrence
i'TI! It is also possible to monitor the occurrence of JN'l"IC)N.
A-POL HaA'rTENTIUN P(JL,
When the occurrence of an interrupt factor is detected by L INu, the status information of the terminal device is REAL). This is to detect the occurrence of INC) O8)
INITIAL P of NG terminal device (iRAM
LOAIJ, 5YSi"EM) Monitor the occurrence of 5ENSI (ATTENTION), such as the tEADY state. It is also possible to monitor the occurrence of a specific 5ENSEATTENTION. (
Similar to the above INCATTENTION POL, this is to detect the occurrence of status information) LEADL, 5ENSE) 0 data REAI)/W [TE addition In the above A-POL, when an interrupt factor of the terminal device is detected, the data I( , EAD, data VI to terminal device
It is also possible to perform I'l"E processing.

処理完了時業務処理プロセッサへ割込む。Interrupts the business processing processor when processing is completed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来技術のブロック図、第2図は本発明の一実
施例の端末制御装置のブロック図、第3図は本発明の同
じく端末制御装置の処理フロー図である。 1・・・端末1tilJ御装置、 2・・・業務処理プロセッサ、 3・・・A−POL制御プロセッサ、 4・・・A−POL制御回路、 5・・・メモリ、 6・・・A−POL制御テーブル、 7・・・ステータス情報格納メモリ、 8・・・端末装置、 9・・・端末制御プロセッサ、 10・・・応答制御回路、 11・・・メモリ、 12・・・A−POL応答格納メモリ、16・・・ステ
ータス情報格納メモリ、14〜24  データ巌。 代理人弁理士薄 1)利ゑ辛 、1←  2.1 才 j 膿 才 2 口 ?3 即
FIG. 1 is a block diagram of the prior art, FIG. 2 is a block diagram of a terminal control device according to an embodiment of the present invention, and FIG. 3 is a processing flow diagram of the same terminal control device of the present invention. DESCRIPTION OF SYMBOLS 1...Terminal 1tilJ control device, 2...Business processing processor, 3...A-POL control processor, 4...A-POL control circuit, 5...Memory, 6...A-POL Control table, 7... Status information storage memory, 8... Terminal device, 9... Terminal control processor, 10... Response control circuit, 11... Memory, 12... A-POL response storage Memory, 16...Status information storage memory, 14-24 Data block. Agent Patent Attorney Bo 1) Lie Shin, 1← 2.1 year old j Pusai 2 mouth? 3 Immediately

Claims (1)

【特許請求の範囲】[Claims] 1、 業務処理プロセッサがA−)’0L(AUTO−
P(JLLINlj)t+J11両テーブルに、インタ
フェース情報をセットする事により、A−)’OL制御
プロセッサはA−POL制御テーブルを見、A−POL
制御回路にA−PO,L発行を起動し端末装置の割込み
賛内発生を監祝し、割込み要因発生検出時、A−POL
iを調べ、データI) READ/VVRi i’E処
坤必要の有無を判定し、必要であれば処理を行なった後
、業務処理プロセッサに割込み、後、k−POL制岬制
御テーブル、次のA−PUL起動要求端末装置を調べて
A−POLを起動し、割込み発生構出を順次くり返す端
末制御装置に於いて、上記、業務処理プロセッサ、A−
POL制釘ン°ロセ、ソサ、A−POL隼1j#回路、
fi、−POL制御テーブルから成り、A−POL制岬
グロセンサで端末装置の割込み要因発生検出及び、兼務
処理プロセッサの指示によるデータREAD 、 WR
i TE処理を行なうことにより業務処理ゾロセッサの
負葡が軽減され、業務処理プロセッサによる業務処理は
、端末装置の割込み要因発生検出と並行して行なうこと
が出来る事を特徴とする端末制御装置。
1. The business processing processor is A-)'0L (AUTO-
By setting the interface information in both the P(JLLINlj)t+J11 tables, the A-)'OL control processor looks at the A-POL control table and
The control circuit starts issuing A-PO and L to monitor the occurrence of an interrupt from the terminal device, and when the occurrence of an interrupt factor is detected, A-POL is issued.
Check the data I) READ/VVRi i'E to determine whether processing is necessary, and if necessary, after processing, interrupt the business processing processor, and then update the k-POL control table and the next In the terminal control device that checks the A-PUL activation request terminal device, activates A-POL, and sequentially repeats the interrupt generation configuration, the above-mentioned business processing processor, A-
POL nail pin ° Rose, Sosa, A-POL Hayabusa 1j# circuit,
fi, - Consists of a POL control table, detects the occurrence of an interrupt factor in the terminal device using the A-POL control cape gloss sensor, and reads data according to instructions from the concurrent processing processor.
A terminal control device characterized in that the burden on a business processing processor is reduced by performing iTE processing, and business processing by the business processor can be performed in parallel with detection of occurrence of an interrupt factor in a terminal device.
JP7521882A 1982-05-07 1982-05-07 Terminal controlling device Pending JPS58192122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7521882A JPS58192122A (en) 1982-05-07 1982-05-07 Terminal controlling device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7521882A JPS58192122A (en) 1982-05-07 1982-05-07 Terminal controlling device

Publications (1)

Publication Number Publication Date
JPS58192122A true JPS58192122A (en) 1983-11-09

Family

ID=13569852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7521882A Pending JPS58192122A (en) 1982-05-07 1982-05-07 Terminal controlling device

Country Status (1)

Country Link
JP (1) JPS58192122A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009238001A (en) * 2008-03-27 2009-10-15 Texas Instr Japan Ltd Computer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009238001A (en) * 2008-03-27 2009-10-15 Texas Instr Japan Ltd Computer system

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