JPS5819172B2 - fine inching device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tuning device that controls an electronically tuned tuner using a phase-locked loop (hereinafter referred to as PLL), and its purpose is to offset the oscillation frequency of the reference oscillator of the PLL. An object of the present invention is to provide a fine tuning device which corrects detuning by using the above method and whose correction range is constant regardless of frequency.

In general, the advantage of a single frequency synthesizer is that it automatically and accurately creates the required frequency, but it is often detuned in television broadcasts and the like.

The reason for this is to increase the gain by detuning in weak electric field areas and bringing the video carrier to the center of the intermediate frequency band.1 To prevent ghosting caused by reflective objects, and to prevent interference with other stations such as in cable TV.

This is the case when standing waves on the antenna line degrade image quality, and in such cases, the receiver needs to have an offset function to match the transmission frequency.

The present invention provides a receiver using a PLL with an offset function, and makes the offset range (correction range) constant regardless of the height of the reception frequency.

An example thereof will be described with reference to FIG.

In FIG. 1, the output of a tuner 1 equipped with a voltage-controllable local oscillator (oscillation output of the local oscillator) is passed through a frequency divider 2 to a first programmable counter (hereinafter referred to as P-DI).
V) 3, divided by a desired frequency division ratio and inputted to a phase comparator 8. The phase comparator 8 compares the phase with a reference signal, and its output is inputted to the tuner 1. A first PLL that controls the local oscillation frequency of tuner 1 is configured.

The first P-DIV 3 passes the signal from the input switch 26 through the channel presetter 4 and converts it into a BCD code of the channel number (address of the memory 6) by the code converter 5.
The output is input to a memory 6 in which the local oscillation frequency value of the television broadcast frequency is stored in binary code for each channel, and the frequency division ratio is determined by the output of the memory 6.

The output of the memory 6 is input to the first P-DIV3 and the second P-DIV22 to determine the frequency division ratio. The output of 14 is inputted via the frequency divider 23, divided by a predetermined frequency division ratio, and inputted to the comparator 19.

Here, the output frequency of the fixed oscillator 14 is f.

The frequency division ratio of the frequency divider 23 is N23. 2nd P-DIV22
The frequency division ratio is N.

Then, the comparator 19 receives the fo signal as input N2
3.N.

will be done.

To operate the offset function, an offset signal is input from the terminal 21 to the comparator 19 via the gate circuit 18, and is also input to the up/down counter 20 while the offset signal is being input.

(Time T) An input signal is input from the comparator 19 to the up/down counter 20, and the counting direction of the up/down counter 20 (increase or decrease from a predetermined value NA) is determined by the offset signal. and its output becomes N±-foT″N23″NO.

The frequency division ratio of the third P-DIVL7 is up/down f.

is determined by the output of counter 20, and is determined by the output of counter 20.
No.

The output of the voltage controlled oscillator 11 is frequency-divided by the frequency divider 16 and then divided by the third P-DIV 17 to be outputted to the phase comparator 1.
A signal from the fixed oscillator 14 is input to the phase comparator 13 via the frequency divider 15, and the phases of the respective signals are compared.

The output of the phase comparator 13 is applied to the voltage-controlled oscillator 11 via the low-pass filter 12 to control the oscillation frequency, and the output of the voltage-controlled oscillator 11, that is, the second P L T,
The output of is added to the phase comparator 8 and serves as a reference oscillator for the first PLL.

Therefore, frequency divider 15.・1 16 frequency division ratio -, -1 voltage controlled oscillator 11N7. N1
When the second PLL is locked, assuming that the oscillation frequency of 6 is fVoc, N16 foT , fvco nini f.

(NA±□)N15 N23°N.

=A±--T N.

N N fo (A=-!-! foN, B --”ヱ)N 15
They become N15 and N23.

Next, set the frequency division ratios of frequency dividers 2 and 10 at intervals. The ball π is the local oscillation frequency of the tuner f.

Considering the first PLL lock as $0.

fO8C:N2°NO°-- 1O N-N B -□・(A±--T) N1oN.

Therefore, the local oscillation frequency N2 when no offset is applied is
N.

There is a number O ma T-°0 o'clock 7・f008-- N,.

There is A7.

Also, the frequencies that change due to offset are 2, N, and B.
T, which is a function of time T and is independent of the station channel and frequency,
There is no offset deviation between channels, and the frequency that changes due to the offset is determined by the time when the offset signal from the terminal 21 indicating whether to turn up or down is applied.

Also, if the entire loop is unlocked, the phase comparator 8
Since a phase-out signal is output and the audio and video are cut only while the lock is released by this signal, the audio and video will be cut if the lock is released during offset.

To prevent this, the offset signal and the phase out output from the phase comparator 8 are added to the gate circuit 24 so that the audio and video are not cut during offset, and if the lock is released at any other time, the lockout occurs. An output is output from terminal 25.

Note that 7 is a band switching circuit.

According to the present invention, as shown on paper, the local oscillation frequency that changes with the offset remains constant regardless of the inter-channel deviation (due to the high or low oscillation frequency), and the changing frequency range is determined by the division ratio of each frequency divider and the fixed It can be arbitrarily determined by selecting the value of the oscillation frequency of the oscillator 14.

Furthermore, since the frequency that changes due to the offset is proportional to time, it has great effects such as good operability.

[Brief explanation of drawings]

FIG. 1 is a diagram 7172 showing an embodiment according to the present invention. 1...Tuner, 2, 10, 15, 16, 23
...Frequency divider, 3, 17, 22...Programmable counter, 6...Memory, 8,
13... Phase comparator, 11... Voltage controlled oscillator, 14... Fixed oscillator, 18.24.
...Gate circuit.

Claims (1)

[Claims] 1. In a tuning device in which a local oscillator of a voltage-controllable tuner is controlled by a first phase-locked loop, a binary code corresponding to each receiving channel is input from an input device into a first programmable channel. The binary code is input to a counter to receive the desired channel, and the binary code is input to a second programmable counter to determine the division ratio, and the signal from the fixed oscillator is increased through the second programmable counter.・Input to the down counter, count with the up/down counter only when an offset signal is added, add/subtract a pre-stored constant code, and send the output to the third programmable counter. the third programmable counter and the fixed oscillator 1 phase comparator form a second phase-locked loop for controlling the voltage controlled oscillator; A fine tuning device characterized in that the reference oscillator of the first phase-locked loop is used as a reference oscillator. 2. A patent claim characterized in that the offset signal and the phase-out output of the phase comparator of the first phase-locked loop are added to a gate circuit so that the offset time phase-out signal is not sent out. The fine tuning device according to scope 1.