JPS58191588A - Encoding and decoding system in frame - Google Patents

Abstract

PURPOSE:To miniaturize the device with large scale circuit integration, by using the synchronizing sampling predictive system and the asnchronizing sampling predictive system through switching depending on the magnitude of the synchronizing frequency fluctuation in an NTSC signal and corresponding one encoder for arbitrary picture signals. CONSTITUTION:The inputted picture signal of the NTSC system is applied to an LPF2 to limit the frequency band to a prescribed value, and applied to clock generator 4 and an A/D converter 3, where the synchronizing signal is separated and the signal is converted into a digital signal. The circuit 4 generates the asynchronizing sampling clock and the sampling clock synchronizing-separated from the clock source 5 through switching by the output of a synchronizing/ asynchronizing changeover switch 6. The signal synchronized/asynchronized in this way is decoded at a clock reproducing circuit 24, a signal representing the distinction whether it is synchronizing or asynchronizing sampling is applied to a switch 26, and a signal representing the quantized representing value is applied to an adder 27. Further, the synchronized/asynchronized sampling predictive systems are switched, and one encoder is used for arbitrary picture signals.

Description

DETAILED DESCRIPTION OF THE INVENTION In order to directly predictively encode an NTSC signal as it is, the present invention switches between a prediction method for synchronous sampling and a prediction method for asynchronous sampling. The present invention relates to an intraframe encoding/decoding method that can easily realize signal encoding according to the method.

Image signal sources to be encoded range from those such as VTR outputs in which the synchronization frequency fluctuations are as high as ±11,000 ppm to those such as broadcast signals in which the synchronization frequency fluctuations are less than ±30 ppm.

Regarding the former, it is difficult to generate a sampling clock synchronized with this synchronous frequency, so asynchronous sampling has to be used.

On the other hand, regarding the latter, since synchronous sampling is possible, it is possible to encode with good image quality.

In addition, in a transmission system where intra-frame encoding and inter-frame encoding are connected in cascade, inter-frame encoding uses inter-frame correlation, so synchronous sampling is performed; It is desirable that the intraframe encoding method used be synchronous sampling.

In the conventional intra-frame encoding method, synchronous sampling and asynchronous sampling were configured as separate devices, so there was no single device that could handle any image signal source.゛Also, even if you try to configure such a device, the input NT
Since subcarrier components are superimposed on the SC signal, conventionally, when performing asynchronous sampling, a high-order measurement method (for example, the Showa 1955 IEICE, Divisional National Conference, A 70
0. Intraframe coding terminal equipment for color television)
When performing synchronous sampling, a two-dimensional prediction method that utilizes the correlation between scanning lines [for example, Transactions of the Institute of Electrical Communication Engineers, Vol. 70-B, A 12 (1977-1
2) direct DPCM encoding of NTSC color television signals), but both methods have the disadvantage that the encoding algorithms are significantly different and the equipment configuration is complicated.

The present invention was made in order to solve these drawbacks, and relates to an intraframe coding/decoding method that can be applied to both synchronous sampling and asynchronous sampling, and can simplify the device configuration. The drawings will be described in detail below.

FIG. 1 is a block diagram showing the configuration of an embodiment for explaining the present invention in detail, and l is an image input terminal 7-. 2 is a low filter, 3 is an A/D converter, 4 is a clock generation circuit, 5
is a clock source, 6 is a synchronous/asynchronous switch, 7 is a switch,
8 and 9 are subtractors, 10 is a quantizer, 11 and 14 are adders, 12 is a variable length encoding circuit, 13 is a 1 sample memory IJ, 15 is a 5 sample memory, 16 is a 565 sample memory, 17 is a transmission buffer memory, 18 is a transmission digital interface, 19 is a data output terminal, 20 is a digital transmission path, 21 is a data input terminal, 22 is a reception digital interface, 23 is a reception buffer memory, 24 is a clock recovery circuit, 25 is a variable Long code decoding circuit, 26 is a switch, 27 and 29 are adders, 28 is 1 sample memory, 30 is 5 sample memory, 31 is 565
A sample memory, 32 a D/A converter, 33 a low-pass filter, and 34 an image signal output terminal.

First, an image signal (NT8C signal) input to an image input terminal 1 is limited to a predetermined frequency band by a low-pass filter 2 and then supplied to a converter 3 and a clock generation circuit 4.

The Iv'D converter 3 converts the band-limited analog signal from the low-pass filter 2 into a digital signal.

The clock generation circuit 4 separates the synchronization signal using the output signal of the low-pass filter 2 and generates a sampling clock synchronized with this synchronization signal, or generates a sampling clock from the clock supplied from the transmission lock source 5. Generates an asynchronous sampling clock.

Here, in the case of synchronous sampling, it is 2.5xf (however, fsc
generates a sampling clock of subcarrier frequency C (wave number), and in the case of asynchronous sampling, for example, 8.9484 MHz (' = 2.5f
,. ) generates a sampling clock.

This switching between synchronous/asynchronous sampling is performed by a synchronous/asynchronous switch 6. This synchronous/asynchronous switch 6 may be a manual switch, for example, or it may automatically switch to synchronous sampling when the measurement result is within ±30 ppm, and to asynchronous sampling when the measurement result is within ±30 ppm. It is also possible to switch. In addition to switching the clock generation circuit 4, this synchronous/asynchronous switch 6 also functions as a switch 7.
It also performs switching control. Here, the switch 7 is configured to connect the A side in the case of synchronous sampling, and connect the B side in the case of asynchronous sampling.

Next, the signal digitized by the A/D converter 3 is passed to a subtracter 8 from which the predicted value supplied via the switch 7 is subtracted, and the difference value is sent to the subtracter 9 as a first-order error signal. supply

FIG. 2 is an explanatory diagram showing the phase relationship between the two human forces in the subtracter 8 shown in FIG.
and LE indicate the scanning line number, uppercase letters indicate the pixel number, and lowercase letters indicate the signal value of the pixel.

Now A/1) When the signal value X of the pixel number X is input from the converter 3 to the subtracter 8, the signal value (predicted value) of the pixel supplied via the switch 7 is h for the case and e for asynchronous sampling.

Note that here, a case is shown in which the signal value of a pixel having the same phase with the subcarrier component is used as the predicted value.

Therefore, the signal supplied from the A/b converter 3 to the subtracter 8 is 5 pixels before or 570 pixels before the signal supplied from the switch 7.
When the color is the same as the predicted value before the pixel, the output signal of the subtracter 8 no longer contains the subcarrier component\, that is, the color signal component, and consists only of the luminance signal component.

Next, the subtracter 9 performs normal DPCM encoding effective on the luminance signal.

The quantizer 10 quantizes the output of the subtracter 9, that is, the second prediction error signal, and supplies its representative value to the adder 11.
A signal representing the quantization level is supplied to the variable length encoding circuit 12.

The adder 11 adds the quantized representative value sent from the quantizer 10 to the output value of the 1-sample memory 13, and stores the result in the 1-sample memory 13. This 1-sample memory 13 compresses the stored signal to V2 and outputs it as a predicted value of the next sample, and supplies the output to the subtracter 9 and adder 11.

The output of the adder 11 is also supplied to the adder 14, and is added to the output value of the 5 sample memory 15 or 565 sample memory 16 via the switch 7, and the result is added to the output value of the 5 sample memory 15 or the 565 sample memory 16. ]6 and use it as the pre-11j value for the next sample.

Next, the variable length encoding circuit 12 assigns short codes to frequently occurring quantization levels and long codes to infrequently occurring quantization levels to the output signal of the quantizer 10. A signal representing the distinction between synchronous sampling and asynchronous sampling supplied from the clock generation circuit 4 is time-division multiplexed with the doji conversion output, for example, at the beginning of the freight.

The transmitter memory 17 smoothes the speed of the signal supplied non-uniformly from the variable length encoding circuit 12, matches the transmission lock, and outputs the signal.

The transmission digital interface 18 converts the output of the transmission buffer memory 17 into a transmission line code and sends it to the data output terminal 1.
9 to the digital transmission line 20. At this time, the transmission digital interface 18 time-division multiplexes the signal representing the sampling frequency supplied from the clock generation circuit and outputs the signal.

On the receiving side, the data input to the data input terminal 21 is converted from a transmission path code into a signal format that can be decoded by the receiving digital interface 22 and sent to the receiving terminal (
The signal is transmitted to the clock memory 23 and the clock recovery path 24.

The buffer memory 23 is the reception digital interface 2
Data supplied from 2 to 2 is temporarily stored with a fixed transmission lock, and sequentially read out in accordance with the decoding speed.

The clock recovery circuit 24 recovers a sampling clock necessary for decoding based on the signal supplied from the reception digital interface 22.

The variable length decoding circuit 25 decodes the output of the reception/reader memory 23, and supplies a signal representing the distinction between synchronous sampling and asynchronous sampling to the switch 26, and a signal representing the quantized representative value to the adder 27. do.

The adder 27 and the 1-sample memory 28 constitute a decoding loop that performs previous value prediction, and supplies the decoded value to the adder 29. The fact that the output of the 1-sample memory 28 is compressed to 1/2 means that the 1-sample memory 13 on the transmitting side
The same is true for .

Adder 29.5 sample memory 30.565 sample memory 31 and switch 26 constitute a decoding loop for the subcarrier component, and supply the decoded signal to D/A converter 32. Here, the switch 26, like the switch 7 on the transmitting side, selects the A side in the case of synchronous sampling and the B side in the case of asynchronous sampling.
Connect the sides.

1) The /A converter 32 converts the decoded digital signal into an ablog signal, removes out-of-band noise components with the low-pass filter 33, and then outputs the NTSC signal to the image signal output terminal 34.
Sending a signal 〇 or above samples the NTSC signal at approximately 2.5 fso, and
The pixel value 70 pixels before is the predicted value in the case of synchronous sampling,
The predicted value is obtained from a single pixel value when performing synchronous sampling, as well as when performing asynchronous sampling and standardization, so that the pixel value 5 pixels before is used as the predicted value in the case of asynchronous sampling. Although the example of the case has been explained, the present invention is not limited to this, and it goes without saying that the predicted value may be a signal value composed of multiple pixel values, as in the case of the high-order sub-measurement method mentioned earlier. O As described above, the present invention switches between the prediction method for synchronous sampling and the prediction method for asynchronous sampling depending on the magnitude of the synchronous frequency fluctuation in the NTSC signal, so that it can be applied to any image signal. , there is an advantage that it can be handled with one encoding device. However, since the encoding algorithm of the present invention is composed of two prediction loops, if an LSI is introduced in this part, the circuit can be easily realized by simply cascading LSIs, resulting in a small and low-cost design. It has the advantage of being electrified and economical.

[Brief explanation of the drawing]

FIG. 1 is a Norrock diagram showing the configuration of an embodiment for explaining the present invention in detail, and FIG. 2 is an explanatory diagram showing the phase relationship between the two forces in the subtracter 8 shown in FIG. l......Image input terminal, 2.33...
・・・・・・Low pass filter, 3・・・・・・・・・A/
D converter, 4......Clock generation circuit,
5......Clock source, 6...
・・・Cyclic/asynchronous switch, 7.26 ・・・・・・
・・・Switcher, 8.9 ・・・・・・・・・Subtractor, l
O......Quantizer, 11, 14.27.2
9...Adder, 12...Variable length encoding circuit, 13.28...1 sample memory, 15.30... ......5 sample memory, 16,31...565 sample memory, 17......Transmission buffer memory, 18......Transmission digital Interface 1. 19... Data output terminal, 20.
......Digital transmission line, 21...
...Data input terminal, 22...Reception digital interface, 23...Reception buffer memory, 24...Clock regeneration circuit, 25. ......Variable length code decoding circuit, 3
2...D/A converter, 34...
...Image signal output terminal f-0 ■
-1e

Claims (1)

[Claims] On the transmitting side, the NTSC color television signal (hereinafter NT
This is called an SC signal. ), the signals with small synchronous frequency fluctuations are subjected to synchronous sampling, and the signals with large synchronous frequency fluctuations are selected with asynchronous sampling using the synchronous/asynchronous switch. (N is a positive integer)
The predicted value is a signal value composed of one pixel value or multiple pixel values located in A first prediction error signal is obtained by comparing each signal value as a predicted value with the current value, and a previous value prediction is further performed on the first prediction error signal to obtain a second prediction error signal. The second prediction error signal is quantized and encoded to directly encode the NTSC signal within the frame and sent to the transmission path, and the receiving side decodes the received second prediction error signal. An intraframe coding/decoding method characterized by obtaining a first prediction error signal and decoding the first prediction error signal to reproduce an NTSC signal.