JPS5819146B2 - charge transfer device - Google Patents

charge transfer device

Info

Publication number
JPS5819146B2
JPS5819146B2 JP53062433A JP6243378A JPS5819146B2 JP S5819146 B2 JPS5819146 B2 JP S5819146B2 JP 53062433 A JP53062433 A JP 53062433A JP 6243378 A JP6243378 A JP 6243378A JP S5819146 B2 JPS5819146 B2 JP S5819146B2
Authority
JP
Japan
Prior art keywords
charge
layer
region
charge transfer
short
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53062433A
Other languages
Japanese (ja)
Other versions
JPS54152980A (en
Inventor
谷川邦広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53062433A priority Critical patent/JPS5819146B2/en
Publication of JPS54152980A publication Critical patent/JPS54152980A/en
Publication of JPS5819146B2 publication Critical patent/JPS5819146B2/en
Expired legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1062Channel region of field-effect devices of charge coupled devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 本発明は電荷転送装置、とくに蛇行状の電荷経路を有す
る電荷転送装置の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a charge transfer device, particularly a charge transfer device having a meandering charge path.

電荷転送装置には種々の形式のものが提案されており、
一般的には電荷を転送するための電極がビットごとに分
割されて一直線に配置されているが、蛇行型電荷転送装
置ではビット数にかかわらず2本の電極により電荷を蛇
行状に転送することが可能となっている。
Various types of charge transfer devices have been proposed.
Generally, electrodes for transferring charge are divided into bits and arranged in a straight line, but in a meandering type charge transfer device, charge is transferred in a meandering manner using two electrodes regardless of the number of bits. is possible.

これ(と関し本出願人は以前に特願昭52−80264
により提案した。
Regarding this, the present applicant previously filed Japanese Patent Application No. 52-80264.
proposed by.

この蛇行型電荷転送装置は、第1図に示すように半導体
基板の一主要面上において互に平行に延長する帯状の電
荷層1および2に挾まれた区域を電荷転送領域とし、さ
らに各帯状電荷層から上記転送領域の中央に向ってくし
歯形に延長する短い電荷層3a、3b’、3c・・・・
・・・・・・・・および4a 、 4b 。
As shown in FIG. 1, this serpentine charge transfer device has an area sandwiched between band-shaped charge layers 1 and 2 extending parallel to each other on one main surface of a semiconductor substrate as a charge transfer region, and each band-shaped Short charge layers 3a, 3b', 3c, . . . extend in a comb-like shape from the charge layer toward the center of the transfer region.
......and 4a, 4b.

4c・・・・・・・・・・・・が設けられている。4c......... is provided.

以下電荷層3a。3b、3c・・・・・・・・・・・・
・を第1群、同様に4a+4bt4c・・・・・・・・
・・・・を第2群と呼ぶことにする。
Charge layer 3a below. 3b, 3c・・・・・・・・・・・・
・is the first group, similarly 4a+4bt4c...
... will be called the second group.

同図から明らかなように、2つの電荷層の群は上下から
交互に突出するように配列されていて、この配列により
電荷転送領域内に蛇行状の電荷通路Rが設定されている
As is clear from the figure, the two groups of charge layers are arranged so as to protrude alternately from above and below, and this arrangement creates a meandering charge path R within the charge transfer region.

しかし上記電荷通路R内を矢印付き曲線5で示す方向に
沿って電荷を転送するためには、電荷転送領域下に深さ
の異なる電位の井戸(Potentia1w’e I
l’)を形成する必要がある。
However, in order to transfer charges along the direction indicated by the arrowed curve 5 within the charge path R, a well (Potenti 1 w'e I
l').

このための手段の一つとしては、電荷転送領域内に局部
的に不純物を導入することで達成することができる。
One way to achieve this is to locally introduce impurities into the charge transfer region.

この点につい□て次に詳細に説明する。This point will be explained in detail next.

電荷転送領域内で同一群中で相隣る2本の短い電荷層、
例えば3aと3bとに挾まれる領域を説明の便宜上セル
と呼ぶことにする。
two short charge layers adjacent to each other in the same group within the charge transfer region;
For example, the area sandwiched between 3a and 3b will be called a cell for convenience of explanation.

したがって、たとえば短い電荷層4aと4bとに挾まれ
る領域は同じ<3aおよび3bに挾まれる領域とは別個
のセルとする。
Therefore, for example, a region sandwiched by short charge layers 4a and 4b is a separate cell from a region sandwiched by the same <3a and 3b.

また各個のセルには矢印付き曲線5で示した方向に順番
に11,12,13・・・・・・・・・という符号を付
ける。
Further, each cell is numbered 11, 12, 13, . . . in order in the direction indicated by the arrowed curve 5.

たとえばいまセル12に電荷が蓄積されているとして、
次の電荷転送の時点ではセル11およびセル13に同時
に転送用電圧が印加されるから、上記電荷はセル13に
のみ転送されるとは限らすセル11の方へも逆流する可
能性がある。
For example, suppose that charge is currently accumulated in cell 12,
At the time of the next charge transfer, the transfer voltage is simultaneously applied to cell 11 and cell 13, so the charge is not necessarily transferred only to cell 13, but may also flow back toward cell 11.

そこで第1図の装置においては、セル12中の128の
領域に当たる基板表面部分に不純物をドープして、電荷
の逆流を阻止するバリア領域を形成し、この部位下に生
ずる電位の井戸の深さは非ドープ領域部位下のそれより
も浅くなるようにしている。
Therefore, in the device shown in FIG. 1, impurities are doped into the surface of the substrate corresponding to the region 128 in the cell 12 to form a barrier region that prevents the reverse flow of charges, and the depth of the potential well generated under this region is is shallower than that under the undoped region.

このように両領域の表面層の不純物濃度に差をつければ
、セル11からセル12の不純物ドープ領域12aの下
の浅い井戸に移動してきた電荷は、全部が直ちに非ドー
プ領域12b直下の深い井戸内に流入してここに蓄積さ
れる。
By making a difference in the impurity concentration in the surface layer of both regions in this way, all of the charges that have moved from cell 11 to the shallow well below the impurity doped region 12a of cell 12 are immediately transferred to the deep well immediately below the undoped region 12b. It flows into the interior and is accumulated here.

ゆえに電荷の逆流は生じない。Therefore, no backflow of charge occurs.

同様にセル13においても13aの領域の下には浅い井
戸、13bの領域の下には深い井戸が生ずるから、12
bからの電荷は一旦不純物ドープ領域13aの下へ移動
し、その電荷は直ちに非ドープ領域13b下の蓄積部へ
移り再びセル12の方へ逆流することはない。
Similarly, in cell 13, a shallow well is formed under the region 13a and a deep well is formed under the region 13b, so 12
The charges from b move once under the impurity doped region 13a, and the charges immediately move to the storage section below the undoped region 13b, and do not flow back toward the cell 12 again.

このように各セルは、電荷を蓄積する蓄積領域と、電荷
の転送とその逆流を防ぐための不純物ドープ領域、すな
わちバリア領域とからできている。
In this way, each cell is made up of an accumulation region for storing charge and an impurity-doped region, that is, a barrier region, for preventing charge transfer and reverse flow.

なおバリア領域には分り易いように交差斜線を施した。Note that the barrier area is marked with intersecting diagonal lines for easy understanding.

以上の説明から明らかなように電荷の転送に方向性を持
たせるために従来は、セル内のバリア領域を形成するの
に、例えば転送セルを構成する蓄積領域とバリア領域は
SiO2等の絶縁層の厚さに差を設けて表面電位の差を
作るステップドオキサイド構造、あるいは不純物の拡散
、イオン注入等により前記両領域のチャネル内ζζ不純
物濃度の差を設けることにより表面電位の差を作る構造
を用いて形成しているが、いずれも選択的なエツチング
あるいは拡散工程等が複雑化し、工程数も増加するので
工程歩留りや集積度などで問題が多い。
As is clear from the above explanation, in order to provide directionality to charge transfer, conventionally, barrier regions within cells have been formed. A stepped oxide structure that creates a difference in surface potential by creating a difference in thickness, or a structure that creates a difference in surface potential by creating a difference in the ζζ impurity concentration in the channel of both regions by impurity diffusion, ion implantation, etc. However, in either case, the selective etching or diffusion process becomes complicated, and the number of steps increases, resulting in many problems in terms of process yield and degree of integration.

本発明は前述の点に鑑み、蛇行型電荷転送装置の機能を
低下させずに工程数を軽減せんとするもので、電荷転送
部のバリア領域の形成に、前記した従来のゲート絶縁層
の厚さを変えるとか、又イオン注入によってチャネル内
に不純物の濃度差を作るといった工程を用いないもので
ある。
In view of the above-mentioned points, the present invention aims to reduce the number of steps without deteriorating the function of the meandering type charge transfer device. This method does not use processes such as changing the impurity concentration or creating a difference in impurity concentration within the channel by ion implantation.

本発明の原理を第2図に示す。The principle of the invention is shown in FIG.

第2図は絶縁層21を介してゲート電極22を配設した
もので、電荷転送装置の電荷転送部の電位分布を示し、
この例ではゲート電圧、基板濃度は同一と仮定した。
FIG. 2 shows the potential distribution of the charge transfer section of the charge transfer device in which a gate electrode 22 is disposed through an insulating layer 21,
In this example, it is assumed that the gate voltage and substrate concentration are the same.

第2図イのチャネル20の幅、つまり電荷層30と4イ
の間が広い場合にはその間に生じる表面電位ξSが点線
で示しているように大きく、深い電位の井戸が生じるが
、他方第2図口の例では電荷層30と4イ間のチャネル
20の幅が狭くなった場合を示し、その間に生じる表面
電位ξSは点線で示したように小さくなり底の浅い電位
の井戸が生ずる。
When the width of the channel 20 in FIG. 2A, that is, between the charge layers 30 and 4A is wide, the surface potential ξS generated therebetween is large as shown by the dotted line, and a deep potential well is created. The example shown in Figure 2A shows a case where the width of the channel 20 between the charge layers 30 and 4A is narrowed, and the surface potential ξS generated therebetween becomes small as shown by the dotted line, creating a shallow potential well.

いわゆるナロウチャネル(narrowchannel
)効果が生じて、本発明はこの効果を利用したもので、
電荷転送経路のバリア領域を形成;すべき位置の電荷層
の間隔を狭くした構造によりバリア領域を形成すること
が可能となる電荷転送装置を提供せんとするものである
so-called narrow channel
) effect occurs, and the present invention utilizes this effect,
It is an object of the present invention to provide a charge transfer device in which a barrier region of a charge transfer path can be formed by a structure in which the distance between charge layers is narrowed at positions where a barrier region is to be formed.

本発明はかかる目的を達成するために、前記蛇行状電荷
転送経路を形成すべく配置する短い電荷層の隣接相互間
のチャネル幅を狭くする構造にして、ナロウチャンネル
効果を生じさせ、以ってバリア機能を有する領域を構成
したことを特徴とするものである。
In order to achieve this object, the present invention employs a structure in which the channel width between adjacent short charge layers arranged to form the meandering charge transfer path is narrowed, thereby producing a narrow channel effect. It is characterized by comprising a region having a barrier function.

以下に本発明の一実施例について第3図を用い□て説明
する。
An embodiment of the present invention will be described below with reference to FIG.

第3図は、本発明に係る電荷転送装置の一実施例を上面
図として示したもので、第1図と同等部分には同一符号
を付した。
FIG. 3 shows an embodiment of the charge transfer device according to the present invention as a top view, and the same parts as in FIG. 1 are given the same reference numerals.

第3図の実施例においては、各短い電荷層3a。In the embodiment of FIG. 3, each short charge layer 3a.

3b・・・・・・・・・と4a、4b・・・・・・・・
・のそれぞれ中央線X−xを越えた突出端部の間に間口
2〜5μm1奥行き5〜8μm程度の島状の電荷層31
1イ、312イ、313イを、又同様に電荷層4aと3
bの間に前述と同様の島状の電荷層411イ、 。
3b...... and 4a, 4b...
An island-shaped charge layer 31 with a width of 2 to 5 μm and a depth of approximately 5 to 8 μm is located between the protruding ends beyond the center line X-x.
1a, 312i, 313i, and similarly charge layers 4a and 3a.
An island-shaped charge layer 411a similar to that described above is formed between b and b.

412イ、413イを3〜5μm程度の間隔をもって中
央線x−x’に沿って配置しである。
412a and 413a are arranged along the center line xx' with an interval of about 3 to 5 μm.

この場合、島状の電荷層411イ、412イ、413イ
等は、電荷層3a 、 3b・・・・・・および4a、
4b、−0・・・等と同一の工程により同時に形成する
ことができる。
In this case, the island-shaped charge layers 411a, 412a, 413i, etc. are the charge layers 3a, 3b... and 4a,
4b, -0, etc. can be formed simultaneously by the same process.

このようにすれば各島状電荷層の両側に斜線で示したい
わゆるバリア領域401イ、4010401ハ、40に
あるいは402イ、4020.402ハ、402二が形
成され、それぞれがナロウチャンネル効果によるバリア
機能を持って電荷を矢印付き曲線5に沿って転送するこ
とが可能となる。
In this way, so-called barrier regions 401A, 4010401C, 40 or 402A, 4020, 402H, 4022 are formed on both sides of each island-like charge layer, each of which is a barrier due to the narrow channel effect. It becomes possible to functionally transfer charges along the arrowed curve 5.

ゆえに本発明によれば、バリア領域を形成すべき領域の
幅を狭くするよう隣接して対向する短い電荷層の相互間
に連続して、又は不連続に電荷堰と同じ高濃度層を設け
ることにより該電荷堰と同時にバリア領域を作ることが
可能となる。
Therefore, according to the present invention, a high concentration layer, which is the same as a charge weir, is provided continuously or discontinuously between adjacent short charge layers so as to narrow the width of the region where the barrier region is to be formed. This makes it possible to create a barrier region simultaneously with the charge weir.

そしてこの場合、ナロウチャンネル効果を与える電荷堰
は島状に配しであるので、セル容量が大きくなった場合
でも島状電荷層を適宜細分化することでチャンネル全体
のコンダクタンスを極端に低下させることなくバリア機
能を達成することができる。
In this case, the charge weirs that provide the narrow channel effect are arranged in the form of islands, so even if the cell capacitance increases, the conductance of the entire channel can be extremely reduced by dividing the island-like charge layer appropriately. Barrier function can be achieved without

以上のことから本発明の電荷転送装置はナロウチャネル
効果を利用して、該電荷転送経路のバリア領域を形成す
べき位置のチャネル幅を電荷堰の形状によって狭くする
ことによりバリア領域と同等の効果を得ている。
From the above, the charge transfer device of the present invention utilizes the narrow channel effect to narrow the channel width at the position where the barrier region of the charge transfer path is to be formed by the shape of the charge weir, thereby achieving the same effect as the barrier region. I am getting .

ゆえに電荷堰を形成すれば同時にバリア領域をも得たと
同等の結果となるからバリア領域形成工程を省くことが
可能となり、大幅に工程数の削減ができるなど優れた利
点がある。
Therefore, if a charge weir is formed, the result is equivalent to forming a barrier region at the same time, so the step of forming a barrier region can be omitted, and the number of steps can be significantly reduced, which is an excellent advantage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の蛇行状電荷通路を有する電荷転送装置の
電荷堰およびバリア領域を示す上面図、第2図イ、口は
本発明に係るバリア機能の原理を説明するための概略図
、第3図は本発明に係る電荷転送装置の一実施例におけ
る電荷堰およびバリア領域の形状を示す上面図である。 1および2:帯状電荷層、3a、3bt3ct・・・・
・・・・・:短い電荷堰の第1群、4a、4b、4c戸
・・・・・・・・・:同じく第2群、5:電荷経路、1
1゜12.13・・・・・・・・・:セル、12a 、
13a 、14a・・・・・・・・・:バリア領域、3
11イ、312イ。 313イおよび411イ、412イ、413イ:島状電
荷層、401イ、4010,401ハ。 140におよび402イ、4020,402ハ。 402二:バリア領域。
FIG. 1 is a top view showing the charge weir and barrier region of a conventional charge transfer device having a meandering charge path; FIG. FIG. 3 is a top view showing the shapes of the charge weir and barrier region in one embodiment of the charge transfer device according to the present invention. 1 and 2: band-shaped charge layer, 3a, 3bt3ct...
...: 1st group of short charge weirs, 4a, 4b, 4c doors ......: Also 2nd group, 5: Charge path, 1
1゜12.13・・・・・・・・・:Cell, 12a,
13a, 14a......: barrier area, 3
11i, 312i. 313i, 411i, 412i, 413i: island-shaped charge layer, 401i, 4010, 401c. 140 and 402a, 4020, 402c. 4022: Barrier area.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板の表面に互に平行に延長する少なくとも
一対の帯状部分を有する電荷層と、該帯状部分に挾まれ
た電荷転送領域と、該領域内において該領域の辺縁部か
ら中央線を越えて交互に突出し、かつ対向する辺縁部と
ある間隔を隔てて終端する複数の短い電荷層とを具え、
該短い電荷層によって電荷転送領域内に蛇行状の電荷経
路を構成してなる電荷転送装置において、上記短い電荷
層の中央線を越えた先端部とその後位に隣接する対向縁
辺部からの短い電荷層との間に、前記中央線に沿って少
なくとも1個の島状電荷層を設け、該島状電荷層の両側
にナロウチャンネル効果を利用した電荷の逆流阻止領域
を構成してなることを特徴とする電荷転送装置。
1. A charge layer having at least a pair of strip-shaped portions extending parallel to each other on the surface of a semiconductor substrate, a charge transfer region sandwiched between the strip-shaped portions, and a charge transfer region extending from the edge of the region beyond the center line within the region. comprising a plurality of short charge layers that alternately protrude from each other and terminate at opposite edges and at a certain interval;
In a charge transfer device in which a meandering charge path is formed in a charge transfer region by the short charge layer, a short charge is generated from the tip of the short charge layer beyond the center line and the opposing edge adjacent to the tip of the short charge layer. At least one island-like charge layer is provided along the center line between the charge island layer and the charge island layer, and charge backflow prevention regions utilizing a narrow channel effect are formed on both sides of the island-like charge layer. charge transfer device.
JP53062433A 1978-05-24 1978-05-24 charge transfer device Expired JPS5819146B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53062433A JPS5819146B2 (en) 1978-05-24 1978-05-24 charge transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53062433A JPS5819146B2 (en) 1978-05-24 1978-05-24 charge transfer device

Publications (2)

Publication Number Publication Date
JPS54152980A JPS54152980A (en) 1979-12-01
JPS5819146B2 true JPS5819146B2 (en) 1983-04-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP53062433A Expired JPS5819146B2 (en) 1978-05-24 1978-05-24 charge transfer device

Country Status (1)

Country Link
JP (1) JPS5819146B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5978572A (en) * 1982-10-28 1984-05-07 Sony Corp Charge transfer device
JP2005174965A (en) * 2003-12-05 2005-06-30 Nec Kyushu Ltd Charge transfer device and its fabricating process

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5217771A (en) * 1975-07-31 1977-02-09 Sony Corp Charge transfer device
JPS5355990A (en) * 1976-10-29 1978-05-20 Fujitsu Ltd Electric charge transfer device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5217771A (en) * 1975-07-31 1977-02-09 Sony Corp Charge transfer device
JPS5355990A (en) * 1976-10-29 1978-05-20 Fujitsu Ltd Electric charge transfer device

Also Published As

Publication number Publication date
JPS54152980A (en) 1979-12-01

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