JPH07321332A - Mis type semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To form a semiconductor region without being substantially affected by thickness nonuniformity of a semiconductor region when grinding an SOI substrate and simultaneously form a double gate structure of a MIS type semi conductor device such as MISFETs in a single step by a self-alignment method and further enhance the integration of semiconductor elements. CONSTITUTION:In a MIS type semiconductor device comprising a semiconductor region 2 of an SOI substrate 1 and a gate electrode provided so as to adjoining the semiconductor region 2 via a gate insulation film 3, two band-like gate electrodes 4a, 4b formed by a self-alignment method are arranged on both-side surfaces of the bandlike semiconductor region 2 and also a channel C formed the in the semiconductor region 2 is set so as to be in the vertical direction of the SOI substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS type semiconductor device using an SOI (semiconductor on insulator) substrate composed of an insulating film and a semiconductor region formed on or in the insulating film in an island shape. Regarding More specifically, the present invention relates to a MIS type semiconductor device having a double gate formed by a self-alignment method.

[0002]

2. Description of the Related Art In recent years, SOI substrates have been used for the purpose of improving the degree of integration of semiconductor devices (JP-A-1-175235).

Such an SOI substrate is manufactured as shown in FIG. That is, the convex portion 51a is provided on the silicon wafer 51 by the photolithography method (FIG. 5A), and the SiO ₂ oxide film 52 is deposited on the surface of the convex portion 51a side (FIG. 5B). A polysilicon film 53 is formed on the upper surface, and the surface thereof is polished to be flat (FIG. 5).
(C)). Next, the support substrate 54 is attached to the flattened polysilicon film 53 (FIG. 5D), and a polishing cloth or the like is used on the silicon wafer 51 side so that only the convex portions 51a of the silicon wafer 51 remain. And polish (Fig. 5
(E)), so that as shown in FIG. 5 (f), island-shaped silicon regions, that is, semiconductor regions 5 are formed in the SiO ₂ oxide film 52.
The SOI substrate 50 in which 5 is formed is obtained.

The SOI substrate thus obtained can be used for manufacturing various devices. For example, it can be used for manufacturing a MISFET as shown in FIG. In the MISFET of the same figure, the source region S or the drain region D is formed in this region by ion-implanting impurities into both ends of the semiconductor region 62 formed in the insulating substrate 61 in an island shape. A channel region C is formed between the source region S and the drain region D, and a gate electrode 64 is provided on the channel region C via a gate oxide film 63.

However, in the MISFET using the SOI substrate as shown in FIG. 6, there is a problem that charges are accumulated in the semiconductor region 62 on the side opposite to the gate electrode 64, and as a result, the channel current flows in the gate electrode 64. Could not be controlled effectively.

Therefore, as shown in FIG. 7, the gate oxide film 6 is formed on the surface of the semiconductor region 62 on the side opposite to the gate electrode 64.
It has been proposed that a second gate electrode 66 is formed via 5 to form a double gate structure so that charges are not accumulated in the semiconductor region 62.

[0007]

However, as shown in FIG. 5, when the silicon wafer 51 is polished to form the semiconductor region 55, the thickness of the semiconductor region is controlled by measuring the actual thickness. However, the surface 52a (FIG. 5E) of the SiO ₂ oxide film 52 having a polishing rate different from that of the material of the semiconductor region 51 is merely used as a polishing stopper. There is a problem that the thickness becomes thinner than that of the peripheral portion and the thickness cannot be controlled. Such a problem has occurred not only when forming a single semiconductor region on an SOI substrate but also when forming a plurality of semiconductor regions. In particular, when forming a plurality of semiconductor regions having different areas on the SOI substrate, it is difficult to control the thickness of a semiconductor region having a wide area among the plurality of semiconductor regions.

Therefore, the MISFE as shown in FIG.
When the T cell is formed, there is a problem that the control of the thickness of the semiconductor region forming the source region, the drain region and the channel region becomes insufficient, and the gate threshold voltage fluctuates and the desired performance cannot be realized in the cell. It was

When the SOI substrate is used to form the double gate as shown in FIG. 7, it is structurally impossible to form the gate electrodes 64 and 66 by the self-alignment method. It was formed separately.
As a result, there is a problem in that misalignment occurs between the gate electrodes, an electric field applied to the semiconductor region becomes unbalanced, and electric field concentration occurs at the gate end, which adversely affects device characteristics.

Further, when the gate electrodes 64 and 66 are formed above and below the semiconductor region 62 to form a double gate structure as shown in FIG. 7, wiring, capacitors, etc. for connecting to the semiconductor region are connected to the gate electrode. Since it is formed on the side of the semiconductor region, the area occupied by the device is increased, which is an obstacle to improving the degree of integration.

The present invention is intended to solve the above-described problems of the prior art, and enables formation of a semiconductor region without being substantially affected by the thickness unevenness of the semiconductor region during polishing of an SOI substrate. And at the same time, M such as MISFET
A double gate structure of an IS type semiconductor device can be formed by a self-alignment method in a single step.
It is an object of the present invention to improve the degree of integration of semiconductor devices.

[0012]

The present inventor has described the above by forming a channel region in a direction perpendicular to the SOI substrate and allowing the channel region to be controlled by two gate electrodes provided on the side surface thereof. The inventors have found that the object can be achieved, and have completed the present invention.

That is, the present invention is a MIS type semiconductor device comprising a band-shaped semiconductor region provided on an SOI substrate and a gate electrode provided so as to be adjacent to the semiconductor region via a gate insulating film. A strip-shaped semiconductor region is provided between two strip-shaped gate electrodes facing each other, and the channel formed in the semiconductor region is SOI.
MI characterized by being formed in the vertical direction of the substrate
An S-type semiconductor device is provided.

In addition, the present invention provides the method for manufacturing a MIS type semiconductor device described above: a step of patterning the semiconductor region in a strip shape so that a side surface of the semiconductor region provided on the SOI substrate is exposed; Forming a gate oxide film; forming a polysilicon layer on the gate oxide film; and anisotropically etching back the polysilicon layer to form two strip-shaped gate electrodes facing each other on both sides of the semiconductor region. Provided is a manufacturing method including a forming step.

[0015]

In the MIS type semiconductor device and the manufacturing method thereof according to the present invention, the channel region is formed in the direction perpendicular to the SOI substrate. Therefore, without increasing the cell occupation area,
The gate length (x in FIG. 1) can be lengthened in the vertical direction of the SOI substrate, and the range of selection of the gate length can be widened.

The width of the semiconductor region forming the source region, the drain region and the channel region (y in FIG. 1).
Can be formed by very precise anisotropic etching,
The width can be controlled on the order of 0.01 μm. Therefore, the influence of uneven polishing of the SOI substrate can be eliminated. Therefore, the MIS semiconductor device of the present invention becomes a semiconductor device having a stable gate threshold voltage. Moreover, since the thickness of the semiconductor region can be made very thin, controllability by the gate electrode can be enhanced.

Further, in the present invention, the channel region is controlled by the two gate electrodes provided on the side surface thereof. Therefore, the controllability of the gate electrode is further improved, and electric charges are not accumulated in the semiconductor region.

[0018]

The present invention will be described in more detail below with reference to the drawings.

FIG. 1A is a sectional perspective view of the basic mode of the MIS type semiconductor device of the present invention. In this semiconductor device, a band-shaped semiconductor region 2 made of Si, GaAs or the like is provided on an SOI substrate 1, and band-shaped gate electrodes 4a and 4b are arranged on both sides of the band-shaped semiconductor region 2 with a gate insulating film 3 interposed therebetween. have. Here, a source region or a drain region (S / D) and a drain region or a source region (D /
S) are formed, and therefore, the channel region C is formed in the vertical direction of the SOI substrate 1. Further, the semiconductor region 2 is connected to the electrodes 5 and 6 at the lower and upper portions thereof,
Further, an interlayer insulating film 7 is formed below the upper electrode 5. The wiring of the gate electrodes 4a and 4b is drawn from the front side of the drawing (not shown). With such a structure, the gate length can be extended in the vertical direction of the SOI substrate without increasing the cell occupying area, and the degree of freedom of the element structure can be improved. In addition, since one channel region is controlled by the two gates, controllability can be improved, and moreover, charges can be prevented from being accumulated in the semiconductor region 2.

In the embodiment shown in FIG. 1A, the semiconductor region 2 is connected to the electrodes 5 and 6 at the lower and upper portions thereof, but any one of the electrodes may be replaced by a capacitor.
In that case, a DRAM cell can be constructed.

Although the embodiment of FIG. 1A shows an example in which a semiconductor device in which one gate region is controlled by two gate electrode is formed in one semiconductor region of the SOI substrate, the present invention is not limited to this. The SOI is not limited to the embodiment.
The present invention also includes two or more similar semiconductor devices formed in one semiconductor region of the substrate. In FIG. 1 (b), S
An example in which two similar semiconductor devices are formed in one semiconductor region of the OI substrate is shown. Next, the manufacturing method of the MIS type semiconductor device of the present invention will be described with reference to FIGS.

First, the semiconductor wafer 21 such as Si or GaAs is patterned to form the convex portion 21a (FIG. 2).
(A)). This convex portion 21a becomes an island-shaped semiconductor region of the SOI substrate.

A SiO ₂ film 22 is formed on the wafer 21 (FIG. 2B). Then, in order to form a bit line to be described later, a hole reaching the convex portion 21a is formed in the SiO ₂ film 22, and further polysilicon 23 is deposited on the entire surface (FIG. 2C). At this time, the contact between the convex portion 21a and the polysilicon 23 can be made by implanting impurities into the polysilicon 23.

Next, the polysilicon 23 is patterned to form a bit line 24 (FIG. 2 (d)). Then, an interlayer insulating film 25 is formed on the entire surface (FIG. 2E), and further,
Polysilicon 26 is deposited and mechanically polished to planarize it (FIG. 2F).

Next, a support substrate 27 made of polysilicon or the like is attached to the flattened polysilicon 26 side (FIG. 2 (g)). Then, the wafer 21 is polished by using the SiO ₂ film 22 as a polishing stopper, and
SO in which the bit line 24 is buried and a semiconductor layer 28 such as Si is formed on the bit line 24 as shown in FIG.
The I substrate 20 is obtained.

Next, the semiconductor layer 28 of the SOI substrate 20.
Is patterned to form a band-shaped semiconductor region 29.
At this time, the side surface of the semiconductor region 29 is exposed (FIG. 3I). This is because the gate electrodes can be formed on both side surfaces as described later.

Next, a gate oxide film 30 is formed on the entire surface (FIG. 3 (j)).

Polysilicon 3 is formed on the gate oxide film 30.
1 (FIG. 3 (k)) and anisotropically etched back by a reactive ion etching method or the like to form the semiconductor region 29.
Side wall-shaped gate electrodes 32a on both sides of the
And 32b are formed (FIG. 3 (l)).

Next, an interlayer insulating film 33 is formed on the surface (FIG. 3 (m)). Then, a contact hole Ch reaching the semiconductor region 29 is formed in the interlayer insulating film 33, and the exposed semiconductor region 29 is further doped with an impurity to form a source region or a drain region (S / D) (FIG. 3 ( n)).

Next, the contact hole Ch is filled with the conductive material 34 by the stacking method or the like, the storage node 35 is further formed thereon, and the capacitor insulating film 36 is further formed on the entire surface (FIG. 3 (o)). .

After that, a cell plate 37 is formed on the capacitor insulating film 36 so that D shown in FIG.
RAM can be obtained.

As described above, since the semiconductor region 28 is formed by anisotropically etching the semiconductor layer 28, the thickness thereof can be made extremely thin and uniform. Further, the length of the gate electrode in the depth direction of the semiconductor region (gate length) can be extended without increasing the cell occupation area.

Further, in the present invention, the two gate electrodes are simultaneously formed into symmetrical shapes by anisotropic etching back without using an etching resist or an etching mask, that is, by the self-alignment method. It Therefore, according to the present invention, it is possible to form a semiconductor device having a double gate structure with no displacement.

As shown in FIG. 1B, the SOI
In a semiconductor device having two similar cells formed in one semiconductor region of a substrate, one semiconductor layer of an SOI substrate is patterned into two independent semiconductor regions 29a and 29b as shown in FIG. 4, and other steps are performed. It can be manufactured by basically the same steps as those shown in FIGS.

[0035]

According to the present invention, the semiconductor region can be formed without being substantially affected by the uneven thickness of the semiconductor region during polishing of the SOI substrate. At the same time, a double gate structure of a MIS type semiconductor device such as a MISFET can be formed by a self-alignment method in one step. Furthermore, the degree of integration of semiconductor elements can be improved.

[Brief description of drawings]

FIG. 1 is a sectional perspective view of a basic aspect of a MIS type semiconductor device of the present invention.

FIG. 2 is a manufacturing process diagram when the MIS semiconductor device of the present invention is applied to a DRAM.

FIG. 3 is a manufacturing process diagram when the MIS semiconductor device of the present invention is applied to a DRAM.

FIG. 4 is an explanatory diagram of patterning of a semiconductor region necessary when two semiconductor devices are formed in one semiconductor region of an SOI substrate.

FIG. 5 is a manufacturing process diagram of an SOI substrate.

FIG. 6 is a schematic cross-sectional view of a conventional DRAM using an SOI substrate.

FIG. 7 is a conventional double gate DR using an SOI substrate.
It is a schematic sectional drawing of AM.

[Explanation of symbols]

 1 SOI Substrate 2 Semiconductor Region 3 Gate Insulating Film 4a, 4b Gate Electrode S / D Source or Drain Region D / S Drain Region or Source Region C Channel Region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/12 Z H01L 27/10 325 E 9056-4M 29/78 311 G

Claims (4)

[Claims] 1. A MIS comprising a band-shaped semiconductor region provided on an SOI substrate and a gate electrode provided adjacent to the semiconductor region with a gate insulating film interposed therebetween.
In the semiconductor device, a strip-shaped semiconductor region is provided between two strip-shaped gate electrodes facing each other, and a channel formed in the semiconductor region is formed in a vertical direction of the SOI substrate. MIS type semiconductor device. 2. The MIS type semiconductor device according to claim 1, wherein a capacitor is formed on an upper part or a lower part of the semiconductor region. 3. The method for manufacturing a MIS type semiconductor device according to claim 1, wherein the step of patterning the semiconductor region in a strip shape so as to expose the side surface of the semiconductor region provided on the SOI substrate; the gate on the surface of the SOI substrate Forming an oxide film; forming a polysilicon layer on the gate oxide film; and anisotropically etching back the polysilicon layer to form two strip-shaped gate electrodes facing each other on both sides of the semiconductor region. A manufacturing method comprising the step of: 4. The manufacturing method according to claim 3, wherein an SOI substrate in which a capacitor is embedded in the upper or lower portion of the semiconductor region is used.