JPS5818931A - Sealing of ic - Google Patents

Sealing of ic

Info

Publication number
JPS5818931A
JPS5818931A JP11794981A JP11794981A JPS5818931A JP S5818931 A JPS5818931 A JP S5818931A JP 11794981 A JP11794981 A JP 11794981A JP 11794981 A JP11794981 A JP 11794981A JP S5818931 A JPS5818931 A JP S5818931A
Authority
JP
Japan
Prior art keywords
resin
hole
sealing
pellet
heating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11794981A
Other languages
Japanese (ja)
Inventor
Isao Komine
小峰　勲
Kenichi Yoshikawa
研一 吉川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Original Assignee
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Holdings Co Ltd, Citizen Watch Co Ltd filed Critical Citizen Holdings Co Ltd
Priority to JP11794981A priority Critical patent/JPS5818931A/en
Publication of JPS5818931A publication Critical patent/JPS5818931A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Abstract

PURPOSE:To obtain sealing of a thin, small circuit by bonding an IC to a hole perforated through a circuit substrate, loading the hole with a resin pellet and heating the pellet so that it is dissolved. CONSTITUTION:A resin pellet 5 is a tubular tablet of an epoxy resin, etc. A perforation hole 1a of a circuit substrate 1 can be loaded with this tubular tablet without the need for high position accuracy associated with resin dropping, since the tablet diameter is governed by the hole 1a. Also, it is a solid and thus can be treated with ease. A complete sealing of an IC3 can be made by heating the pellet at 150-180 deg.C so that it is dissolved, then it becomes stiff. The weight dispersion between formed resin pellets is far smaller than the vomit volume dispersion of liquid sealing; therefore, the constant amount of resin pellets can be provided for sealing. There is no resin upheaval through the hole 1a towards the reverse side of the substrate 1, and thus the thickness of IC packaging can be reduced to a minimum.

Description

【発明の詳細な説明】 本発明は電子時計の回路実装のためのＩＣの封止方法の
改良に関り、特に水晶発振式電子腕時計の如く、薄型小
型でかつ廉価な回路実装が要求されるＩＣの樹脂封止方
法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in the sealing method of an IC for circuit mounting of an electronic watch, and in particular, a thin, compact and inexpensive circuit mounting is required, such as a crystal oscillation type electronic watch. The present invention relates to a resin sealing method for IC.

近年市場に於ける水晶発振式電子腕時計の需要は急増し
ており、゛これに伴い市場の要求も薄型小型で多機能を
有し、かつ廉価である等と厳しいものとなっている。In recent years, the demand for crystal oscillation type electronic wristwatches in the market has increased rapidly, and along with this, the market demands have become stricter, such as thin and compact watches with multiple functions and low prices.

これらの要求を満足し、薄型小型でかつ廉価な回路実装
を実現すφために最近では、ＩＣのアルミニウム電極上
に、半田でなる突起電極を形成し、この突起電極と回路
基板上の接続パターンとをフェイスダウンポンディング
して成すフリップチップ実装方式が採用されている。こ
のフリップチップ実装方式によると、従来のワイヤーボ
ンディング方式に比べ１、ワイヤーを張って接続を取る
ことなしにポンディング可能のため、ワイヤーループに
要する高さ方向および平面方向のスペースを最小限に押
えることができる。さらに多数電、極を同時にボンディ
ング処理できるため、工数の削減に寄与し、廉価で薄型
小型の回路実装を追求する水晶発振式電子腕時計などに
対し今後大いに期待されるものである。In order to satisfy these demands and realize thin, small, and inexpensive circuit mounting, recently, protruding electrodes made of solder are formed on the aluminum electrodes of ICs, and connection patterns between these protruding electrodes and the circuit board are formed. A flip-chip mounting method is used, which is achieved by face-down bonding. Compared to conventional wire bonding methods, this flip-chip mounting method allows bonding without stretching wires and making connections, minimizing the vertical and horizontal space required for wire loops. be able to. Furthermore, since multiple electrodes and poles can be bonded at the same time, it contributes to a reduction in man-hours, and is expected to be used in the future in applications such as crystal oscillation electronic watches that pursue inexpensive, thin, and compact circuit packaging.

このフリップチップ実装方式の多くの利点を生かし、薄
型小型でかつ廉価な回路実装を実現するための回路封止
構造の開発は重要な事柄となっている。It is important to develop a circuit sealing structure that takes advantage of the many advantages of this flip-chip mounting method and realizes thin, compact, and inexpensive circuit mounting.

以下従来の水晶発振式電子時計に於けるフリノグチノブ
実装による封止方法の欠点を、第１図、第２図によって
説明する。Hereinafter, the drawbacks of the sealing method using the furinoguchi knob mounting in the conventional crystal oscillation type electronic timepiece will be explained with reference to FIGS. 1 and 2.

第１図は、従来技術のフリップチップ実装力デによるＩ
Ｃ実装部の、液状の封止樹脂を滴下す２際の断面図を示
し、第２図は、第１図に示すＩＣ実装部の液状樹脂を滴
下し加熱硬化させて封止した状態の断面図を示す。Figure 1 shows the I
FIG. 2 is a cross-sectional view of the IC mounting portion shown in FIG. 1 after dropping the liquid resin and heating and hardening it to seal it. Show the diagram.

１は回路基板であり、エポキシ等の樹脂部材力ら成り、
その表面に極薄銅箔を接着した後、エツチング等の手法
で所定の接続パターン２が形成され、該接続パターン２
のボンディング部を含む必要部分には金メッキが施され
ている。又、後述するＩＣボンディング部の略中夫に所
定の大きさの貫通孔１ａが加工されている。６はＩＣで
あり、半田等から成る突起電極３ａを有し、前記回路基
板１の接続パターン２と３００℃程度の加熱をしてボン
ディングされている。1 is a circuit board, which is made of resin material such as epoxy;
After adhering an ultra-thin copper foil to the surface, a predetermined connection pattern 2 is formed by a method such as etching, and the connection pattern 2 is
The necessary parts, including the bonding parts, are plated with gold. Further, a through hole 1a of a predetermined size is formed approximately in the middle of an IC bonding portion, which will be described later. Reference numeral 6 denotes an IC, which has a protruding electrode 3a made of solder or the like, and is bonded to the connection pattern 2 of the circuit board 1 by heating to about 300°C.

上記構成に於て、第１図に示すごとく、前記貫通孔１ａ
にディスペンサー等で封止樹脂４を液状で滴下した後、
加熱して硬化させることにより、第２図に示すごとく、
ＩＣ３の回路が構成されている表面側と側面とを確実に
樹脂封止するフリップチップ実装方式が採用されていた
。In the above configuration, as shown in FIG.
After dropping the sealing resin 4 in liquid form with a dispenser etc.,
By heating and curing, as shown in Figure 2,
A flip-chip mounting method was used to securely seal the front and side surfaces of the IC3 with resin.

この様な従来のフリップチップ実装方式は、多くの電極
を同時にポンディング出来るため、工数の削減をもたら
しコストダウンに寄与することができるものの、工Ｃ３
の表面と側面とを確実に封止樹脂４で覆うためには、デ
ィスペンサーの吐出誤差があることを考慮して、封止樹
脂４を若干多めに供給する必要が有り、このために、封
止樹脂４が回路基板１０貫通孔１ａから裏面側に盛り上
り、ＩＣ実装部の厚みを大きくしてしまうという欠点が
有り、又、前記ディスペンサーの吐出誤差を厳しく管理
しても、ディスペンサーと貫通孔１ａとの位置精度がず
れると、吐出された樹脂の一部が回路基板１の裏面側に
吐出される結果となり、貫通孔１ａの中に吐出されて封
止を行う樹脂の量が減少し、完全な封止が行われない事
により信頼性が低下するという欠点が有った。Conventional flip-chip mounting methods like this can reduce the number of man-hours and reduce costs because many electrodes can be bonded at the same time.
In order to reliably cover the surface and side surfaces of the sealing resin 4, it is necessary to supply a slightly larger amount of the sealing resin 4, taking into account the dispensing error of the dispenser. There is a drawback that the resin 4 rises from the through hole 1a of the circuit board 10 to the back side, increasing the thickness of the IC mounting part.Also, even if the dispense error of the dispenser is strictly controlled, the dispenser and the through hole 1a If the positional accuracy deviates, a portion of the discharged resin will be discharged to the back side of the circuit board 1, and the amount of resin discharged into the through hole 1a for sealing will decrease, resulting in complete sealing. This had the disadvantage that reliability was lowered because proper sealing was not performed.

本発明の目的は、これらの欠点を解決しようとするもの
であり、フリップチップ実装方式に於て、回路基板裏面
への封止樹脂の盛り上りを防止し、より薄型化を可能に
するＩＣの封止方法を提供することである。The purpose of the present invention is to solve these drawbacks, and to provide an IC that prevents the bulging of the sealing resin on the back surface of the circuit board in the flip-chip mounting method and enables thinner ICs. An object of the present invention is to provide a sealing method.

上記目的を達成するための本発明に於ける要旨は、従来
用いられていた液状樹脂の代りに、定量化が容易な樹脂
ベレットを用いることによって、封止樹脂の定量供給を
はかり、回路基板裏面への盛り上りを防止したことにあ
る。The gist of the present invention to achieve the above object is to use a resin pellet that is easy to quantify in place of the conventionally used liquid resin, thereby supplying a fixed amount of sealing resin to the back side of the circuit board. This is to prevent the build-up of the situation.

以下本発明によるフリップチップ実装のＩＣＣ正正方法
、第３図および第４図によって説明する。The ICC correcting method for flip-chip mounting according to the present invention will be explained below with reference to FIGS. 3 and 4.

第３図および第４図は、本発明のフリップチップ実装に
よるＩＣ実装部の断面図であり、第１図、第２図と同番
号は同一部材を示し説明を省略する。3 and 4 are cross-sectional views of an IC mounting section by flip-chip mounting according to the present invention, and the same numbers as in FIGS. 1 and 2 indicate the same members, and the explanation will be omitted.

第３図に於て、第１図と異なる部分は封止用樹脂として
液状の封止樹脂４０代りに定量化された樹脂ベレット５
を用いたところである。該樹脂ベレット５は、エポキシ
系樹脂等を円筒形にタブレット成形したものであり、回
路基板１０貫通孔１ａに装填する場合、外径が貫通孔１
ａによって規制されるため、前記封止樹脂４０滴下時の
様な位置精度が要求されず、かつ固形であるため、その
取扱いも極めて容易である。In Fig. 3, the different parts from Fig. 1 are resin pellets 5 quantified as liquid sealing resin 40 as the sealing resin.
Here we have used . The resin pellet 5 is made by molding an epoxy resin or the like into a cylindrical tablet, and when loaded into the through hole 1a of the circuit board 10, the outer diameter is equal to that of the through hole 1.
Since the sealing resin is regulated by a, the positional precision required when dropping the sealing resin 40 is not required, and since it is solid, it is extremely easy to handle.

さらに第４図に於て、前記樹脂ベレット５は、１５０°
Ｃ〜１８０℃程度の加熱をすることにより溶融しさらに
硬化して封止形状を得る。Furthermore, in FIG. 4, the resin pellet 5 is rotated at 150°.
It is melted and further hardened by heating to about 180°C to obtain a sealed shape.

本発明にて使用するタブレット成形された樹脂ペレノ、
ト５の重量バラツキは、前記液状の封止樹脂４の吐出量
バラツキに比べてはるかに少な（・ため、必要の樹脂体
積となる様に寸法を選ぶことにより、定量供給が可能と
なり、回路基板１０貫通孔１ａから裏面側に樹脂が盛り
上る事は無く、ＩＣ実装部の厚みを必要最小限に押える
ことが出来る。Tablet-shaped resin pereno used in the present invention,
The variation in the weight of the resin 5 is much smaller than the variation in the discharge amount of the liquid sealing resin 4 (- Therefore, by selecting the dimensions to achieve the required resin volume, it is possible to supply a fixed quantity, and the circuit board 10 The resin does not bulge up from the through hole 1a to the back surface side, and the thickness of the IC mounting part can be kept to the necessary minimum.

なお、樹脂ベレット５は、ポリエチレン、ポリスチレン
等の炭化水素系プラスチック、ポリ塩化ビニル等のビニ
ル系プラスチック、等の熱可塑性樹脂をタブレット成形
したものでも可能なことが実験で確認できている。It has been confirmed through experiments that the resin pellet 5 can also be formed by tablet-molding thermoplastic resin such as hydrocarbon plastics such as polyethylene and polystyrene, and vinyl plastics such as polyvinyl chloride.

以上のごとく本発明の封止方法によれば、従来技術によ
るフリップチップ実装方式の実装部厚みに比べ、より薄
型化された実装部が得られ、遮光性、耐環境性等におけ
る信頼性も充分な回路実装構造を提供することが出来、
その効果は大きい。As described above, according to the sealing method of the present invention, it is possible to obtain a mounting part that is thinner than that of the conventional flip-chip mounting method, and has sufficient reliability in terms of light shielding properties, environmental resistance, etc. It is possible to provide a circuit mounting structure that is
The effect is great.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図、は従来技術によるフリップチップ実装
方式でのＩＣ実装部の断面図。 第３図、第４図、は本発明によるフリップチップ実装方
式でのＩＣ実装部の断面図。 １・・・・・・・・・回路基板 １ａ・・・・・・貫通孔 、２・・・・・・・・・接続パターン ６・・・・・・・・・ＩＣ ３ａ・・・・・・突起電極 ４・・・・・・・・・封止樹脂 ５・・・・・・・・・樹脂ペレット 第１図 第２図FIGS. 1 and 2 are cross-sectional views of an IC mounting part using a flip-chip mounting method according to the prior art. 3 and 4 are cross-sectional views of an IC mounting part using the flip-chip mounting method according to the present invention. 1......Circuit board 1a...Through hole, 2...Connection pattern 6...IC 3a...・・Protruding electrode 4 ・・・ Sealing resin 5 ・・・Resin pellet Fig. 1 Fig. 2

Claims (1)

【特許請求の範囲】[Claims] 回路基板上に形成された接続パターンに、ＩＣをフェイ
スダウンでボンディングして樹脂封止する回路実装方法
に於て、前記回路基板のＩＣボンディング部に貫通孔を
設け、前記ＩＣをボンディングした後、貫通孔に樹脂ペ
レットを装填し、加熱溶融することにより、ＩＣの表面
側を樹脂封止したことを特徴とするＩＣの封止方法。In a circuit mounting method in which an IC is bonded face-down to a connection pattern formed on a circuit board and sealed with resin, a through hole is provided in an IC bonding part of the circuit board, and after bonding the IC, A method for sealing an IC, characterized in that the front side of the IC is sealed with a resin by loading resin pellets into a through hole and heating and melting the pellets.
JP11794981A 1981-07-28 1981-07-28 Sealing of ic Pending JPS5818931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11794981A JPS5818931A (en) 1981-07-28 1981-07-28 Sealing of ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11794981A JPS5818931A (en) 1981-07-28 1981-07-28 Sealing of ic

Publications (1)

Publication Number Publication Date
JPS5818931A true JPS5818931A (en) 1983-02-03

Family

ID=14724215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11794981A Pending JPS5818931A (en) 1981-07-28 1981-07-28 Sealing of ic

Country Status (1)

Country Link
JP (1) JPS5818931A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304512A (en) * 1991-12-25 1994-04-19 Hitachi, Ltd. Process for manufacturing semiconductor integrated circuit device, and molding apparatus and molding material for the process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304512A (en) * 1991-12-25 1994-04-19 Hitachi, Ltd. Process for manufacturing semiconductor integrated circuit device, and molding apparatus and molding material for the process

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