JPS58188968A - Solid-state image pickup device - Google Patents

Solid-state image pickup device

Info

Publication number
JPS58188968A
JPS58188968A JP57071850A JP7185082A JPS58188968A JP S58188968 A JPS58188968 A JP S58188968A JP 57071850 A JP57071850 A JP 57071850A JP 7185082 A JP7185082 A JP 7185082A JP S58188968 A JPS58188968 A JP S58188968A
Authority
JP
Japan
Prior art keywords
main surface
solid
substrate
processing circuit
signal processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57071850A
Other languages
Japanese (ja)
Inventor
Akira Shimohashi
下橋 彰
Yuichiro Ito
雄一郎 伊藤
Shuji Watanabe
渡辺 修治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57071850A priority Critical patent/JPS58188968A/en
Publication of JPS58188968A publication Critical patent/JPS58188968A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/30Transforming light or analogous information into electric information

Abstract

PURPOSE:To improve integration density and to obtain a solid-state image pickup device with high resolution, by arranging a photodetecting element equipped with a photoelectric converter on one main surface of a semiconductor substrate, and arranging a circuit element for processing a signal from the photodetecting element on the other main surface. CONSTITUTION:The photodetection part is formed of an (n) type impurity layer 11 by thermal diffusion, etc., on the surface layer part of one main surface 10a of a (p) type Si substrate 10 and the impurity layer 11 is surrounded with a charge barrier 12 made of a (p) type impurity layer with high density. Further, a signal processing circuit element having a transfer gate TG and transfer electrodes phi1-phi4 is formed on the other main surface 12b through an SiO2 film 13. An output terminal by a depth-directional recessed part 14 and the input terminal 15 of the signal processing circuit element are formed of (n) type diffused layers 16 with high density at the peak part of the photodetection part while piercing both main surfaces 10a and 10b. Then, a solid-state image pickup device with a matrix array is formed on the semiconductor substrate 20 and coupled with the signal processing circuit through an (n) type diffused layer 22 without forming the signal processing circuit on the array of photodetecting elements 21, improving the degree of integration.

Description

【発明の詳細な説明】 (川 発明の技術分野 本発明は一次元あるいは二次元の固体撮lII装置に係
り、特に入射光に感応する受光素子と、該受光素子で光
電変換された信号電荷を処理するだめの回路素子とを供
えた固体撮像装置の構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a one-dimensional or two-dimensional solid-state imaging device, and particularly relates to a light-receiving element that is sensitive to incident light and a signal charge that is photoelectrically converted by the light-receiving element. The present invention relates to the structure of a solid-state imaging device including circuit elements for processing.

(b 技術の背景 近年、受光素子を多素子化して高解像度の固体撮像装置
を実現すべく集積度を向上させる研究・開発がなされて
いる。
(b) Background of the Technology In recent years, research and development has been carried out to increase the degree of integration in order to realize a high-resolution solid-state imaging device by increasing the number of light-receiving elements.

+(3+  従来技術と間部点 第1図は従来の固体撮像装置を説明するための概念的な
L面図であり、この場f&8X8のインクフィン転送方
式の二次元固体撮儂装置を例示している。
+(3+ Prior Art and Intermediate Points Figure 1 is a conceptual L-plane diagram for explaining a conventional solid-state imaging device. Here, a two-dimensional solid-state imaging device using an f&8×8 ink fin transfer method is shown as an example. ing.

第1図において、半導体基板lの一生面玉に受光素子2
がマトリックス状に配設され、各縦列ごとに配列された
各受光素子2に対応して移送グー)TOと垂直シフトレ
ジスタVSが配設されている。また各垂直シフトレジス
タvSからの信号電荷を時系列的に出力するための水平
シフトレジヌタf(Sおよび出力増幅器AMPが配設さ
れている。
In FIG.
are arranged in a matrix, and a transfer register (TO) and a vertical shift register VS are arranged corresponding to each light receiving element 2 arranged in each column. Further, a horizontal shift register f(S) and an output amplifier AMP are provided for outputting signal charges from each vertical shift register vS in time series.

、かかる固体撮像装置において、受光素子2に入射した
光は該受光素子内で光tge換されて信号電荷を発生す
る。該信号電荷は該受光素子内に一時蓄積される。一定
時間蓄積された該信号電荷は移送ゲートTGが開かれる
と垂直シフトレジヌタvSに移送され、該垂直シフトレ
ジスタVS内を順次転送したのち水平シフトレノスタE
(Sへ並列的ニ移る・さらに該信号電荷は該水平シフト
レジスタH8内を輸送されて出力増幅1(l A M 
Pで電圧に変換され時系列的に読み出される。なお第1
図中の矢印は上記信号電荷の流れを示している。
In such a solid-state imaging device, light incident on the light-receiving element 2 is converted into light tge within the light-receiving element to generate signal charges. The signal charge is temporarily accumulated within the light receiving element. When the transfer gate TG is opened, the signal charges accumulated for a certain period of time are transferred to the vertical shift register vS, and after sequentially transferred within the vertical shift register VS, the signal charges are transferred to the horizontal shift register E.
(Moves to S in parallel) Further, the signal charge is transported within the horizontal shift register H8 and output amplification 1 (l A M
It is converted into voltage at P and read out in time series. Note that the first
Arrows in the figure indicate the flow of the signal charges.

上述したような構成の固体撮像装置においては各受光素
子2が転送ゲートTO,垂1[シフトレンヌタvSおよ
び水平シフトレンメタH8等の信号処理回路素子と同−
基板玉に構成されているため、基板l内に占める有効受
光面積の割合は低下し、かつ解像度向丘の妨げとなって
いた。
In the solid-state imaging device configured as described above, each light receiving element 2 has a transfer gate TO, a vertical 1 [same as a signal processing circuit element such as a shift lens VS and a horizontal shift lens H8].
Since it is configured as a substrate ball, the ratio of the effective light-receiving area within the substrate 1 is reduced, and the resolution is hindered.

(■ 発明の目的 本発明は丘記従来の欠点に鑑み、半4体抵板の両主面を
有効に利用することで集積ifを飛躍的に向上させ、も
って高解像度の固体撮像装置を提供することを目的とす
るものである。
(■ Purpose of the Invention In view of the drawbacks of the conventional technology, the present invention dramatically improves the integrated IF by effectively utilizing both principal surfaces of a semi-quadram resistor, thereby providing a high-resolution solid-state imaging device. The purpose is to

+611  発明の構成 そしてこの目的は本発明によれば半4体基板の一主面と
に光電変換素子である受光調子を配設し、池の一王面北
に該受光素子からの信号電荷を処理するための回路素子
を配設し、かつ前記受光素子に設けた信号電荷の出力端
と前記回路素子に前記信号vi1.荷を導入する入力端
とを電気的に接続するための前記基板と通導111c型
の不純物層を該基板を繊゛通して設けたことを特做とす
る固体撮像装置を提供することによって1a成できる。
+611 Structure and object of the invention According to the present invention, a light-receiving element, which is a photoelectric conversion element, is arranged on one main surface of a semi-quartet board, and a signal charge from the light-receiving element is transmitted to the north side of the pond. A circuit element for processing is arranged, and the signal vi1. By providing a solid-state imaging device characterized in that a conductive 111c type impurity layer is provided through the substrate for electrical connection with the input end through which a charge is introduced. Can be done.

(わ 発明の実施例 、以F本発明の実施例を図面によって詳述する。(Embodiments of the invention Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第2図は本発明による固体撮像装置の一受光素子を含む
囃位構成を示す概略図であり、第2図(川あ・よび+C
+はそれぞれ基板の表裏各面く形成された受光素子およ
び信号処理回路素子の平面図を、第2図(至)は第2図
μ)およびtc+ノx −x’、Y −Y’断面を示す
図である。
FIG. 2 is a schematic diagram showing the configuration of a solid-state imaging device including one light-receiving element according to the present invention.
+ is a plan view of the light receiving element and signal processing circuit element formed on each side of the substrate, and Figure 2 (to) is a cross section of Figure 2 μ) and tc + -x', Y-Y'. FIG.

同図において、IOは例えばp型s1ウェハからなる半
導体基板であって、該基板ioの一主面tOaの表一部
にイオン注入または熱拡散法により       ”て
形成したn型不純物層からなる受光部11が形成されて
おり、該受光部の周辺は高濃度のp型不純物−からなる
或荷堰12で囲まれている。一方基板10の也の一主面
上tabには、例えばS1酸化@(S1υ1I)18を
介して移送グー)TGおよび垂直シフトレジスタとなる
電荷結合装置の転送電極ダl、ダ2.43.貞4等が配
設されて信号処理回の 路素子を形成している。そして、前記受光部2出力端1
4と信号処理回路素子の入力端15とをwL電気的闇続
するため前記基板10と通導を型の不純物層である高濃
度のn型不純物層16が基板10の両主面toa、  
tabを貫通するよう形成されている。
In the figure, IO is a semiconductor substrate made of, for example, a p-type S1 wafer, and a light-receiving layer made of an n-type impurity layer formed by ion implantation or thermal diffusion on a part of the main surface tOa of the substrate IO. A portion 11 is formed, and the periphery of the light-receiving portion is surrounded by a weir 12 made of a highly concentrated p-type impurity.On the other hand, a tab on one main surface of the substrate 10 is coated with, for example, S1 oxide. @(S1υ1I) Transfer via 18) TG and the transfer electrodes of the charge coupled device, which becomes the vertical shift register, DA1, DA2, 43, 4, etc. are arranged to form the circuit elements of the signal processing circuit. Then, the light receiving section 2 output end 1
4 and the input end 15 of the signal processing circuit element wL, a high concentration n-type impurity layer 16 which is an impurity layer of the type that conducts with the substrate 10 is formed on both main surfaces toa of the substrate 10.
It is formed to pass through the tab.

かくして、上述したような構e、を用いて、例えば8X
8のマ) IJツクヌ配列の固体撮像装置を作成すれば
、第8図のようになる。この−図から明らかなように信
号処理回路素子が受光素子21の配設面上にないため該
受光素子21を近接配置できて集積度を飛躍的に向丘さ
せ得る。第8図において、20は半導体基板、22は該
基板20と逆導電型の不純物層で前期受光素子21と図
示していない池の一主面上に配設された信号処理回路素
子とを電気的に接続する役目をもっている。
Thus, using the configuration e as described above, for example 8X
8) If you create a solid-state imaging device with an IJ Tsuknu array, it will look like the one shown in Figure 8. As is clear from this figure, since the signal processing circuit element is not on the surface on which the light receiving element 21 is disposed, the light receiving element 21 can be placed close to each other, and the degree of integration can be dramatically increased. In FIG. 8, 20 is a semiconductor substrate, and 22 is an impurity layer of a conductivity type opposite to that of the substrate 20, which electrically connects the light receiving element 21 and a signal processing circuit element disposed on one main surface of a pond (not shown). It has the role of connecting people.

次に本発明の固体撮像装置の動乍について、第2図を用
いて説明する。
Next, the operation of the solid-state imaging device of the present invention will be explained using FIG. 2.

入射光17が受光部11に入射すると、該受光部内で光
電変換されて発生した信号電荷(この場合は電子)は該
受光部11およびn型不純物層16下の電位の井戸18
に一時蓄積される。一定時間蓄積された該信号電荷は移
送グー)TGが開かれると移送グー)TG下を経て電荷
転送装置の転送電極夏1Fの電位の井戸19に移送され
る。さらに電荷転送装置の転送電極01.グg、 as
、ダ4に順次駆動バルヌが印加されると曲記信り一亀荷
は第2図+01の矢印方向へ転送された後、図25を省
略したが水平シフトレジスタへ移され、その後該水平シ
クトレジスタ内を転送されて出力増幅器に入り、その出
力増幅器で電圧に変換されて出力される。
When the incident light 17 enters the light receiving section 11, signal charges (electrons in this case) generated by photoelectric conversion in the light receiving section are transferred to a potential well 18 under the light receiving section 11 and the n-type impurity layer 16.
is temporarily accumulated. When the transfer gate (TG) is opened, the signal charge accumulated for a certain period of time is transferred to the potential well 19 of the transfer electrode summer 1F of the charge transfer device through the transfer gate (TG). Furthermore, the transfer electrode 01 of the charge transfer device. g, as
, when the driving signals are sequentially applied to D4, the load is transferred in the direction of the arrow +01 in FIG. 2, and then transferred to the horizontal shift register (not shown in FIG. 25); The voltage is transferred to the output amplifier, where it is converted to voltage and output.

なお、上述した受光素子11の出力端14と信号処理回
路素子の入力@15を電気的に接続するための不純物#
16を形成する一実施例を第4図を用いて説明する。
Note that impurity # for electrically connecting the output terminal 14 of the light receiving element 11 and the input @ 15 of the signal processing circuit element described above
An example of forming the device 16 will be described with reference to FIG.

通常半導体基板80の厚みは800μm程度であるが、
該基板80の一生面上80aの周辺の幅lを5sm轢度
残して化学研磨し、基板中央部の厚みdlを20μm程
度まで薄くする。さらに所定の位置に、例えば異方性エ
ツチング等の手法を用いて凹部81を設け、該四部81
の底部と池の一主面80bとの距jlidlを577 
m程度にする。しかる後に基板80と逆導電型の不純物
を深さ方向に6μm以と拡散することにより該基板に新
たに形成した一主面800と曲の一主面80bとを貫通
する拡散N182を容易に形成することができる。
Normally, the thickness of the semiconductor substrate 80 is about 800 μm,
The substrate 80 is chemically polished leaving a width l of 5 sm at the periphery of the surface 80a, and the thickness dl at the center of the substrate is reduced to about 20 μm. Furthermore, recesses 81 are provided at predetermined positions using a technique such as anisotropic etching, and the four portions 81 are
The distance jlidl between the bottom of the pond and one main surface 80b of the pond is 577
Make it about m. Thereafter, by diffusing impurities of a conductivity type opposite to that of the substrate 80 to a depth of 6 μm or more, a diffusion N182 penetrating the newly formed main surface 800 and the curved main surface 80b is easily formed in the substrate. can do.

なお、半導体基板80の周辺の輻lを6W程度初期の厚
みのまま分厚くしておく理由はウェハの取り扱いを容易
にするためである。
Incidentally, the reason why the radius around the semiconductor substrate 80 is kept as thick as about 6W at the initial thickness is to facilitate handling of the wafer.

前記のような凹部81の形成に異方性エツチングを採用
すれば四角踵状の凹部が形成できる。この場合Si基板
BOとしては(100)面のものを用い、四角踵状四部
を形成すべき領域以外の領域をホトレジストでマスキン
グした後、例えばHBO(水)とN5k14(ヒドラジ
ノ)の混合水溶液(例えば液温100℃)に浸漬せしめ
て基板80の露出部をエツチングすることにより(il
l)面が現われ、その結果81基板表面に頂部を基板深
さ方向に有する四角鍾伏凹部81が容易に形成される。
If anisotropic etching is employed to form the recess 81 as described above, a square heel-shaped recess can be formed. In this case, the (100)-plane Si substrate BO is used, and after masking the area other than the area where the square heel-shaped four parts are to be formed with photoresist, a mixed aqueous solution of HBO (water) and N5k14 (hydrazino), for example, By etching the exposed portion of the substrate 80 by immersing it in a liquid temperature of 100° C.
1) surface appears, and as a result, a rectangular protruding recess 81 having an apex in the depth direction of the substrate is easily formed on the surface of the substrate 81.

このように形成された四角踵状四部81の基板表面に対
する角度θは約65度(正確にはθ目54゜74度)と
なる・ なお、前述の実施例では受光素子にp −n接合を用い
九町視光用固体撮像装置について説明し九像装置にも有
効である。また基板の一生面上に信   ゛号処理回路
素子を形成するだけでなく、信す処理回路素子を駆動す
る駆動回路素子を形成することも可能である。
The angle θ of the square heel-shaped four portions 81 formed in this way with respect to the substrate surface is approximately 65 degrees (to be exact, the angle θ is 54 degrees and 74 degrees). In the above-mentioned embodiment, a p-n junction is provided in the light receiving element. The solid-state imaging device used for Kucho optical viewing will be explained, and it is also effective for Kuchin image devices. In addition to forming signal processing circuit elements on the entire surface of the substrate, it is also possible to form drive circuit elements for driving the signal processing circuit elements.

(2)発明の効果 以北、絆細に説明したように、本究明は半導体基板の一
生面上全面に受光素子を形成することができ集積度を飛
躍的KIt8iIJ:できるため、高解像度の固体撮像
装置を実現し得るという多大な効果を有する。
(2) Beyond the effects of the invention, as explained in detail, this research enables the formation of light-receiving elements on the entire surface of a semiconductor substrate, dramatically increasing the degree of integration. This has the great effect of realizing an imaging device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の固体撮像装置を説明するための(既、金
的な上面図、第2図(a)、(至)およびtc+は本発
明による固体撮像装置の単位構成を示す概略図、第8図
は本発明による8×8のマトリックス状に配列された固
体撮像装置の概念的な上面図、第4図は受光素子と借り
処理回路素子とを電気的に接続する拡散層を作る工程を
説明するための図である。 1.20:半導体基板、2,21:受光素子、10、8
0 : p型Sj−M板、ll:n型不純物層、12:
[荷堰、l 9 : 5ins、14,81:頂部を深
さ方向に有する凹部、16.22.$2:n型拡散層、
17二人射光。 第1図 第2図 第3図 U 第 4 図
FIG. 1 is a schematic top view for explaining a conventional solid-state imaging device; FIG. FIG. 8 is a conceptual top view of a solid-state imaging device arranged in an 8×8 matrix according to the present invention, and FIG. 4 is a process for creating a diffusion layer that electrically connects the light receiving element and the processing circuit element. 1.20: semiconductor substrate, 2, 21: light receiving element, 10, 8
0: p-type Sj-M plate, ll: n-type impurity layer, 12:
[Loading weir, l9: 5ins, 14,81: recess with top in depth direction, 16.22. $2: n-type diffusion layer,
17 Two people shooting light. Figure 1 Figure 2 Figure 3 Figure U Figure 4

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の一主面上に光電変換機能を有する受光素子
を配設し、池の一主面土に該受光素子からの信号電荷を
処理するだめの回路素子を配設し、かつ前記受光素子に
設けた信号電荷の出力端と前記回路素子にmll倍信号
電荷導入するための入力端とを電気的に接続するための
前記基板と逆導電型の不純物層を該基板をlK通して設
けたことを特徴とする固体機ll装置。
A light receiving element having a photoelectric conversion function is disposed on one main surface of a semiconductor substrate, a circuit element for processing signal charges from the light receiving element is disposed on one main surface of the pond, and the light receiving element An impurity layer having a conductivity type opposite to that of the substrate is provided through the substrate to electrically connect an output terminal for signal charges provided in the circuit element to an input terminal for introducing signal charges multiplied by millimeter into the circuit element. A solid-state device characterized by:
JP57071850A 1982-04-28 1982-04-28 Solid-state image pickup device Pending JPS58188968A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57071850A JPS58188968A (en) 1982-04-28 1982-04-28 Solid-state image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57071850A JPS58188968A (en) 1982-04-28 1982-04-28 Solid-state image pickup device

Publications (1)

Publication Number Publication Date
JPS58188968A true JPS58188968A (en) 1983-11-04

Family

ID=13472421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57071850A Pending JPS58188968A (en) 1982-04-28 1982-04-28 Solid-state image pickup device

Country Status (1)

Country Link
JP (1) JPS58188968A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106535A (en) * 1993-10-01 1995-04-21 Sharp Corp Photodetector and formation of photodetector
WO2004030102A1 (en) * 2002-09-24 2004-04-08 Hamamatsu Photonics K.K. Photodiode array and method for manufacturing same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106535A (en) * 1993-10-01 1995-04-21 Sharp Corp Photodetector and formation of photodetector
WO2004030102A1 (en) * 2002-09-24 2004-04-08 Hamamatsu Photonics K.K. Photodiode array and method for manufacturing same
JPWO2004030102A1 (en) * 2002-09-24 2006-01-26 浜松ホトニクス株式会社 Photodiode array and manufacturing method thereof
CN100399570C (en) * 2002-09-24 2008-07-02 浜松光子学株式会社 Photodiode array and method for manufacturing same
JP4554368B2 (en) * 2002-09-24 2010-09-29 浜松ホトニクス株式会社 Photodiode array and manufacturing method thereof
KR101087866B1 (en) 2002-09-24 2011-11-30 하마마츠 포토닉스 가부시키가이샤 Photodiode array and method for manufacturing same

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