JPS58188907A - Delay noise signal generator - Google Patents

Abstract

PURPOSE:To delay an output signal by giving an initial value a specific time later. CONSTITUTION:When a power source is turned on, an initial value setting circuit outputs the initial value K. The initial value K is supplied immediately to a random noise generating circuit 5 in M series. Consequently, an output signal O1 is obtained. The initial value K is supplied to multiplying circuits 51-5n via AND gates. Output signals of comparing circuits 41-4n are supplied to the other-side input terminals of the AND gates. When the counted value of corresponding counters 21-2n attain to a specific value, the AND gates are opened to supply the initial value K to the multiplying circuit. Therefore, the random noise generating circuit 51-5n output random noises in the same series as that appearing at a terminal O1 from terminals O2-On with specific time delay.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a combined signal generator with a long delay time and high accuracy.

A block diagram of a conventional delay noise signal generator is shown in FIG.

In FIG. 1, 11 is a multiplication circuit, 12 is an addition circuit, 1
3 is a mono-euro circuit, 14 is a conversion circuit, 15 is a memory circuit, 16 is an address control circuit, and 17 is an output circuit. Its action is that the initial value K obtained when the power is turned on is multiplied by the set value of the multiplier circuit in the multiplier circuit 11, and this result is added to the output of the monochrome circuit 13 in the adder circuit I2. 01 circuit 13, and generally outputs a 2n monochrome signal. .

The output of this mono-euro circuit 13 is known as M-sequence random noise, and the number is 33, which is a rank of uniform distribution.The conversion circuit 14 changes the number of uniform distributions to other distributions. Yes, it can be done simply by using ROM.

The memory circuit 15 stores the noise signal created in this way, records the output of the conversion circuit 14 at 18 hours, and reads it out to the output circuit 17 at time t1 by the address control circuit 16 to become the output OI. 1. The signal recorded in the address control circuit 16
is read out to the t2 time output circuit 17 and output 02.
Similarly, the output circuit 17 can only be obtained from the output ot.If you compare the output created in 17 with the output OL and the output 02, the signals are exactly the same, and the time output 02 is It is delayed by T2 + -12-1 from output 01. In this way, output 02 + 03 t ~ 0 has a signal characteristic that is completely cyclic compared to output O8, but the time is T21 + 31 + ~ T. It will only be delayed.

However, for example, T3+""αT21 (α is a suitable value '
j′, l number) T4. -αT31 + Tn, -αknee When trying to obtain the output of the relationship, Tol−αn
2T2. Assuming that α-2, T2I-1m8n-10, if l/ls is required as the precision of each output signal, the memory circuit 15 will require a time step of 256 x 105, which will require a large-scale circuit. 5. The present invention solves these conventional drawbacks and d) provides a delay time without using a memory circuit. The purpose is to obtain a noise signal with a long delay time and high accuracy using a small-scale circuit.

1: J, F An embodiment of the present invention will be described in detail with reference to the drawings. , Fig. 2 is a diagram showing one embodiment of the delay noise signal generator of the present invention, in which 1 is an initial value setting circuit, 2°~2 is a counter circuit, 3 is a timing setting circuit, and 41,~4 are a timing setting circuit. Comparison circuit, 5+51 r~5 is multiplier n

n path, 6+61t~6 is adder circuit, 7'+71
t~2n are mono-euro circuits, 8, 8I,~8 are conversion circuits, ri, 9. ．． -9 are output circuits. , Next, I will explain its operation. 1. First, when the power is turned on by the initial value setting circuit 1? /J
The FJI value K is obtained, and at the same time, the counter circuits 2I-2 count the operation 1-time. This output is compared with the value of the timing setting circuit 3 in comparison circuits 4I to 4n,
When the values become the same, the output of the initial value circuit I is added to the multiplier circuit 5I.

During this time, the input of the multiplier circuit 5 is multiplied by the set value, added to the adder circuit 6, and inputted to the mono-euro circuit 7. The first output of the mono-euro circuit 7 is inputted to the conversion circuit 8, and the output circuit 9 Then, the output O5 is obtained, but on the other hand, the output of the monochrome circuit 2 becomes the human power of the multiplier 5, passes through the adder circuit 6, and the monochrome circuit 7 to obtain the next output No. 11.

In this way, the output of the monochrome 7 starts from the initial value and becomes K(tl), .about.K(t,), obtaining uniformly distributed random noise, and the output signal OI becomes a highly distributed noise output.

Ichiriki, multiplication circuit 5. obtains the initial value K with a delay of the output time of the comparator circuit 4I, so the output signal o2 becomes K(
tl), ~pc(to), whose distribution is changed by using a conversion circuit 8' which is exactly the same as the conversion circuit 8.

Therefore, the output signal 02 is completely different from the output signal OI,
Moreover, it is delayed by the time set by the timing setting circuit 3. Similarly, the output signal On is also output (r).

At this time, multiplication circuit 5*51r~5, addition circuit 6゜61,~
6. Mono-Euro circuit 7! The clock pulses applied to 711-7 are all the same, and the counter circuit 21
Kuro, Ri, and Rus to be added to ~2 are Norihiro circuit 51, ~5,
Addition circuit 6 - 6, mono, use the clock signal applied to the circuits 71 - 7 divided by 1/T1. By applying a 1 μs clock pulse to the circuit and a 1 ms clock pulse to the counter circuit, a counter circuit and a comparison circuit can be constructed using several ICs. In this way, a noise signal with a long delay time and high accuracy can be obtained with a small-scale configuration without requiring a memory circuit. This has the effect of providing a reference delay noise generator with a long delay time and high accuracy. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional delay noise signal generator.
FIG. 2 shows the delay noise ff signal generation of the present invention -1J=, ? It is a block diagram which shows one example of %. l...Initial value setting circuit, 21-2...Color/tar circuit, 3...Timing nog setting circuit, 41-4...Comparison circuit, 5, 5I, ~5n...P, arithmetic circuit, 6+ 61
r~6...weighted calculation 0 circuit, 7+71+~7o...mono euro circuit, 8°8, 1~8n-conversion 1iJl path, 9.9+,~9o-output circuit・'B 1 1 sentence 1;+ : 2 Paragraph 1 Procedural Amendment (White I) : 1'J Cho-de-dou Tono-i 11 Table of Showa 5741 Special, 1'1 Application No. o '10'
2 Name of the invention d Pregnancy
1'l17? rTJ2 'J name (02) r'l'
+Ij '＜CI Industry Association 1 Representative Iris jlfll
Book Minami γ111 Men's office (〒105) Heavy industry;・Tokyo l! ! Utme!
, Zino-bar No. 51118, No. 4, II, No. 11. Detailed description of the invention in 11, page 11, and drawing 11. "Details-1 h l'l "17th line 11rs'" 1
-8- and Ura 11, Figure 2 of the 2 drawings are supplemented as attached.
[Zuro.

Claims (1)

[Claims] In the multiplier circuit, the initial value K is multiplied by the setting value of the multiplier circuit, and this output is added to the output of the mono circuit and the output circuit in the adder circuit. - In the H-type noise generator, which inputs power into the input circuit and converts the M-sequence random noise as its output into other noise generators using the conversion circuit, the initial value setting circuit allows the initial value K to be obtained as soon as the power is turned on. The circuit is configured to operate multiple counter circuits, each of which has a comparator circuit that compares its output with the value of the timing setting circuit, and when the values are the same, the output of the initial value circuit is added to the multiplier circuit of the noise generator. A delay noise γ?belief generator characterized by making the delay time ('t'j)