JPS5818835B2 - Shingokenshiyutsushiyutsuriyokuhoushiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal detection output method in a signal receiver,
In particular, it relates to a signal detection and output method that detects and outputs multi-frequency signals.

In general, multi-frequency signaling systems have been put to practical use in push-button dial telephone signaling systems, etc., and in such multi-frequency signaling systems, frequencies within the sound/voice band are used as multi-frequency signals.

Therefore, when receiving a multi-frequency signal, it is necessary to distinguish between the original multi-frequency signal and a pseudo signal such as voice mixed in from a transmitter or the like.

Additionally, if the Keio University signal is momentarily interrupted for several tens of milliseconds due to mechanically generated noise while the Cedar frequency signal is being received, the receiver will malfunction.

For this reason, conventionally, this type of receiver has a first time-limiting circuit that checks that the input signal continues for a certain period of time and distinguishes between multi-frequency signals and pseudo signals, and a A second time limit circuit is provided which maintains this state for a certain period of time even if the input signal is momentarily interrupted.

Further, the output circuit is provided with a third time limit circuit configured with a monostable multi-by-break circuit, and is configured to send out an output signal for a required time by this time limit circuit.

However, the signal detection output method using three timer circuits cannot be said to be simple in structure.

In particular, the time limit circuit for sending out the output signal is constituted by a monostable multi-pie break that requires transistors, which is economically disadvantageous.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal detection and output method that can prevent malfunctions and send output signals with a simpler configuration.

. Another object of the present invention is to provide an economical signal detection output system that does not require a monostable multi-bye break.

According to the present invention, a plurality of tuning circuits that receive a multi-frequency signal and tune to respective frequencies constituting the multi-frequency signal, and a plurality of rectifier circuits that rectify the outputs of the plurality of tuning circuits, respectively; a first timer circuit that receives an output from the rectifier circuit and delays it by a predetermined time; and a second timer circuit that receives an output from the rectifier circuit and delays recovery of the output by a predetermined time. a timed circuit; and the first and second circuits.
a first gate circuit that sends out an output when the output of the timer circuit is present; an information line that returns a part of the output of the first gate circuit to the input section of the first timer circuit; When the output power of the first gate circuit and the output power of the rectifier circuit ≦ exist, a plurality of second gate circuits that send out the output, and a part of the output of the second gate circuit are connected to the second gate circuit. A signal detection output system is obtained, which is configured by an information line that returns to the input section of the gate circuit.

In the present invention, by simply using the first and second timer circuits,
A simple and economical signal detection/output method can be obtained, which can distinguish between multi-frequency signals and pseudo signals, prevent instantaneous interruption of input signals, and send out output signals.

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a receiver receives a 4×4 multi-frequency signal.

An example of application to a signal device is shown.

Referring to FIG. 1, this embodiment includes tuning circuits 21 to 24, rectification circuits 31 to 34, OR circuits 101 to 104, and gate circuits 111 to 114, corresponding to four frequencies constituting a multifrequency signal. have.

. Further, an OR circuit 40 that receives the output of the rectifier circuit, and an AND circuit 50 that performs an AND with another frequency group (not shown) are provided.

Furthermore, in response to the output of the AND circuit 50, an OR circuit 60, 1' and 1', is used to prevent malfunctions and to send an output signal.

and second time limit circuits 70 and 80, and a gate circuit 90, and the output of the gate circuit 90 is fed back via an information line 71 to an OR circuit 60 provided on the input side of the first time limit circuit. I need work.

The first and second timer circuits 70 and 80 are cocidensors.

It is convenient to use a C'R integration circuit consisting of a resistor and a resistor.

Among these, the first timer circuit 70 receives the input signal from
On the other hand, the second time limit circuit 80 is configured to be activated after a certain period of time has elapsed after the end of the input signal.

FIG. 2 is a time chart for explaining the operation of FIG. 1.

In the figure, reference symbols a''-e indicate signal waveforms in corresponding portions of FIG. 1, respectively.

Referring to FIGS. 1 and 2, a signal waveform a applied to the input terminal 1 has a signal period t1 and a signal weight period t2, and a tuning circuit 21 corresponding to the frequency included in this waveform a
Tuning is achieved at ~24.

Since the tuning circuits 21-24 respond with a delay to the input signal, waveforms with delayed rising and falling edges are provided from the tuning circuits 21-24 to the corresponding rectifier circuits 31-34.

Therefore, the rectifier circuits 31-34 send out waveforms delayed by the rising delay time t3 of the tuning circuits 21-24 and delayed by the falling delay time t5 of the tuning circuits 21-24 with respect to the input waveform a.

This waveform is applied to an AND circuit 50 through an OR circuit 40 and ANDed with other frequency groups.The output of the AND circuit 50 is sent to a first timer circuit 70 via an OR circuit 60 and a second timer circuit 80
It is given directly to 4.

The first timer circuit 70 monitors the duration of the waveform corresponding to the output waveforms of the rectifiers 21 to 24, and the duration is 1
It checks that it is 4 or more and operates as shown in waveform C.

Therefore, this timer circuit 70 removes short-duration pseudo signals such as voices, while the second timer circuit 80 operates in response to the output of the AND circuit 50 as shown in waveform d. When the process ends, recovery is delayed by the minimum guaranteed time t6.

Additionally, the outputs of the first and second timer circuits 70 and q80 are provided to a gate circuit 90 which provides an output when both outputs are present.

The output signal e of this gate circuit 90 is fed back to the OR circuit 60 provided at the input part of the timer circuit 70 via the information line 71, and during the period when the output of the gate 1 circuit 90 is present, The timer circuit 7.0 can be held down.

1 Also, the outputs of the rectifier circuits 31 to 34 are logical profit candy 10
1 to 104, to gate circuits 111 to 114 operated by the output signal e of gate circuit 90.

One signal of the gate circuits 111 to 114 is transmitted to the gate circuits 111 to 11 while the output signal e of the gate circuit 90 is in the 0 state.
4, information lines 105 to 10 are connected to OR circuits 101 to 104 at the input parts of gate circuits 111 to 114.
8, respectively.

Therefore, each of the gate circuits 111 to 114 can send out an output signal having substantially the same waveform as the input signal.

In addition, the instantaneous interruption absorption time in this example is t5°+16
．． -17 (see Figure 2).

However, t7 indicates the rise delay time of the tuning circuit.

Here, t5=3ms, t6=45ms, t7=10
If it is m seconds, the instantaneous interruption absorption time will be 38 msec, and the instantaneous interruption of the input signal can be easily absorbed.

As described above, according to the present invention, an output signal having almost the same waveform as the input signal can be generated without using a monostable multi-byte break, which is required when the input signal is slightly longer than the input signal continuation check time. In addition, it is possible to prevent malfunctions with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment in which the present invention is applied to a receiver that receives 4×4 multi-frequency signals. 1... Input terminal, 21-24... Tuning circuit, 31-
34... Rectifier circuit, 40... OR circuit A, 50...
...AND circuit A, 60...OR circuit B, 70...
・Time limit circuit A, 80...Time limit circuit B, 90...Gate circuit A, 101-104...OR circuit C1111
~114...Gate circuit B, 121~124...
FIG. 2 is a time diagram for explaining the operation of FIG. 1.

Claims (1)

[Claims] 1. A plurality of tuning circuits that receive a multi-frequency signal and tune to each frequency of the multi-frequency signal, a plurality of rectifier circuits that rectify the outputs of the plurality of tuning circuits, and a plurality of rectifiers that are sent through the rectifier circuit. a first timer circuit that takes an input signal as an input signal and delays the input signal by a predetermined time; a second timer circuit located in parallel with the first delay circuit that delays the time;
and a first gate circuit that sends out an output when the output of the second timer circuit is present, and an information line that returns a part of the output of the first gate circuit to the input section of the first timer circuit. and a plurality of second gate circuits that receive the output of the first gate circuit and the output of each of the rectifier circuits and send out an output when both of the outputs are present; A signal detection output method comprising an information line that feeds back a portion of the output to the input section of each second gate circuit.