JPS58188127A - Semiconductor wafer - Google Patents

Semiconductor wafer

Info

Publication number
JPS58188127A
JPS58188127A JP57071988A JP7198882A JPS58188127A JP S58188127 A JPS58188127 A JP S58188127A JP 57071988 A JP57071988 A JP 57071988A JP 7198882 A JP7198882 A JP 7198882A JP S58188127 A JPS58188127 A JP S58188127A
Authority
JP
Japan
Prior art keywords
chip
area
chips
wafer
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57071988A
Other languages
Japanese (ja)
Inventor
Masahiro Ouchi
大内 雅弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57071988A priority Critical patent/JPS58188127A/en
Publication of JPS58188127A publication Critical patent/JPS58188127A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54406Marks applied to semiconductor devices or parts comprising alphanumeric information
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/5442Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448Located on chip prior to dicing and remaining on chip after dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To improve the efficiency of P/W test, assemblage, selection, etc. in forming chip areas on a semiconductor wafer by such an arrangement wherein an optional character or symbol containing information whereby each of chip areas can be distinguished from others is provided in each chip area. CONSTITUTION:In preparing a semiconductor integrated circuit, many chips having areas of diffusion, whring, etc. are formed by using a mask of quartz glass. At this time, in each of chips A11-A22, an area D of which size is of such a degree that will not give any influence on a functional area C of the chip is formed at such a corner outside the area C, and an optional character, symbol, etc. are provided in the area. By this arrangement, chips can be distinguished from outside, even if relative positions of chips are changed after they are scribed. Based on test information, it also becomes possible not only to distinguish good chips from bad ones, but also to classify good ones in ranks, and production efficiency can be improved.

Description

【発明の詳細な説明】 本発明は、半導体ウエノ)−に*!り、%にウエノ1−
のチップとなる領域に各々識別情報が設けられている半
導体ウニ/”t−に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides semiconductor ueno)-! % Ueno 1-
This invention relates to a semiconductor urchin/"t-" in which identification information is provided in each region that becomes a chip.

現在、半導体の製造は、m数の3〜5インチ角のガラス
マスクを使用し、シリコ/つ、バー上に塗布されたレジ
ストを紫外線等で感光し、感光されない部分を除去しく
ネガレジスト)、又は感光した部分を除去しくポジレジ
スト)残ったレジメトtマスクにして作られた酸化膜を
マスクにして不純物を拡散し、P型およびN型半導体を
製造し、アルはニウム、ポリシリコン等で配線を行ない
半導体集積回路を製造している。
Currently, semiconductor manufacturing uses a 3 to 5 inch square glass mask to expose the resist coated on the silicon bar to ultraviolet rays, etc., and remove the unexposed areas (negative resist). (or remove the exposed areas (positive resist)) Use the remaining oxide film as a mask to diffuse impurities to produce P-type and N-type semiconductors, and interconnect with Al, Ni, polysilicon, etc. The company manufactures semiconductor integrated circuits.

電子ビーム露光装置を使用した場合は、ガラスマスクの
代りKli接電子電子ビームェノ・−上のレジストを感
光させる事を除けば拡散、配線の工程はガラスマスクの
場合と同じである。
When an electron beam exposure apparatus is used, the diffusion and wiring processes are the same as those for the glass mask, except that the resist on the Kli-contact electron beam is exposed instead of the glass mask.

拡散、配線等のすべての工程を終了したウェハーは、ウ
ェハーの状態でLSIテスター、プロパー等でP/Wテ
ストされ不良のチップは何らかの印がつけられスクライ
プ後組み立て時に良、不良品の区別がつくようになって
いる。
After completing all processes such as diffusion and wiring, the wafer is subjected to a P/W test using an LSI tester, proper, etc., and defective chips are marked with some kind of mark, so that it is possible to distinguish between good and defective chips when assembling them after scribing. It looks like this.

lチップ1回路(1機能)の場合は、何らかの印をつけ
ても問題はないが、lチップ2回路以上(2機能以上)
あって複数の回路のうちいくつかが良品であれば、その
チップは組み立てて使用できる。この場合、ウェハー上
の座標とチップ上のどの回路が良品かを把掴する必要が
ある。この情報を得るにはウェハーマツピング等の機能
を有するテスターおよびプローバーを使用すれば良い。
If the l chip has one circuit (one function), there is no problem with adding some kind of mark, but if the l chip has two or more circuits (two or more functions)
If some of the circuits are good, the chip can be assembled and used. In this case, it is necessary to know the coordinates on the wafer and which circuits on the chip are good. To obtain this information, a tester and a prober having functions such as wafer mapping may be used.

しかしこのようにしても、ウェハーをスクライプして各
々の相対位置が変化してしまうと、各チップがウェハー
上でどの位置にTo−)たものがわからなくなる。
However, even with this method, if the relative positions of each chip change as the wafer is scribed, it becomes impossible to know where each chip is located on the wafer.

本発明の目的Fi、このような従来の欠点のない半導体
ウェハーを提供することにある。
An object of the present invention is to provide a semiconductor wafer that does not have these conventional drawbacks.

本発明の他の目的は、半導体集積回路装置の製造におい
てP/Wテスト、組み立て1選別等の効率を上げる半導
体集積回路装置の製造方法を4!!供することにある。
Another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that increases the efficiency of P/W testing, assembly 1 selection, etc. in the manufacturing of semiconductor integrated circuit devices. ! It is about providing.

本発明の特徴は、半導体ウェハーにおいて、ウェハー上
に製造された各チップ領域を区別できる情報を含む任意
の文字、記号等を各チップ上に有する半導体ウェハーに
ある。このテップ上の情報にはウェハー上でのチップの
位置の区別も可能な情報を含ませることがで龜る。また
、ζO?yプ上の情報はウェハーごとの区別も可能な情
報や。
A feature of the present invention resides in a semiconductor wafer in which each chip has arbitrary characters, symbols, etc. containing information that can distinguish each chip region manufactured on the wafer. It is possible to include information on this chip that can also distinguish the position of the chip on the wafer. Also, ζO? The information on the YP is information that can be distinguished by wafer.

製造年月日の区別も可能な情報を含ませる仁とができる
It is possible to include information that allows the date of manufacture to be distinguished.

次に本発明の実施例について図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.

第1図は5石英ガラスを用いた半導体集積回路製造用マ
スクの一例であり、全工程の一部を本マスクで製造し、
かつ本マスクにより製造された部分は、拡散配線等の全
工程が終了した時点で外部から見えるものである。この
工程の例は、アルオニウム、ポリ/リコ/等の被着工程
である。また。
Figure 1 shows an example of a mask for manufacturing semiconductor integrated circuits using 5-quartz glass, and a part of the entire process is manufactured using this mask.
In addition, the portion manufactured using this mask is visible from the outside when all processes such as diffusion wiring are completed. Examples of this process are Alonium, poly/lico/etc. deposition processes. Also.

第1図のAII + A12 r・・・・・・Aij・
・印・A77の各チップの機能にすべて同一のものとす
る。第2図は第1図の各ナツプパター/(Aij)を拡
大したものであるが、このナツプパター/のD領域にA
ljの位[=示す記号又は文字がマスク製造時に半導体
集積回路としての機能を有する領域Cに何ら影響を与え
ない程度の大きさで書かれている。本実施例で1第3図
に示した様にA、 2示す「 1」か領域D′にマスク
製造時に書かれている。
AII + A12 r...Aij・ in Figure 1
・The functions of each chip marked ・A77 shall all be the same. Figure 2 is an enlarged view of each nap putter / (Aij) in Figure 1.
The symbol or character in the lj digit [= is written in such a size that it does not have any effect on the area C that functions as a semiconductor integrated circuit during mask manufacturing. In this embodiment, as shown in FIG. 3, "1" is written in areas A and D' shown in FIG. 3 at the time of mask manufacturing.

また、領域D′の位置および文字、記号の太ききは半導
体集積回路設計者が任意に決めることができる様になっ
ている。本マスクを使用して半導体集積回路を製造した
場合、ウェハー上には各チップ、の位置を示す文字が残
り、スクライプ後に各ウェハーの相対位置が変っても外
部から識別がつく。
Further, the position of the region D' and the thickness of the characters and symbols can be arbitrarily determined by the semiconductor integrated circuit designer. When a semiconductor integrated circuit is manufactured using this mask, letters indicating the position of each chip remain on the wafer, and even if the relative position of each wafer changes after scribing, it can be identified from the outside.

第4図は、を子ビーム露光装置を使用してウェハー上に
直接パター/を書いた例である。この場合も前記石英ガ
ラスマスクを使用した時と同様にウェハー上に#′i、
各チップの位置を示す情報が電子ビーム無光時に書かれ
る。この時、位置を示す文字、記号の位置および大きさ
はチップ上の半導体集積回路の機能に影響を与えない様
に任意に決める。
FIG. 4 shows an example in which a pattern is written directly on a wafer using a beam exposure device. In this case as well, #'i,
Information indicating the position of each chip is written when the electron beam is off. At this time, the position and size of the characters and symbols indicating the position are arbitrarily determined so as not to affect the function of the semiconductor integrated circuit on the chip.

第5図は、ステッパーを用いる時に使用するデツ7’ 
パター/を10倍に拡大したレティクルであるが、この
場合は、第5図のD領域を透明にしておいてステッパー
が各チップのパターンを投影していく時点でDめ透明な
領域を通して位置を示す情報を投影していく。ただ位置
情報を半導体製造用レティクルの投影とは別に行なう場
合は、Dの領域を不透明にして光が透過しない様にして
お(。
Figure 5 shows the step 7' used when using a stepper.
This is a reticle that magnifies the putter by 10 times, but in this case, the D area in Figure 5 is made transparent, and when the stepper projects the pattern of each chip, the position is determined through the D transparent area. The information shown will be projected. However, if position information is to be projected separately from the projection of a reticle for semiconductor manufacturing, the area D should be made opaque so that no light passes through.

以上の実施例は共に人間が目でMRできる文字。Both of the above examples are characters that can be read by human eyes.

記号をウェハー上に半導体集積回路製造時に作ったもの
であるが、この位置情報を示す文字、記号はパターン飴
識等の機能を有する自動組み立て装置を使用する場合は
、パター/認識装置が識別できるパターン金ウェハー上
に作ればよい。この実施例を飢6図に示す。第6図にお
いて、人はプローバー、L8I テスター、BViスク
ライブ処理、Cは自動組み立て装置、Dはデータ処理お
よびパターン認識等を行なう情報処理装置である。A。
Symbols are created on wafers during the manufacture of semiconductor integrated circuits, but when using automatic assembly equipment with functions such as pattern recognition, the characters and symbols indicating this positional information can be identified by putter/recognition equipment. The pattern can be made on a gold wafer. This example is shown in Figure 6. In FIG. 6, person is a prober, L8I tester, BVi scribe processing, C is an automatic assembly device, and D is an information processing device that performs data processing, pattern recognition, etc. A.

C,DI4お互いにバスで接続されていてデータの受授
が可能になっている。実際の処理方法は以下のようにな
る。
C and DI4 are connected to each other by a bus and can receive and receive data. The actual processing method is as follows.

LSIテスタープロパーでP/Wテストされたウェハー
は、そのウェハー上の位置情報、および良。
A wafer that has been P/W tested with the LSI tester proper has position information on the wafer, and whether the wafer is good or not.

不良、良品のランク等の情報を情報処理装置に送る。次
KBのスクライプ処理されたウェハーはCの組み立て装
置へ送られるが、この過程でガラスマスクを使用して製
造されたウェハーならばウェハ一単位で処理順序を管理
しておけばDに保存されているテスト情報音もとにして
良、不良のみならず良品のランク付まで可能になり従来
は1組み立て作業が終了してから行なっていたランク付
の時間が不必用になりテスト時間の短縮にもなる。
Information such as the rank of defective and non-defective products is sent to the information processing device. The next KB's scribed wafer is sent to the assembly device at C, but if the wafer is manufactured using a glass mask during this process, it can be stored at D if the processing order is managed for each wafer. It is now possible to rank not only good and bad products but also non-defective products based on the test information sound, which eliminates the need for ranking time, which was traditionally done after completing one assembly task, and can also shorten test time. Become.

電子ビーム露光やステッパーを使用した時は。When using electron beam exposure or a stepper.

ウェハーごと、製逸年月日ごとに各チップを区別する情
報をチップ上に作ることが可能であるから、ウェハーご
との管理も不必要となる。
Since it is possible to create information on each chip to distinguish each chip by each wafer and each manufacturing date, there is no need to manage each wafer.

また同一チップ内に複数の機能を有する回路が存在する
場合、第6図の装置を使用することにより良品の回路の
部分のみの組例立て等の作業も自動的に行なえることに
なる。
Further, when there are circuits having multiple functions in the same chip, by using the apparatus shown in FIG. 6, it is possible to automatically perform tasks such as assembling only the non-defective parts of the circuit.

第6図の装置がない場合でも、チップ上に人間がそのウ
ェハーの位置をamできゐパターンを作っておけば、ウ
ェハーマツピングの機能と併用して。
Even if you do not have the device shown in Figure 6, if you create a pattern on the chip that allows a person to map the wafer position, you can use it in conjunction with the wafer mapping function.

複数の機能を有する回路の食品の部分のみの選別も従来
よりも早く行なうことができる。
It is also possible to select only the food portion of a circuit with multiple functions faster than before.

本発明は、以上説明したように半導体集積回路ウェハー
上の各チップにそのチップのウェハー上での位償情報を
持つ任意の文字で半導体集積回路製造時に作ることによ
り P/wテスト、組み立て選別等の効率が上がる効果
がある。
As explained above, the present invention enables each chip on a semiconductor integrated circuit wafer to be printed with arbitrary characters having compensation information for that chip on the wafer at the time of semiconductor integrated circuit manufacturing. This has the effect of increasing efficiency.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例に用いる石英ガラスマスク
であり、本マスクで全工程の特定の工程を製造する。第
2図は、第1図の1つのチップパター/A4 Jf取り
出したものでD領域にマスク上での位f1/11に示す
特定のパター/が書かれている。 w、3図Fi第2図のDの部分を拡大したもので、この
例ではA3.にあるチップであることを示すために「ヨ
1」のパター/が書かれている。 第4図は、を子ビーム喜光装置を用いてウェハー上にパ
ター/を書いて作られたウェハーを示しており、各チッ
プには、その位fitを示す情報が作られている。 m5図はステッパー2使用するための10倍のレティク
ルでD@域が透明になっている。 第6図はLSIのP/Wから組み立てtlつの装置とし
たものでA・・・・・・プロパー、LSIテスター。 B・・・・・・スクライブ処理、C・川・・自動組み立
て機。 D・・・・・・情報処理装置である。 第1図 第3図 第4図 第5図
FIG. 1 shows a quartz glass mask used in one embodiment of the present invention, and a specific step of the entire process is manufactured using this mask. FIG. 2 shows one chip pattern /A4 Jf taken out from FIG. 1, and a specific pattern / shown at position f1/11 on the mask is written in the D area. w, Figure 3Fi is an enlarged view of the part D in Figure 2, and in this example, it is A3. ``Yo 1'' putter/ is written to indicate that the chip is located on the tip. FIG. 4 shows a wafer made by writing a pattern on the wafer using a beam-forming device, and information indicating the fit is created on each chip. The m5 diagram is a 10x reticle for use with stepper 2, and the D@ area is transparent. Figure 6 shows two devices assembled from LSI P/W.A...proper, LSI tester. B...Scribe processing, C...Automatic assembly machine. D... Information processing device. Figure 1 Figure 3 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェハーにおいて、鋏りエノ\−に製造された各
チップ領域を各々区別できる情報を含む任意の文字、記
号が該各チップ領域上に各々設けられていることを特徴
とする半導体ウニノー−0
A semiconductor wafer characterized in that arbitrary characters and symbols containing information for distinguishing each chip region manufactured using scissors are provided on each chip region.
JP57071988A 1982-04-28 1982-04-28 Semiconductor wafer Pending JPS58188127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57071988A JPS58188127A (en) 1982-04-28 1982-04-28 Semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57071988A JPS58188127A (en) 1982-04-28 1982-04-28 Semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS58188127A true JPS58188127A (en) 1983-11-02

Family

ID=13476346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57071988A Pending JPS58188127A (en) 1982-04-28 1982-04-28 Semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS58188127A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123417A (en) * 1990-09-14 1992-04-23 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123417A (en) * 1990-09-14 1992-04-23 Toshiba Corp Semiconductor device

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