JPS58187143U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS58187143U
JPS58187143U JP8480282U JP8480282U JPS58187143U JP S58187143 U JPS58187143 U JP S58187143U JP 8480282 U JP8480282 U JP 8480282U JP 8480282 U JP8480282 U JP 8480282U JP S58187143 U JPS58187143 U JP S58187143U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
standard
corresponds
standardization
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8480282U
Other languages
Japanese (ja)
Inventor
信和 岩瀬
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP8480282U priority Critical patent/JPS58187143U/en
Publication of JPS58187143U publication Critical patent/JPS58187143U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図、第２図は、本考案の一実施例の構成図である。 図において、１・・・・・・ペレット、２〜４・・・・
・・アルミニウムのパターン、５〜７・・・・・・規格
を示すアルミニウムのパターン、８〜１０・・・・・・
針である。FIGS. 1 and 2 are configuration diagrams of an embodiment of the present invention. In the figure, 1...pellet, 2-4...
... Aluminum pattern, 5 to 7 ... Aluminum pattern indicating the standard, 8 to 10 ...
It's a needle.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 性能の違いによって規格分けを必要とする半導体装置に
於て、前もって規格に対応した金属層のパターンを備え
、特性チェック時に、前記規格に対応した該パターンに
キズを付け、ウェハー状態での規格分けが出来るように
した事を特徴とした半導体装置。For semiconductor devices that require standardization due to differences in performance, a metal layer pattern that corresponds to the standard is prepared in advance, and when checking the characteristics, the pattern that corresponds to the standard is scratched, and the standardization is performed in the wafer state. A semiconductor device characterized by being able to perform.
JP8480282U 1982-06-08 1982-06-08 semiconductor equipment Pending JPS58187143U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8480282U JPS58187143U (en) 1982-06-08 1982-06-08 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8480282U JPS58187143U (en) 1982-06-08 1982-06-08 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS58187143U true JPS58187143U (en) 1983-12-12

Family

ID=30093724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8480282U Pending JPS58187143U (en) 1982-06-08 1982-06-08 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS58187143U (en)

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