JPS58187025A - Not device used in alternating current - Google Patents
Not device used in alternating currentInfo
- Publication number
- JPS58187025A JPS58187025A JP7238682A JP7238682A JPS58187025A JP S58187025 A JPS58187025 A JP S58187025A JP 7238682 A JP7238682 A JP 7238682A JP 7238682 A JP7238682 A JP 7238682A JP S58187025 A JPS58187025 A JP S58187025A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- power supply
- input signal
- oscillation circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/007—Fail-safe circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、両極性パルスの入力信号が到来し几時に発振
回路による発振を停止させ、該入力信号が断xnた時に
発振回路の発振を引き起す工うにし几交流NOT装置に
関するもので、安全装置等ロジックの7エイルセーフ設
計に用いて好適ならしめたちのである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for stopping oscillation in an oscillation circuit when a bipolar pulse input signal arrives, and causing the oscillation circuit to oscillate when the input signal is interrupted. It relates to NOT devices and is suitable for use in 7-fail safe designs of logic such as safety devices.
従来、この糧の装置として第1図に示すものがあつ几。Conventionally, the device shown in Figure 1 has been used to provide this food.
図において(1)は両極性パルスの入力信号(以下入力
信号で略称す)が1次巻線に入力するトランス、(2)
は該トランス(1)の2次側に設けられ、その2次側出
力によってオンオフ制御さnるトランジスタ Trとコ
ンデンサ C工からなる入力信号処理回路、(8)は抵
抗、(4)は電源電圧の供給をうけて発振する。ゲート
G□* G@* Gjl 及び抵抗R工、R8とコン
デンサ C3とからなる発振回路、(5)は電源を示し
、こnら構成による従来例の動作を第2図に示す動作波
形図に基いて以下説明する。In the figure, (1) is a transformer in which a bipolar pulse input signal (hereinafter referred to as input signal) is input to the primary winding; (2)
is an input signal processing circuit that is provided on the secondary side of the transformer (1) and is controlled on/off by the output of the secondary side, consisting of a transistor Tr and a capacitor C, (8) is a resistor, and (4) is a power supply voltage. It oscillates when supplied with . An oscillation circuit consisting of gate G□* G@* Gjl, resistor R, R8 and capacitor C3, (5) indicates a power supply, and the operation of the conventional example with these configurations is shown in the operating waveform diagram shown in Fig. 2. The following is an explanation based on this.
すなわち、第1図構成において、第2図Aに示す入力信
号がトランス(1)の1次巻線に入力すると。That is, in the configuration of FIG. 1, when the input signal shown in FIG. 2A is input to the primary winding of the transformer (1).
該トランス(1)の2次巻線にペースが接続さnた入力
信号処理回路(2)のトランジスタ T は該入力信号
に基いて流nるベース電流(第2図B参照)に動作制御
さnてスイッチング動作をすると共に。The transistor T of the input signal processing circuit (2) whose pace is connected to the secondary winding of the transformer (1) is controlled in operation by the base current (see FIG. 2B) flowing based on the input signal. It also performs switching operations.
該トランジスタ Trのコレクタ・ニオツタ間に並列接
続さnて電源(6)からの電圧供給により充電されるコ
ンデンサ C□は、上記トランジスタ Trのスイッチ
ング動作により第2図Cに示す如く充電電圧の充放電を
繰り返すことになり発振回路(4)のゲー)C)工に供
給する電圧を所定の動作電圧■8以下とする。すなわち
、入力信号処理回路(2)は入力信号の到来時は発振回
路(4)による発振(第2図り参照)を停止させる。A capacitor C□ connected in parallel between the collector and the capacitor of the transistor Tr and charged by the voltage supplied from the power supply (6) is charged and discharged with a charging voltage as shown in FIG. 2C by the switching operation of the transistor Tr. As a result, the voltage supplied to the gate (C) of the oscillation circuit (4) is set to a predetermined operating voltage (8) or lower. That is, the input signal processing circuit (2) stops the oscillation (see the second diagram) by the oscillation circuit (4) when the input signal arrives.
一方、入力信号が第2図に示す時刻 t工て断たn九時
(第2図A診照)Kは、入力信号処理回路(2)のトラ
ンジスタ Trはベース電流(第2図B参照)の供給が
断九れてOFF状態となり、コンディサ Cユは所定の
電源電圧まで充電さn続は上記ゲー)G□(A)への供
給電圧は動作電圧 V、 (第2図C参照)以上となり
、こnKより発振回路(4)は第2図りに示さnるよう
に発振することになる。On the other hand, at 9 o'clock when the input signal is cut off at the time shown in Figure 2 (see Figure 2A), K is the transistor of the input signal processing circuit (2), and Tr is the base current (see Figure 2B). The supply voltage to G□ (A) is cut off and it becomes OFF state, and the conditioner C is charged to the specified power supply voltage. From this nK, the oscillation circuit (4) oscillates as shown in the second diagram.
しかるに、従来の交流NOT装置は以上の工うに構成さ
nているので、構成部品が故障した場合には誤まった論
理で出力することがあり、充分な7エイルセー7設計が
出来なかった0例えば入力信号処理回路(2)及び発振
回路(4)におけるコンデンサC工、C1の短絡事故或
いは抵抗(8)の断線事故によって生ずる発振回路(4
)の発振停止とが、またはトランス(x)、トランジス
タTHのコレクタ断線事故時に入力信号の如伺に拘らず
発振回路(4)が発振を継続するという不都合がともな
って十分なフェイルセーフが行ない得ない欠点があった
。However, since conventional AC NOT devices are configured in the manner described above, if a component fails, the output may be based on incorrect logic, making it impossible to create a satisfactory design. Oscillation circuit (4) caused by short-circuit accident of capacitor C, C1 or disconnection of resistor (8) in input signal processing circuit (2) and oscillation circuit (4).
), or the oscillation circuit (4) continues to oscillate regardless of the input signal in the event of a breakage accident in the collector of the transformer (x) or transistor TH. There were no drawbacks.
そこで、本発明は、上記のような従来のものの欠点を除
去するためになさnたもので、入カ信号t−直流に整流
して直流電圧を発生させると共に。Therefore, the present invention was devised to eliminate the above-mentioned drawbacks of the conventional system, and it rectifies the input signal t to direct current to generate a direct current voltage.
この発生電圧をもって発振回路に供給さnる電源電圧を
制御することによって、構成部品に故障が生じた場合、
発振回路を特定の状態に保持するようにして従来例の欠
点を解消し、かつ7エイルセー7設計を実施するに容易
なる交流NOT装置を提供することを目的としている。By controlling the power supply voltage supplied to the oscillation circuit using this generated voltage, if a failure occurs in a component,
It is an object of the present invention to provide an AC NOT device which eliminates the drawbacks of the conventional example by holding an oscillation circuit in a specific state, and which makes it easy to implement a 7-eliminate-7 design.
以下、本発明の一実施例を従来例の第1図と同一部分は
同一符号を符し几第3図で説明する。図において(6)
は2次巻線には中性点を設け1次巻線に入力信号が入力
するトランス、(γ)は整流ダイオードD工、D、及び
抵抗R5からなる本発明の入力信号処理回路で、この入
力信号処理回路は、両極性パルスが入力し九時に所定の
電圧を発生して、その発生電圧に裏って上記発振回路(
4)の入力端への供給電圧上零電位ま友は負電位とし1
発振回路(4)を発振制御する工うになさnている。Hereinafter, one embodiment of the present invention will be described with reference to FIG. 3, in which the same parts as in FIG. 1 of the conventional example are denoted by the same reference numerals. In the figure (6)
is a transformer in which a neutral point is provided in the secondary winding and an input signal is input to the primary winding, and (γ) is an input signal processing circuit of the present invention consisting of a rectifier diode D, D, and a resistor R5. The input signal processing circuit generates a predetermined voltage at 9 o'clock when a bipolar pulse is input, and the above-mentioned oscillation circuit (
4) The zero potential on the supply voltage to the input terminal of 1 is assumed to be a negative potential.
There is no way to control the oscillation of the oscillation circuit (4).
すなわち、上記構成に係る動作を第4図に示す波形図に
基いて説明すると、先ず、入力信号(第2図C参照)が
トランス(6)の1次巻線に入力したときには、該トラ
ンス(6)の2次巻線に接続した入力信号処理回路(γ
)の整流ダイオードD□、D8 によってその入力信
号は直流に整流さnて、抵抗R1に電圧降下を生じせし
めることになる。この場合。That is, the operation of the above configuration will be explained based on the waveform diagram shown in FIG. 4. First, when the input signal (see FIG. 2 C) is input to the primary winding of the transformer (6), 6) Input signal processing circuit (γ
), the input signal is rectified into direct current by the rectifier diodes D□, D8, which causes a voltage drop across the resistor R1. in this case.
七の発生電圧(第4図E)は予め絶対値で電源(5)の
電圧以上となるように設定さnていて、電源(5)と抵
抗R5の電圧降下の代数和が発振回路(4)の電源電圧
として供給さnその供給電圧(第4図F)は零ま次は負
電位となるため、こnKより発振(ロ)路(4)は発振
しない(第4図D)。すなわち入力信号が供給さnてい
る限りは交流信号が出力さnないのでNOTの論理%H
I入力に対する論理%Ll出力に対応する。The generated voltage (Fig. 4 E) is set in advance so that its absolute value is higher than the voltage of the power supply (5), and the algebraic sum of the voltage drops of the power supply (5) and the resistor R5 is the voltage of the oscillation circuit (4). ) is supplied as a power supply voltage (FIG. 4F), which becomes a negative potential after zero, so that the oscillation (B) path (4) does not oscillate from this nK (FIG. 4D). In other words, as long as the input signal is supplied, the AC signal will not be output, so the NOT logic %H
Corresponds to logical %Ll output for I input.
一方、入力信号の供給が第4図に示す時刻tよて断几n
、 fC場合には、抵抗R5の電圧降下は零(第4図Z
)であるため1発振回路(4)には電源(6)の電源′
1圧が供給(第4図F)さnることになシ、この状態で
は発振回路(4)は発振を継続(第4図D)することに
なる。すなわち、入力信号が断几nている限りは、交流
信号が出力されるのでNOTの論理%LI入力に対する
論理%lI#出力に対応することになる。On the other hand, the input signal supply is interrupted at time t shown in FIG.
, fC, the voltage drop across resistor R5 is zero (Fig. 4 Z
), the 1 oscillation circuit (4) has the power supply (6)'
1 pressure is supplied (FIG. 4F), and in this state, the oscillation circuit (4) continues to oscillate (FIG. 4D). That is, as long as the input signal is uninterrupted, an AC signal is output, which corresponds to the logical %lI# output for the logical %LI input of NOT.
なお、上記実施例では電源(5)と入力信号による抵抗
Raの電圧降下を直列状態で比較するようにして入力信
号処理回路全構成したが、第5図に示す工うに、整流ダ
イオードDユ、へ を第6図のものとは逆方向に用いト
ランス(6)の2次側で中性点をアースとして整流回路
を構成し、さらに抵抗R4を付加して上記抵抗R3は整
流回路の出力側に直列接続し、抵抗R4は電源(5)に
直列接続させて両抵抗の接続点で上記発振回路(4)に
電源電圧を供給するようにして、すなわち接軸電位を基
準にし抵抗R,,R,を用いて並列な関係が比較した電
圧を供給する工うに入力信号処理回路(8)を構成して
も上記実施例と同様の効果が得らrする。In the above embodiment, the entire input signal processing circuit was constructed so as to compare the voltage drop across the resistor Ra caused by the power supply (5) and the input signal in series. However, in the structure shown in FIG. To is used in the opposite direction to the one in Figure 6, a rectifier circuit is constructed with the neutral point grounded on the secondary side of the transformer (6), and a resistor R4 is added, and the above resistor R3 is connected to the output side of the rectifier circuit. The resistor R4 is connected in series with the power supply (5), and the power supply voltage is supplied to the oscillation circuit (4) at the connection point of both resistors. Even if the input signal processing circuit (8) is configured to supply the voltages compared in parallel using R, the same effect as in the above embodiment can be obtained.
以上の二うに本発明に工nは、両極性パルスが入力し几
時に上記直流を詠から上記発振回路に供給する電源電圧
を動作電圧以下として発振回路Vこよる発振を停止させ
ると共に、該両極性ノくルスが断たn九時には上記発振
回路に上記直流電源から所定の動作電圧を供給するよう
にして発振させる入力信号処理回路?1人カドランスの
2次側に接続し九整流ダイオードと、該整流ダイオード
に流れる電流の経路に設けらnlかつ上記直流電源から
発振回路に供給さnる電源電圧の供給路に介在さnて、
上記両極性パルスが入力した時に所定の電圧を発生して
、その発生電圧によって上記発振回路の入力端への供給
電圧を零電位ま友は負電位とする抵抗体とで構成したの
で、故障率の低い部品を用い、かつ回路が簡単に構成で
きて信頼性の高い交流NOT装置が得らnる効果がある
。As described above, the present invention has a feature that when a bipolar pulse is input, the power supply voltage supplied from the direct current to the oscillation circuit is lower than the operating voltage to stop the oscillation caused by the oscillation circuit V, and the bipolar pulse is input to the oscillation circuit. An input signal processing circuit that causes the oscillation circuit to oscillate by supplying a predetermined operating voltage from the DC power supply to the oscillation circuit at 9 o'clock when the sexual power is cut off? a rectifier diode connected to the secondary side of the one-person quadrant; and a rectifier diode provided in the path of the current flowing through the rectifier diode, and interposed in the supply path of the power supply voltage supplied from the DC power supply to the oscillation circuit;
Since it is constructed with a resistor that generates a predetermined voltage when the above-mentioned bipolar pulse is input, and the generated voltage changes the voltage supplied to the input terminal of the oscillation circuit from zero potential to negative potential, the failure rate is reduced. This has the effect of providing a highly reliable AC NOT device that uses components with a low cost and that has a simple circuit structure.
第1図は従来の交流NO?装置を示す回路図、第2図は
その動作図、第5図は本発明の一実施例による交流NO
T装置を示す回路図、第4図はその動作波形図、第5図
は本発明の他の実施例による交流NOT装置を示す回路
図である。
(131(6): )ランス
(2) # (7) # (8) :入力信号処理回路
(8):抵抗 (4):発振回路(6):電
源
図中、同一符号は同一部分ま友は相当部分を示す。
代凰人 葛 野 信 −
筆1図
第3図
第2図
■
I
第4図
;
峙翫・Xt
1Figure 1 shows the conventional AC NO? A circuit diagram showing the device, FIG. 2 is its operation diagram, and FIG. 5 is an AC NO according to an embodiment of the present invention.
FIG. 4 is a circuit diagram showing the T device, FIG. 4 is an operating waveform diagram thereof, and FIG. 5 is a circuit diagram showing an AC NOT device according to another embodiment of the present invention. (131 (6): ) Lance (2) # (7) # (8) : Input signal processing circuit (8): Resistor (4): Oscillator circuit (6): In the power supply diagram, the same symbols indicate the same parts. indicates a considerable portion. Daiouin Shin Kuzuno - Brush 1 Figure 3 Figure 2 ■ I Figure 4; Chikan/Xt 1
Claims (1)
路と、両極性パルスが入力さnるトランスの2次側に設
けられて、該両極性パルスが入力し友時に上記直流電源
から上記発振回路に供給する電源電圧を動作電圧以下と
して発振回路による発振を停止させると共に、該両極性
パルスが断tne時には上記発振回路に上記直流電源か
ら所定の動作電圧全供給するようにして発振させる入力
信号処理回路とをlえ友交流NOT装置において。 上記入力信号処理回路を、上記トランスの2次側に接続
し次整流ダイオードと、該整流ダイオードに流nる電流
の経路に設けらn、かつ上記直流電源から発振回路に供
給さnる電源電圧の供給路に介在さnて、上記両極性パ
ルスが入力した時に所定の電圧を発生して、その発生電
圧によって上記発振回路の入力端への供給電圧を零電位
ま之は負電位とする抵抗体とで構成し友ことを特徴とす
る交流NOT装置。[Claims] An oscillation circuit that oscillates when supplied with a power supply voltage from a DC power source, and a transformer that is provided on the secondary side of a transformer to which bipolar pulses are input, The power supply voltage supplied from the DC power supply to the oscillation circuit is set to be lower than the operating voltage to stop the oscillation circuit, and when the bipolar pulse is cut off, the oscillation circuit is supplied with the full predetermined operating voltage from the DC power supply. In an AC NOT device, an input signal processing circuit that generates oscillation is used. The input signal processing circuit is connected to the secondary side of the transformer and connected to a rectifier diode, which is provided in a path for current flowing through the rectifier diode, and has a power supply voltage supplied from the DC power supply to the oscillation circuit. a resistor interposed in the supply path of the oscillator circuit, which generates a predetermined voltage when the bipolar pulse is input, and uses the generated voltage to reduce the voltage supplied to the input terminal of the oscillation circuit from zero potential to a negative potential; An AC NOT device that consists of a body and a friend.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7238682A JPS58187025A (en) | 1982-04-26 | 1982-04-26 | Not device used in alternating current |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7238682A JPS58187025A (en) | 1982-04-26 | 1982-04-26 | Not device used in alternating current |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58187025A true JPS58187025A (en) | 1983-11-01 |
Family
ID=13487786
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7238682A Pending JPS58187025A (en) | 1982-04-26 | 1982-04-26 | Not device used in alternating current |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58187025A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2481717A (en) * | 2010-07-01 | 2012-01-04 | Univ Manchester Metropolitan | Adders and logic gates comprising coupled oscillators |
-
1982
- 1982-04-26 JP JP7238682A patent/JPS58187025A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2481717A (en) * | 2010-07-01 | 2012-01-04 | Univ Manchester Metropolitan | Adders and logic gates comprising coupled oscillators |
US8928353B2 (en) | 2010-07-01 | 2015-01-06 | Manchester Metropolitan University | Binary half-adder using oscillators |
GB2481717B (en) * | 2010-07-01 | 2017-09-13 | Manchester Metropolitan Univ | Binary half-adder and other logic circuits |
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