JPS58186948A - Dielectric-isolated semiconductor substrate and manufacture thereof - Google Patents
Dielectric-isolated semiconductor substrate and manufacture thereofInfo
- Publication number
- JPS58186948A JPS58186948A JP6865882A JP6865882A JPS58186948A JP S58186948 A JPS58186948 A JP S58186948A JP 6865882 A JP6865882 A JP 6865882A JP 6865882 A JP6865882 A JP 6865882A JP S58186948 A JPS58186948 A JP S58186948A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- substrate
- solution
- dielectric film
- liquid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Abstract
Description
【発明の詳細な説明】
本発明は、性能が良好で、製造が簡単な、誘電体分離し
た半導体基板及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dielectrically isolated semiconductor substrate that has good performance and is easy to manufacture, and a method for manufacturing the same.
従来、このような誘電体分離基板の製造は８１基板にエ
ツチングあるいは機械加工等によｐｖ字溝を設け、次い
で誘電体である５ｉ０２膜を熱酸化法により１字溝の表
面に形成した後、ＣｖＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏ
ｕｒ Ｄｅｐｏｓｉｔｉｏｎ）法により誘電体膜上に多
結晶８１ヲ堆積させていた。そして、この多結晶Ｓｉを
Ｓｉ基板保持体として用い、その後の工程である研摩、
素子形成などを行っていた。Conventionally, such a dielectric isolation substrate was manufactured by forming a PV-shaped groove on an 81 substrate by etching or machining, and then forming a dielectric 5i02 film on the surface of the 1-shaped groove by thermal oxidation. CvD (Chemical Vapo)
Polycrystalline 81 was deposited on the dielectric film by the ur deposition method. Then, using this polycrystalline Si as a Si substrate holder, the subsequent steps of polishing and
They were involved in element formation, etc.
しかしながら、ＣＶＤ法による多結晶Ｓ１の堆積は堆積
速度が数μｍ／分程度と非常に遅い。一般に基板保持体
となる多結晶Ｓ１の厚さは３００μｍ〜４００μｍ程度
必要なため、この方法では製造に多くの時間を要する欠
点があった。また、ＣＶＤ法は大損りで非常に高価な装
置を必要とし、誘電体分離した半導体基板が非常に高価
なものとなる原因の一つになっていた。However, the deposition rate of polycrystalline S1 by the CVD method is very slow, on the order of several μm/min. Generally, the thickness of the polycrystalline S1 serving as the substrate holder is required to be about 300 μm to 400 μm, so this method has the drawback that it requires a lot of time to manufacture. Furthermore, the CVD method requires a large amount of waste and very expensive equipment, which is one of the reasons why dielectrically isolated semiconductor substrates become very expensive.
本発明は、これらの欠点を解決するために５ｉ０２
の超微粒子が結合剤として機能することを利用すること
により、高速度でしかも簡単な装置で作製できる、誘電
体分離した半導体基板及びその製造方法を提供するにあ
る。The present invention aims to solve these drawbacks in accordance with 5i02
An object of the present invention is to provide a dielectrically separated semiconductor substrate and a method for manufacturing the same, which can be manufactured at high speed and with a simple device by utilizing the fact that the ultrafine particles of the present invention function as a binder.
すなわち、本発明を概説すれば、本発明の第１の発明（
半導体基板の発明）は、誘電体膜を施した溝を有する半
導体基板の溝部に、けい素像粒子、又は非金属酸化物微
粒子を、５ｉＯ１の超微粒子を結合剤として用いて被覆
しだ構造の保持体を有することを特徴とする誘導体分離
した半導体基板に関する。That is, if the present invention is summarized, the first invention of the present invention (
The semiconductor substrate invention) has a structure in which silicon image particles or non-metal oxide fine particles are coated on the grooves of a semiconductor substrate having grooves coated with a dielectric film using ultrafine particles of 5iO1 as a binder. The present invention relates to a dielectric-separated semiconductor substrate characterized by having a holder.
また、本発明の第２の発明（半導体基板の製造方法の発
明）は、テトラアルキルオルソシリケート又はその初期
縮合物を加水分解して得られる液体中に、けい素又は非
金属酸化物の微粒子を分散しだ液状体中で、誘電体膜を
施した溝を有する半導体基板を浸漬処理し、その後膣基
板を乾燥及び焼結することを特徴とする誘電体分離した
半導体基板の製造方法に関する。In addition, the second invention of the present invention (invention of a method for manufacturing a semiconductor substrate) includes fine particles of silicon or nonmetal oxide in a liquid obtained by hydrolyzing a tetraalkyl orthosilicate or an initial condensate thereof. The present invention relates to a method for producing a dielectric-separated semiconductor substrate, which comprises immersing a semiconductor substrate having grooves coated with a dielectric film in a dispersed liquid, and then drying and sintering the substrate.
以下、本発明を添付図面に基づいて具体的に説明する。Hereinafter, the present invention will be specifically explained based on the accompanying drawings.
第１図は、本発明の誘電体分離した半導体基板の一例を
示す断面図である。第１図において１は深さ５０μｍの
７字溝を形成した８１基板、２は熱酸化により形成され
たシリコン酸化膜（Ｓ１０□）（誘電体）、６は超微粒
子の８１０２とＳｌ又は非金属酸化物の微粒子とが互い
に強力に結合した保持体である。まだ第２図は、本発明
の製造方法における浸漬処理工程の一実施の態様を示す
断面概要図である。第２図において、１及び２は第１図
と同義、４はＳｉＯ□の超微粒子、５は５ｉ０２の微粒
子、６は該超微粒子及び微粒子を含む液状体、７は容器
、８は真空ポンプを表す。FIG. 1 is a sectional view showing an example of a dielectrically isolated semiconductor substrate of the present invention. In Figure 1, 1 is an 81 substrate with a 7-shaped groove with a depth of 50 μm formed, 2 is a silicon oxide film (S10□) (dielectric material) formed by thermal oxidation, and 6 is ultrafine particle 8102 and Sl or nonmetal. It is a carrier in which fine oxide particles are strongly bonded to each other. FIG. 2 is a schematic cross-sectional view showing an embodiment of the immersion treatment step in the manufacturing method of the present invention. In Figure 2, 1 and 2 have the same meanings as in Figure 1, 4 is an ultrafine particle of SiO□, 5 is a fine particle of 5i02, 6 is a liquid containing the ultrafine particle and the fine particle, 7 is a container, and 8 is a vacuum pump. represent.
本発明において、半導体基板上の溝の形には、例えば、
Ｖ字型及びＵ字型等があるが、満作製の容易さ及びその
後の操作の良好さからＶ字型であるのが最適である。In the present invention, the shape of the groove on the semiconductor substrate includes, for example,
Although there are V-shape and U-shape, the V-shape is most suitable because of ease of full production and ease of subsequent operation.
５１０２超微粒子を含有する液体は、テトラアルキルオ
ルソシリケート（例えばテトラエチルオルソシリケート
）、又はその初期縮合物であるアルキルシリケート（例
えばエチルシリケート）等を加水分解することによって
得られる。結合剤である該５ｉ０２超微粒子の大きさは
６〜１００×１０−３μｍ程度である。A liquid containing 5102 ultrafine particles can be obtained by hydrolyzing a tetraalkyl orthosilicate (eg, tetraethyl orthosilicate) or an alkyl silicate (eg, ethyl silicate) that is an initial condensate thereof. The size of the 5i02 ultrafine particles that are the binder is about 6 to 100 x 10 -3 μm.
それに対して、けい素像粒子又は５１０２、Ｂ２Ｏ３若
しくはＰ２Ｏ５等の非金属酸化物の微粒子の大きさは１
μｍ 前後で最小０．１μｍ程度である。In contrast, the size of silicon image particles or fine particles of nonmetal oxides such as 5102, B2O3, or P2O5 is 1
The minimum value is around 0.1 μm.
前記加水分解では、反応を促進させるために、必要に応
じて酸を混入させてもよい。In the hydrolysis, an acid may be mixed as necessary to accelerate the reaction.
また、該液体と微粒子との配合比は、使用強度に応じて
自由に変えることができる。その配合比によっては、浸
漬処理における減圧脱泡工程を省略することもできる。Further, the blending ratio of the liquid and the fine particles can be freely changed depending on the strength of use. Depending on the blending ratio, the vacuum degassing step in the immersion treatment can be omitted.
以下、実施例により本発明を更に具体的に説明するが、
本発明はこれに限定されるものではない。Hereinafter, the present invention will be explained in more detail with reference to Examples.
The present invention is not limited to this.
実施例
まず、８１基板にエツチングにより７字溝を形成し、そ
の後熱酸化により５１０２の誘電体膜を１〜２μｍ程度
形成する。酸化膜厚さは素子の設計条件によって決めら
れる。その後、エチルシリケート・４０（テトラエチル
オルソシリケートの縮合体〕、エタノール、水並びに濃
塩酸を水で１０倍に薄めたものを体積比４０対５２対４
対１の割合で混合して得た液体に５ｉ０２の微粒子（径
およそ０．１μｍ程度）５を配合したクリーム状の液状
体６の中に上記７字溝並びに薄い酸化膜を形成した８１
基板を浸漬し、容器７全体を真空ポンプ８により減圧し
、７字溝部に存在する気泡を取除いた後、液状体６から
引上げ乾燥させる。乾燥後、例えば空気中で１０００°
Ｃ１１時間焼結する。５１０２超微粒子４を含有する液
体に５ｉ０２の微粒子５を配合する割合を、該液体１に
対してＳ ｉ０２微粒子５を１（重量比）とした場合に
ついて実施した結果、およそ５００μｍ厚以上の強固な
保持体が形成された。Embodiment First, a 7-shaped groove is formed on a substrate 81 by etching, and then a dielectric film 5102 is formed to a thickness of about 1 to 2 .mu.m by thermal oxidation. The thickness of the oxide film is determined by the design conditions of the device. Then, ethyl silicate 40 (a condensate of tetraethyl orthosilicate), ethanol, water, and concentrated hydrochloric acid diluted 10 times with water were added in a volume ratio of 40:52:4.
81 The above-mentioned 7-shaped groove and a thin oxide film were formed in a cream-like liquid material 6 in which fine particles of 5i02 (approximately 0.1 μm in diameter) 5 were mixed in a liquid obtained by mixing at a ratio of 1:1.
The substrate is immersed, and the entire container 7 is depressurized by a vacuum pump 8 to remove air bubbles existing in the 7-shaped groove, and then pulled out from the liquid 6 and dried. After drying, e.g. 1000° in air
Sinter for C11 hours. As a result of blending 5i02 fine particles 5 into a liquid containing 5102 ultrafine particles 4, the ratio of Si02 fine particles 5 to 1 (weight ratio) of the liquid was 1 (weight ratio). A holder was formed.
既述のように、この配合比（液体対５１０２微粒子の重
駄比）は、使用強度に応じて自由に変えることができる
。そして、仁の配合比が大きい場合には粘性が小さいた
め、液状体６が溝の隔隔まで行渡り気泡が発生しないこ
とから、浸漬処理における前記減圧脱泡工程を省略する
ことができる。As mentioned above, this blending ratio (liquid to 5102 fine particles weight ratio) can be freely changed depending on the strength of use. When the blending ratio of kernels is high, the viscosity is low, so the liquid material 6 spreads to the gaps between the grooves and no air bubbles are generated, so that the vacuum degassing step in the immersion process can be omitted.
また前記実施例における８ｉ０２微粒子の代りに、８１
微粒子、又はＰ２Ｏ５若しくはＢ２Ｏ３等の非金属酸
化物の微粒子を用いることにより、保持体の強度及び膨
張率等を容易に変化させることもできる。Also, instead of the 8i02 fine particles in the above example, 81
By using fine particles or fine particles of a non-metal oxide such as P2O5 or B2O3, the strength, expansion rate, etc. of the holder can be easily changed.
更に、既述のように、加水分解で塩酸は必須要件ではな
い。しかしながら、塩酸を混入することにより、熱酸化
中１ｃｓｉ 基板表面に導入される結晶欠陥を低減化さ
せる効果（ゲッタリング効果）がある。Furthermore, as mentioned above, hydrochloric acid is not an essential requirement for hydrolysis. However, by mixing hydrochloric acid, there is an effect (gettering effect) of reducing crystal defects introduced to the surface of the 1csi substrate during thermal oxidation.
以上詳細に説明したように、本発明による誘電体分離し
た半導体基板においては、Ｓｉｎ、の超微粒子が結合剤
として作用して匹るため、半導体基板との密着性が良く
、シかも半導体基板への不純物の導入が少ない上に、高
熱処理にも十分耐えられる。また本発明は、装置構成が
簡単なもので、十分にその目的を達成するという利点も
ある。As explained in detail above, in the dielectrically separated semiconductor substrate according to the present invention, the ultrafine particles of Sin act as a binder, so the adhesion with the semiconductor substrate is good, and it is easy to bond to the semiconductor substrate. In addition to introducing fewer impurities, it can withstand high heat treatment. Further, the present invention has the advantage that the device configuration is simple and the object can be fully achieved.
第１図は、本発明の誘電体分離した半導体基板の一例を
示す断面図である。第２図は、本発明の製造方法におけ
る浸漬処理工程の一実施の態様を示す断面概要図である
。
１：Ｓ１基板 ２：誘電体膜 ６：保持体４ ： ５ｉ
０２の超微粒子 ５ ： ５ｉｎ２の微粒子 ６：液状
体 ７：容器 ８：真空ポンプ
特許出願人 日本電信電話公社
代理人中 本 宏
同 井 上 昭FIG. 1 is a sectional view showing an example of a dielectrically isolated semiconductor substrate of the present invention. FIG. 2 is a schematic cross-sectional view showing an embodiment of the immersion treatment step in the manufacturing method of the present invention. 1: S1 substrate 2: Dielectric film 6: Holder 4: 5i
02 ultrafine particles 5: 5in2 microparticles 6: Liquid 7: Container 8: Vacuum pump patent applicant Nippon Telegraph and Telephone Public Corporation agent Hirotoshi Moto Akira Inoue
Claims (1)
、けい素像粒子、又は非金属酸化物微粒子’６．５ｉｎ
２ の超微粒子を結合剤として用いて被覆した構造の
保持体を有することを特徴とする誘導体分離した半導体
基板。 ２、 テトラアルキルオルソシリケート又はその初期縮
合物を加水分解して得られる液体中に、けい素又は非金
属酸化物の微粒子を分散した液状体中で、誘電体膜を施
した溝を有する半導体基板を浸漬処理し、その後肢基板
を乾燥及び焼結することを特徴とする誘電体分離した半
導体基板の製造方法。 ３、 該半導体基板の浸漬処理が、全体を減圧して脱泡
することによって行うものである特許請求の範囲第２項
に記載の誘電体分離した半導体基板の製造方法。[Claims] 1. Silicon image particles or non-metal oxide fine particles of 6.5 inches are placed in the grooves of a semiconductor substrate coated with a dielectric film and having grooves.
2. A derivatized semiconductor substrate characterized by having a holder having a structure coated with the ultrafine particles of Item 2 as a binder. 2. A semiconductor substrate having grooves coated with a dielectric film in a liquid obtained by hydrolyzing a tetraalkyl orthosilicate or an initial condensate thereof, in which fine particles of silicon or nonmetal oxide are dispersed. 1. A method for manufacturing a dielectrically separated semiconductor substrate, which comprises subjecting the hindlimb substrate to a dipping treatment, and drying and sintering the hindlimb substrate. 3. The method for manufacturing a dielectrically separated semiconductor substrate according to claim 2, wherein the immersion treatment of the semiconductor substrate is carried out by degassing the entire substrate by reducing the pressure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6865882A JPS58186948A (en) | 1982-04-26 | 1982-04-26 | Dielectric-isolated semiconductor substrate and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6865882A JPS58186948A (en) | 1982-04-26 | 1982-04-26 | Dielectric-isolated semiconductor substrate and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58186948A true JPS58186948A (en) | 1983-11-01 |
| JPH0432544B2 JPH0432544B2 (en) | 1992-05-29 |
Family
ID=13380015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6865882A Granted JPS58186948A (en) | 1982-04-26 | 1982-04-26 | Dielectric-isolated semiconductor substrate and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58186948A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996024163A1 (en) * | 1995-02-01 | 1996-08-08 | The Whitaker Corporation | Process for producing a glass-coated article and article produced thereby |
-
1982
- 1982-04-26 JP JP6865882A patent/JPS58186948A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996024163A1 (en) * | 1995-02-01 | 1996-08-08 | The Whitaker Corporation | Process for producing a glass-coated article and article produced thereby |
| US5639325A (en) * | 1995-02-01 | 1997-06-17 | The Whitaker Corporation | Process for producing a glass-coated article |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0432544B2 (en) | 1992-05-29 |
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