JPS58186940A - Preparation of semiconductor apparatus - Google Patents

Preparation of semiconductor apparatus

Info

Publication number
JPS58186940A
JPS58186940A JP57068926A JP6892682A JPS58186940A JP S58186940 A JPS58186940 A JP S58186940A JP 57068926 A JP57068926 A JP 57068926A JP 6892682 A JP6892682 A JP 6892682A JP S58186940 A JPS58186940 A JP S58186940A
Authority
JP
Japan
Prior art keywords
oxide film
boron
ambient
concentration
thermal processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57068926A
Other languages
Japanese (ja)
Inventor
Shoichi Kitane
北根 正一
Kiyoshi Wakashima
若島 清
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57068926A priority Critical patent/JPS58186940A/en
Publication of JPS58186940A publication Critical patent/JPS58186940A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent lowering of impurity concentration at the surface of boron diffusion region surface and also prevent deterioration of reverse current reduction effect and deterioration after life test. CONSTITUTION:A P type region is formed as a base 12 by diffusing P type impurity to the internal surface of an N type silicon substrate 11, and an N type region is formed as an emitter 13 by diffusing an N type impurity, for example, boron to a part of internal surface. An oxide film 14 is formed by executing thermal processing in the oxygen gas ambient and then annealing is carried out by changing the ambient condition to inactive gas, for example, to the nitrogen gas ambient. A power transistor is formed by forming a base electrode 16 and emitter electrode 17. A lowered concentration at the surface of boron diffused layer is recovered by additionally executing the thermal processing under the inactive gas ambient within the same furnace at the same or higher temperature immediately after the thermal processing under the acidic ambient.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体装置の製造方法に係り、特にボロン拡
散層を有する半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a boron diffusion layer.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

通常のプレーナ形P−N接合の表面保護膜に対して次の
ような性質が要求されている。
The following properties are required for the surface protective film of a normal planar PN junction.

■絶縁性が良好で電気的安定性が良いこと、■分極が小
さいこと、■膜欠陥が少ないこと、■不純物の拡散に対
するブロック性が良いこと、■耐湿性が良いこと、■下
地材質の密着性が良いこと、■低ストレス性の膜である
こと、■膜中の不純物含有量が少ないこと、■界面電荷
密度が小さいこと、[株]物巡的、化学的、機械的に安
定性が良いことなどである。これらの要求項目に対して
種々の物質が種々の形成方法によって検討され、実施さ
れているが、一般的に上記要求項目をほぼ満足し、合理
的かつ容易に形成されるシリコン酸化膜が使用されてい
る。このシリコン酸化膜の形成方法には ■ 高温酸化の乾燥、ウェット酸素雰囲気中でのシリコ
ンとの反応による81−$−0,→810゜■ スチー
ム雰囲気中でのシリコンとの反応による8 + +2H
* 0→810.+2H。
■ Good insulation and electrical stability, ■ Small polarization, ■ Few film defects, ■ Good blocking properties against diffusion of impurities, ■ Good moisture resistance, ■ Adhesion to base material. ■Low-stress membrane; ■Low impurity content in the membrane; ■Low interfacial charge density; Physically, chemically, and mechanically stable. It's a good thing. Various materials have been studied and implemented using various formation methods to meet these requirements, but in general, silicon oxide films are used, which mostly satisfy the above requirements and can be formed rationally and easily. ing. The method for forming this silicon oxide film includes: ■ Drying of high temperature oxidation, reaction with silicon in a wet oxygen atmosphere to 81-$-0,→810° ■ Reaction with silicon in a steam atmosphere to 8 + +2H
*0→810. +2H.

■ 水素と酸素の混合ガス中でのシリコンとの反応によ
るH、 −4−)0.→馬0.2H,O+81→840
t−1−2H。
■H by reaction with silicon in a mixed gas of hydrogen and oxygen, -4-)0. → Horse 0.2H, O+81 → 840
t-1-2H.

■ この雰囲気の中にHclを混合した方法■ 低温酸
化のCVD法によるモノシランと酸素の反応8iH4−
)0.→8i0.+2Htの堆積法によるシリコン酸化
膜の形成法 などがある。
■ Method of mixing HCl in this atmosphere ■ Reaction of monosilane and oxygen using low temperature oxidation CVD method 8iH4-
)0. →8i0. There is a method of forming a silicon oxide film using a +2Ht deposition method.

これらの方法の中で一般に常用されている方法は、高温
酸化法のスチーム雰囲気中での酸化膜の形成である。他
方、低温酸化のCVD法により形成した酸化膜は、高温
酸化法により形成した酸化膜に比し、厚さの厚い酸化膜
が容易に形成される利点を有するが、低温がゆえに膜密
度が粗であり、耐湿性も劣り、耐薬品性も60程度と弱
く、安定な表面保護膜としては不適当である。しかし、
仮りに表面保護膜として適用されるには、1000℃以
上の高温処理を行って高温酸化法による酸化膜並の膜厚
にする必要がある。しかし、この様な工程増加の方法を
採用するよりも、酸化膜形成時間が多少長くても簡便で
生産性の良い合理的な高温酸化法のスチーム雰囲気中で
の酸化膜形成が多用されるゆえんと思われる。
Among these methods, a commonly used method is a high temperature oxidation method in which an oxide film is formed in a steam atmosphere. On the other hand, an oxide film formed by a low-temperature oxidation CVD method has the advantage that a thick oxide film can be easily formed compared to an oxide film formed by a high-temperature oxidation method, but the film density is rough due to the low temperature. It has poor moisture resistance and weak chemical resistance of about 60, making it unsuitable as a stable surface protective film. but,
If it were to be used as a surface protective film, it would need to be treated at a high temperature of 1000° C. or higher to achieve a film thickness comparable to that of an oxide film produced by high-temperature oxidation. However, rather than adopting such a method of increasing the number of steps, oxide film formation in a steam atmosphere is often used, which is a simple and highly productive high-temperature oxidation method, even if the oxide film formation time is a little longer. I think that the.

第1図はボロン不純物拡散層を有する半導体素子(ダイ
オード)を示している。すなわち、N形シリコン基板1
の一面側内表面にボロン不純物を拡散したP影領域2を
形成してP−N接合を形成し、この表面に前記高温酸化
法を用いスチーム雰囲気中で表面保護膜としてv9コン
酸化膜3を形成し、さらにその表面上に第2の表面保護
膜としてシリコン酸化膜4を形成しである。このような
半導体素子には次のような問題がある。すなわち、v9
コンとの反応による酸化膜の形成は、ボロン不純物を拡
散した形成層の表面不純物濃度が低下する現象が起る。
FIG. 1 shows a semiconductor element (diode) having a boron impurity diffusion layer. That is, N-type silicon substrate 1
A P shadow region 2 in which boron impurities are diffused is formed on the inner surface of one side to form a P-N junction, and a V9 Con oxide film 3 is formed on this surface as a surface protective film in a steam atmosphere using the high temperature oxidation method. Then, a silicon oxide film 4 is formed as a second surface protection film on the surface. Such semiconductor devices have the following problems. That is, v9
When an oxide film is formed by the reaction with silicon, a phenomenon occurs in which the surface impurity concentration of the formed layer in which boron impurities are diffused decreases.

この現象は、シリコン基板表面のボロン濃度が酸化膜中
に吸い出され、低下することであるが、そのP影領域2
の深さ方向の不純物濃度分布は182図の曲線Aで示す
分布となる。すなわち、酸化膜4形成後の酸化膜中のボ
ロン濃度に対するシリコン基板1中のP影領域2の表面
濃度の比は0.3以下である。このような不純物濃度の
ダイオードやトランジスタは、表面保l[′Ws中にト
ラップされたナトリューム(Na)などのアルカリイオ
ンの1譬によって、Vリコン表面のボロン濃度低下領域
が反転したり外部汚染の悪影響をもろに受けたりして、
P−N接合に逆バイアスした場合、第3図の曲線Cで示
すようにリバース電流の増加を招来する問題がある。さ
らに、寿命試験後のリバース電流の初期値に対する変動
率が第4図のX印で示す特性のように大さくなったりし
て、信頼性の劣化を生ずる欠点がある。
This phenomenon is that the boron concentration on the silicon substrate surface is sucked out into the oxide film and decreases, but the P shadow area 2
The impurity concentration distribution in the depth direction is the distribution shown by curve A in Figure 182. That is, the ratio of the surface concentration of the P shadow region 2 in the silicon substrate 1 to the boron concentration in the oxide film after the oxide film 4 is formed is 0.3 or less. In diodes and transistors with such impurity concentrations, the region of reduced boron concentration on the V recon surface may be reversed due to alkaline ions such as sodium (Na) trapped in the surface storage l['Ws, or external contamination may occur. Due to negative influences,
When the PN junction is reverse biased, there is a problem in that the reverse current increases as shown by curve C in FIG. Furthermore, there is a drawback that the rate of variation of the reverse current with respect to the initial value after the life test becomes large as shown by the X mark in FIG. 4, resulting in deterioration of reliability.

〔発明の目的〕[Purpose of the invention]

この発明は上記事情に鑑みてなされたもので、その目的
とするところは、ボロン拡散領域上に酸化膜を形成した
後のシリコン表面不純物濃度の低下を極少にし、リバー
ス電流が小さく、かつ寿命試験後でも劣下の少ない安定
した特性が得られる半導体装置の製造方法を提供するこ
とにある。
This invention was made in view of the above circumstances, and its objectives are to minimize the decrease in the silicon surface impurity concentration after forming an oxide film on the boron diffusion region, to reduce the reverse current, and to reduce the lifetime test. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can obtain stable characteristics with little deterioration even after the manufacturing process.

〔発明の概要〕[Summary of the invention]

この発明は、半導体基板の内表面にボロン拡散領域を形
成し、表面に酸化膜を形成した後不活性ガス、たとえば
窒素ガス雰囲気中で熱J6理することにより、ボロン拡
散領域表面での不純物濃度の低下を防止し、リバース電
流の減少効果や寿命試験後の劣下特性を防止するように
したものである。
This invention forms a boron diffusion region on the inner surface of a semiconductor substrate, forms an oxide film on the surface, and then heats it in an inert gas atmosphere, such as nitrogen gas, to increase the impurity concentration on the surface of the boron diffusion region. This prevents a decrease in the reverse current and prevents deterioration of characteristics after a life test.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例について図面を参照して説明
する。なお、この実施例はメディアムパワーNPN )
ランジスタの製造に適用した場合である。第5図におい
て、−導電形半導体基板たとえばN形シリコン基板11
の内表面にP形不純物を拡散してP影領域を形成し、こ
れをベース12として用いる。このペース12の領域の
一部内表面にN形不純物たとえばボロンを拡散してN影
領域を形成し、これをエミッタ13として用いる。次に
、表面に酸化Il!14を形成する。
An embodiment of the present invention will be described below with reference to the drawings. Note that this example uses medium power NPN)
This is a case where it is applied to the manufacture of transistors. In FIG. 5, a − conductivity type semiconductor substrate, for example, an N type silicon substrate 11
A P-type impurity is diffused on the inner surface of the substrate to form a P shadow region, which is used as the base 12. An N-type impurity, such as boron, is diffused into a part of the inner surface of the region of the paste 12 to form an N shadow region, which is used as the emitter 13. Next, oxidized Il! on the surface! form 14.

すなわち、スチーム状の酸素ガス雰囲気中で30分間程
度1000℃の熱処理を行うことにより酸化膜を形成し
、しかるのち追加熱処理を行う。すなわち、スチーム状
の酸素ガスの雰囲気を不活性ガスたとえば窒素ガス雰囲
気に切換えて900℃で20分間のアニールを行う。こ
のアニール処理を行った後、ペース12およびエミッタ
13の゛電極を取出すため、前記酸化膜14を選択エツ
チングする。次に、基板の表裏面に電極形成のため金属
層たとえばA1層を形成し、選択エツチングしてコレク
タ電極15、ペース電極16およびエミッタ電極11を
それぞれ形成してパワートランジスタを構成する。
That is, an oxide film is formed by performing heat treatment at 1000° C. for about 30 minutes in a steam-like oxygen gas atmosphere, and then additional heat treatment is performed. That is, the steam-like oxygen gas atmosphere is changed to an inert gas atmosphere, such as nitrogen gas atmosphere, and annealing is performed at 900° C. for 20 minutes. After this annealing process, the oxide film 14 is selectively etched in order to take out the electrodes of the paste 12 and emitter 13. Next, a metal layer, for example, an A1 layer, is formed on the front and back surfaces of the substrate for forming electrodes, and selectively etched to form a collector electrode 15, a space electrode 16, and an emitter electrode 11, respectively, thereby forming a power transistor.

このように構成したパワートランジスタは初特性でのI
Cll0のバラツキが小さくなり、かつ寿命試峡後のI
CBOの変動幅が小さくなる特性が得られる。また、酸
化膜14の形成法として、1000℃のスチーム酸化工
程および1000℃でHcl→−0童の雰囲気での酸化
工程の後、基板肩囲の雰囲気を窒素ガス雰囲気に切換え
て900℃20分間のアニールを行う方法を用いてパワ
ートランジスタを形成することにより、第2図曲線Bの
ボロン拡散層の不純物濃度プロファイルに示されるよう
に、従来の製法によるプロファイルに比べ表面濃度が持
上り−化、−X100>0.5の値が得られる。実測値
で0.76のものが得られている。その結果、第3図に
破線りで示すように初特性のリバース電流(ICBO)
の値が小さくなり、かつバラツキも小さくなり、168
時間の寿命試験後のリバース電流(Icmo )の変動
幅も、第4図に○印で示すように大きく変動(劣化)す
るものがなくなり、変動幅も小さくなった。実際の量産
において不良が従来のへ程度に減少した。
The power transistor configured in this way has an initial characteristic of I
The variation in Cll0 becomes smaller and the I after the life test
A characteristic in which the fluctuation range of CBO is reduced can be obtained. In addition, as a method for forming the oxide film 14, after a steam oxidation process at 1000°C and an oxidation process at 1000°C in an atmosphere of HCl→-0, the atmosphere around the substrate shoulder area was changed to a nitrogen gas atmosphere, and the atmosphere was heated at 900°C for 20 minutes. By forming a power transistor using the annealing method, as shown in the impurity concentration profile of the boron diffusion layer shown in curve B in Figure 2, the surface concentration is raised compared to the profile obtained by the conventional manufacturing method. A value of -X100>0.5 is obtained. An actual value of 0.76 was obtained. As a result, as shown by the broken line in Figure 3, the initial characteristic reverse current (ICBO)
The value of becomes smaller and the variation becomes smaller, 168
The fluctuation width of the reverse current (Icmo) after the time life test also became small, with no large fluctuations (deterioration) as shown by the circles in FIG. 4. In actual mass production, defects have been reduced to the same level as before.

以上説明したように、ボロン拡散層の表面の濃度低下を
酸化性雰囲気中での熱処理直後に、同一炉内で同一温度
もしくはそれ以上の温度で不活性ガス雰囲気中で熱処理
(アニール)を追加して行い1回復させることによって
、初特性および寿命試験後のリバース電流を小さく、か
つ劣下のきわめて小さい安定な半導体装置の製造方法を
得ることができる。
As explained above, immediately after heat treatment in an oxidizing atmosphere, heat treatment (annealing) in an inert gas atmosphere at the same temperature or higher is added in the same furnace to reduce the concentration on the surface of the boron diffusion layer. By performing one recovery, it is possible to obtain a stable method for manufacturing a semiconductor device in which the initial characteristics and the reverse current after the life test are small, and the deterioration is extremely small.

この発明の方法により表面不純物濃度低下の同道効果を
有する理由は、不純物拡散の基本原理に基づ<1眼であ
り、表rkI濃度低下要因の酸化性雰囲気を遍断し、不
活性ガスたとえば窒素雰囲気に切換えて調温熱処理を追
加することにより、シリコン基板内に拡散されたボロン
不純物の量が濃度の高いところから低いところへ再分布
し、不純物濃度のピーク値は若干低下し、低ドしていた
表面濃度は充埴させる形で−F昇(回復)することにな
ると思われる。
The reason why the method of this invention has the same effect of reducing the surface impurity concentration is that it is based on the basic principle of impurity diffusion, and the oxidizing atmosphere, which is a factor in reducing the rkI concentration, is traversed, and an inert gas such as nitrogen is used. By switching to the atmosphere and adding temperature-controlled heat treatment, the amount of boron impurities diffused into the silicon substrate is redistributed from areas with high concentration to areas with low concentration, and the peak value of the impurity concentration decreases slightly, resulting in a lower concentration of boron. It is thought that the surface concentration that had been present will rise (recover) in the form of -F filling.

なお、前記実施例では、酸化膜形成手段としてスチーム
酸化の方法について説明したが、酸化膜形成手段であれ
ば何れでもよい。また、窒素ガス雰囲気中で酸化膜形成
後の追加熱処理を行った例について説明したが、不活性
ガスであれば何れでもよい、さらに、追加熱処理時間は
In the above embodiments, a steam oxidation method was used as an oxide film forming means, but any method may be used as long as it is an oxide film forming means. Further, although an example has been described in which additional heat treatment is performed after forming an oxide film in a nitrogen gas atmosphere, any inert gas may be used.Furthermore, the additional heat treatment time may be determined using any inert gas.

所定の拡散層の接合位置が特性に影響を与えない範囲で
設定されなければならない。
The bonding position of a predetermined diffusion layer must be set within a range that does not affect the characteristics.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、ボロン拡散領域上
に酸化膜を形成した後のV9コン表が小さく、かつ寿命
試験後でも劣下の少ない安定した特性が得られる半導体
装置の製造方法を提供できる。
As explained above, according to the present invention, a method for manufacturing a semiconductor device is provided in which the V9 surface after forming an oxide film on a boron diffusion region is small and stable characteristics with little deterioration even after a life test are obtained. Can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の製法によるボロン拡散層を有する半導体
素子(ダイオード)を説明するための構造断面図、第2
図は本発明方法および従来法によるボロン拡散層の表面
における不純物濃度の分布状態を示す特性曲線図、第3
図は第2図の特性によりリバース電流の便化の様子を従
来および本発明方法と比較して示す特性曲線図。 第4図は第3図のリバース電流特性について寿命試岐後
の変化の様子を従来および本発明方法と比較して示す特
性曲線図、第5図は本発明方法をパワートランジスタの
製法に適用した実施例を説明するための構造断面図であ
る。 11・・・N形シリコン基板、12・・・P影領域、1
3・・・N影領域、14・・・酸化膜、15・・・コレ
クタ゛4!権、16・・・ベース電極、17・・・エミ
ッタ電極。
Figure 1 is a structural cross-sectional view for explaining a semiconductor element (diode) having a boron diffusion layer manufactured by a conventional manufacturing method.
The figure is a characteristic curve diagram showing the distribution state of impurity concentration on the surface of the boron diffusion layer according to the method of the present invention and the conventional method.
The figure is a characteristic curve diagram showing how the reverse current is simplified by the characteristic shown in FIG. 2 in comparison with the conventional method and the method of the present invention. Fig. 4 is a characteristic curve diagram showing how the reverse current characteristic shown in Fig. 3 changes after the life cycle is compared with the conventional method and the method of the present invention, and Fig. 5 shows the method of the present invention applied to the manufacturing method of a power transistor. It is a structural sectional view for explaining an example. 11...N type silicon substrate, 12...P shadow area, 1
3...N shadow area, 14...Oxide film, 15...Collector ゛4! 16...Base electrode, 17...Emitter electrode.

Claims (4)

【特許請求の範囲】[Claims] (1)  ボロン拡散領域の表面上に酸化膜を形成する
に際し、高温熱処理により酸化膜を形成したのち不活性
ガス雰囲気中で熱処理することを特徴とする半導体装置
の製造方法。
(1) A method for manufacturing a semiconductor device, which comprises forming an oxide film on the surface of a boron diffusion region by forming the oxide film by high-temperature heat treatment and then heat-treating it in an inert gas atmosphere.
(2)  前記不活性ガス雰囲気は窒素ガス雰囲気であ
る特許請求の範囲第1項記載の半導体装置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the inert gas atmosphere is a nitrogen gas atmosphere.
(3)@記不活性ガス雰囲気中の熱処理は酸化膜形成炉
と同一炉で行うことを特徴とする特許請求の範囲第1項
記載の半導体装置の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment in the inert gas atmosphere is performed in the same furnace as the oxide film forming furnace.
(4)前記不活性ガス雰囲気中での熱処理は酸化膜の形
成直後に行うことを特徴とする特許請求の範囲第1項記
載の半導体装置の製造方法。
(4) The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment in the inert gas atmosphere is performed immediately after the formation of the oxide film.
JP57068926A 1982-04-24 1982-04-24 Preparation of semiconductor apparatus Pending JPS58186940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57068926A JPS58186940A (en) 1982-04-24 1982-04-24 Preparation of semiconductor apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57068926A JPS58186940A (en) 1982-04-24 1982-04-24 Preparation of semiconductor apparatus

Publications (1)

Publication Number Publication Date
JPS58186940A true JPS58186940A (en) 1983-11-01

Family

ID=13387742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57068926A Pending JPS58186940A (en) 1982-04-24 1982-04-24 Preparation of semiconductor apparatus

Country Status (1)

Country Link
JP (1) JPS58186940A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63313824A (en) * 1987-06-16 1988-12-21 Seiko Instr & Electronics Ltd Formation of silicon oxide film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63313824A (en) * 1987-06-16 1988-12-21 Seiko Instr & Electronics Ltd Formation of silicon oxide film

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